LCD Entity

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;

entity LCD is
    Port ( Clock : in  STD_LOGIC;
           Nex : in  STD_LOGIC;
           Prev : in  STD_LOGIC;
              LED : out std_logic_vector (7 downto 0);
           LCD_DB : inout  STD_LOGIC_VECTOR (7 downto 0);
           LCD_E : out  STD_LOGIC;
           LCD_RS : out  STD_LOGIC;
           LCD_RW : out  STD_LOGIC);
end LCD;

architecture Behavioral of LCD is
component LCD_Driver is
    Port ( Clock : in  STD_LOGIC;
           New_Line : in  STD_LOGIC;
           Reset : in  STD_LOGIC;
           Home_Line : in  STD_LOGIC;
           Write_Now : in  STD_LOGIC;
           Data : in  STD_LOGIC_VECTOR (7 downto 0);
              Busy : out std_logic;
           LCD_DB : out  STD_LOGIC_VECTOR (7 downto 0);
           LCD_E : out  STD_LOGIC;
           LCD_RS : out  STD_LOGIC;
           LCD_RW : out  STD_LOGIC);
end component;

signal New_Line : std_logic;
signal Reset : std_logic;
signal Home_Line : std_logic;
signal Write_Now : std_logic;
signal Data : std_logic_vector(7 downto 0);
signal Busy : std_logic;

type Vectors is array (1 downto 0) of std_logic_vector(7 downto 0);
signal abc : Vectors := (0 => "00001111", 1 => "11110000");
signal temp : std_logic_vector (7 downto 0) := abc(0);

type State_type is (Init, Print, Printb, Idle, Finish);
signal State : State_type := Init;

signal counter : integer range 0 to 50000000;
signal pointer : std_logic_vector(7 downto 0) := x"00";
begin

    drv : LCD_Driver port map(Clock => Clock, New_Line => New_Line, Reset => Reset, Busy => Busy,
                                        Home_Line => Home_Line, Write_Now => Write_Now, Data => Data, LCD_DB => LCD_DB,
                                        LCD_E => LCD_E, LCD_RS => LCD_RS, LCD_RW => LCD_RW);

end Behavioral;