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| 1 | - | /* BCM6348 /* |
| 1 | + | /* BCM6348 */ |
| 2 | u32 val; | |
| 3 | /* Enable Extra SPI CS */ | |
| 4 | /* GPIO 29 is SSx FIXME */ | |
| 5 | val = bcm_gpio_readl(GPIO_MODE_REG); | |
| 6 | val |= GPIO_MODE_6348_G1_SPI_MASTER; | |
| 7 | bcm_gpio_writel(val, GPIO_MODE_REG); | |
| 8 | ||
| 9 | - | /* BCM6358 /* |
| 9 | + | /* BCM6358 */ |
| 10 | u32 val; | |
| 11 | /* Enable Overlay for SPI SS Pins */ | |
| 12 | val = bcm_gpio_readl(GPIO_MODE_REG); | |
| 13 | val |= GPIO_MODE_6358_EXTRA_SPI_SS; | |
| 14 | bcm_gpio_writel(val, GPIO_MODE_REG); | |
| 15 | /* Enable SPI Slave Select as Output Pins */ | |
| 16 | /* GPIO 32 is SS2, GPIO 33 is SS3 */ | |
| 17 | val = bcm_gpio_readl(GPIO_CTL_HI_REG); | |
| 18 | val |= 0x0003 | |
| 19 | bcm_gpio_writel(val, GPIO_CTL_HI_REG); | |
| 20 | ||
| 21 | - | /* BCM6368 /* |
| 21 | + | /* BCM6368 */ |
| 22 | u32 val; | |
| 23 | /* Enable Extra SPI CS */ | |
| 24 | val = bcm_gpio_readl(GPIO_MODE_REG); | |
| 25 | val |= (GPIO_MODE_6368_SPI_SSN2 | GPIO_MODE_6368_SPI_SSN3 | GPIO_MODE_6368_SPI_SSN4 | GPIO_MODE_6368_SPI_SSN5); | |
| 26 | bcm_gpio_writel(val, GPIO_MODE_REG); | |
| 27 | /* Enable SPI Slave Select as Output Pins */ | |
| 28 | /* GPIO 28 is SS2, GPIO 29 is SS3, GPIO 30 is SS4, GPIO 31 is SS5*/ | |
| 29 | val = bcm_gpio_readl(GPIO_CTL_HI_REG); | |
| 30 | val |= (GPIO_MODE_6368_SPI_SSN2 | GPIO_MODE_6368_SPI_SSN3 | GPIO_MODE_6368_SPI_SSN4 | GPIO_MODE_6368_SPI_SSN5); | |
| 31 | bcm_gpio_writel(val, GPIO_CTL_HI_REG); |
