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omap-serial.c support rs485

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  1. /*
  2. * Driver for OMAP-UART controller.
  3. * Based on drivers/serial/8250.c
  4. *
  5. * Copyright (C) 2010 Texas Instruments.
  6. *
  7. * Authors:
  8. * Govindraj R <govindraj.raja@ti.com>
  9. * Thara Gopinath <thara@ti.com>
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2 of the License, or
  14. * (at your option) any later version.
  15. *
  16. * Note: This driver is made separate from 8250 driver as we cannot
  17. * over load 8250 driver with omap platform specific configuration for
  18. * features like DMA, it makes easier to implement features like DMA and
  19. * hardware flow control and software flow control configuration with
  20. * this driver as required for the omap-platform.
  21. */
  22.  
  23. #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  24. #define SUPPORT_SYSRQ
  25. #endif
  26.  
  27. #include <linux/module.h>
  28. #include <linux/init.h>
  29. #include <linux/console.h>
  30. #include <linux/serial_reg.h>
  31. #include <linux/delay.h>
  32. #include <linux/slab.h>
  33. #include <linux/tty.h>
  34. #include <linux/tty_flip.h>
  35. #include <linux/platform_device.h>
  36. #include <linux/io.h>
  37. #include <linux/clk.h>
  38. #include <linux/serial_core.h>
  39. #include <linux/irq.h>
  40. #include <linux/gpio.h>
  41. #include <linux/uaccess.h>
  42. #include <linux/pm_runtime.h>
  43. #include <linux/of.h>
  44. #include <linux/gpio.h>
  45. #include <linux/pinctrl/consumer.h>
  46. #include <linux/platform_data/serial-omap.h>
  47.  
  48. #define OMAP_MAX_HSUART_PORTS 6
  49.  
  50. #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
  51.  
  52. #define OMAP_UART_REV_42 0x0402
  53. #define OMAP_UART_REV_46 0x0406
  54. #define OMAP_UART_REV_52 0x0502
  55. #define OMAP_UART_REV_63 0x0603
  56.  
  57. #define UART_ERRATA_i202_MDR1_ACCESS BIT(0)
  58. #define UART_ERRATA_i291_DMA_FORCEIDLE BIT(1)
  59.  
  60. #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
  61.  
  62. /* SCR register bitmasks */
  63. #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
  64. #define OMAP_UART_SCR_TX_EMPTY (1 << 3)
  65.  
  66. /* FCR register bitmasks */
  67. #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6)
  68. #define OMAP_UART_FCR_TX_FIFO_TRIG_MASK (0x3 << 4)
  69.  
  70. /* MVR register bitmasks */
  71. #define OMAP_UART_MVR_SCHEME_SHIFT 30
  72.  
  73. #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0
  74. #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4
  75. #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f
  76.  
  77. #define OMAP_UART_MVR_MAJ_MASK 0x700
  78. #define OMAP_UART_MVR_MAJ_SHIFT 8
  79. #define OMAP_UART_MVR_MIN_MASK 0x3f
  80.  
  81. #define OMAP_UART_DMA_CH_FREE -1
  82.  
  83. #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
  84. #define OMAP_MODE13X_SPEED 230400
  85.  
  86. /* WER = 0x7F
  87. * Enable module level wakeup in WER reg
  88. */
  89. #define OMAP_UART_WER_MOD_WKUP 0X7F
  90.  
  91. /* Enable XON/XOFF flow control on output */
  92. #define OMAP_UART_SW_TX 0x08
  93.  
  94. /* Enable XON/XOFF flow control on input */
  95. #define OMAP_UART_SW_RX 0x02
  96.  
  97. #define OMAP_UART_SW_CLR 0xF0
  98.  
  99. #define OMAP_UART_TCR_TRIG 0x0F
  100.  
  101. struct uart_omap_dma {
  102. u8 uart_dma_tx;
  103. u8 uart_dma_rx;
  104. int rx_dma_channel;
  105. int tx_dma_channel;
  106. dma_addr_t rx_buf_dma_phys;
  107. dma_addr_t tx_buf_dma_phys;
  108. unsigned int uart_base;
  109. /*
  110. * Buffer for rx dma.It is not required for tx because the buffer
  111. * comes from port structure.
  112. */
  113. unsigned char *rx_buf;
  114. unsigned int prev_rx_dma_pos;
  115. int tx_buf_size;
  116. int tx_dma_used;
  117. int rx_dma_used;
  118. spinlock_t tx_lock;
  119. spinlock_t rx_lock;
  120. /* timer to poll activity on rx dma */
  121. struct timer_list rx_timer;
  122. unsigned int rx_buf_size;
  123. unsigned int rx_poll_rate;
  124. unsigned int rx_timeout;
  125. };
  126.  
  127. struct uart_omap_port {
  128. struct uart_port port;
  129. struct uart_omap_dma uart_dma;
  130. struct device *dev;
  131.  
  132. unsigned char ier;
  133. unsigned char lcr;
  134. unsigned char mcr;
  135. unsigned char fcr;
  136. unsigned char efr;
  137. unsigned char dll;
  138. unsigned char dlh;
  139. unsigned char mdr1;
  140. unsigned char scr;
  141.  
  142. int use_dma;
  143. /*
  144. * Some bits in registers are cleared on a read, so they must
  145. * be saved whenever the register is read but the bits will not
  146. * be immediately processed.
  147. */
  148. unsigned int lsr_break_flag;
  149. unsigned char msr_saved_flags;
  150. char name[20];
  151. unsigned long port_activity;
  152. struct serial_rs485 rs485;
  153. int context_loss_cnt;
  154. u32 errata;
  155. u8 wakeups_enabled;
  156.  
  157. int DTR_gpio;
  158. int DTR_inverted;
  159. int DTR_active;
  160.  
  161. struct pm_qos_request pm_qos_request;
  162. u32 latency;
  163. u32 calc_latency;
  164. struct work_struct qos_work;
  165. struct pinctrl *pins;
  166. };
  167.  
  168. #define to_uart_omap_port(p) ((container_of((p), struct uart_omap_port, port)))
  169.  
  170. static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
  171.  
  172. /* Forward declaration of functions */
  173. static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
  174.  
  175. static struct workqueue_struct *serial_omap_uart_wq;
  176.  
  177. static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
  178. {
  179. offset <<= up->port.regshift;
  180. return readw(up->port.membase + offset);
  181. }
  182.  
  183. static inline void serial_out(struct uart_omap_port *up, int offset, int value)
  184. {
  185. offset <<= up->port.regshift;
  186. writew(value, up->port.membase + offset);
  187. }
  188.  
  189. static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
  190. {
  191. serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
  192. serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
  193. UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
  194. serial_out(up, UART_FCR, 0);
  195. }
  196.  
  197. static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
  198. {
  199. struct omap_uart_port_info *pdata = up->dev->platform_data;
  200.  
  201. if (!pdata || !pdata->get_context_loss_count)
  202. return 0;
  203.  
  204. return pdata->get_context_loss_count(up->dev);
  205. }
  206.  
  207. static void serial_omap_set_forceidle(struct uart_omap_port *up)
  208. {
  209. struct omap_uart_port_info *pdata = up->dev->platform_data;
  210.  
  211. if (!pdata || !pdata->set_forceidle)
  212. return;
  213.  
  214. pdata->set_forceidle(up->dev);
  215. }
  216.  
  217. static void serial_omap_set_noidle(struct uart_omap_port *up)
  218. {
  219. struct omap_uart_port_info *pdata = up->dev->platform_data;
  220.  
  221. if (!pdata || !pdata->set_noidle)
  222. return;
  223.  
  224. pdata->set_noidle(up->dev);
  225. }
  226.  
  227. static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
  228. {
  229. struct omap_uart_port_info *pdata = up->dev->platform_data;
  230.  
  231. if (!pdata || !pdata->enable_wakeup)
  232. return;
  233.  
  234. pdata->enable_wakeup(up->dev, enable);
  235. }
  236.  
  237. /*
  238. * serial_omap_get_divisor - calculate divisor value
  239. * @port: uart port info
  240. * @baud: baudrate for which divisor needs to be calculated.
  241. *
  242. * We have written our own function to get the divisor so as to support
  243. * 13x mode. 3Mbps Baudrate as an different divisor.
  244. * Reference OMAP TRM Chapter 17:
  245. * Table 17-1. UART Mode Baud Rates, Divisor Values, and Error Rates
  246. * referring to oversampling - divisor value
  247. * baudrate 460,800 to 3,686,400 all have divisor 13
  248. * except 3,000,000 which has divisor value 16
  249. */
  250. static unsigned int
  251. serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
  252. {
  253. unsigned int divisor;
  254.  
  255. if (baud > OMAP_MODE13X_SPEED && baud != 3000000)
  256. divisor = 13;
  257. else
  258. divisor = 16;
  259. return port->uartclk/(baud * divisor);
  260. }
  261.  
  262. static void serial_omap_enable_ms(struct uart_port *port)
  263. {
  264. struct uart_omap_port *up = to_uart_omap_port(port);
  265.  
  266. dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
  267.  
  268. pm_runtime_get_sync(up->dev);
  269. up->ier |= UART_IER_MSI;
  270. serial_out(up, UART_IER, up->ier);
  271. pm_runtime_mark_last_busy(up->dev);
  272. pm_runtime_put_autosuspend(up->dev);
  273. }
  274. static inline void wait_for_xmitr(struct uart_omap_port *up);
  275. static void serial_omap_stop_tx(struct uart_port *port)
  276. {
  277. struct uart_omap_port *up = to_uart_omap_port(port);
  278.  
  279. pm_runtime_get_sync(up->dev);
  280. if (up->ier & UART_IER_THRI) {
  281. up->ier &= ~UART_IER_THRI;
  282. serial_out(up, UART_IER, up->ier);
  283. }
  284. wait_for_xmitr(up);
  285. if (up->rs485.flags & SER_RS485_ENABLED) {
  286. /* Disable RS485 TX EN */
  287. int val = (up->rs485.flags & SER_RS485_RTS_AFTER_SEND) ? 1 : 0;
  288. gpio_set_value(up->rs485.gpio_pin, val);
  289. }
  290.  
  291. serial_omap_set_forceidle(up);
  292.  
  293. pm_runtime_mark_last_busy(up->dev);
  294. pm_runtime_put_autosuspend(up->dev);
  295. }
  296.  
  297. static void serial_omap_stop_rx(struct uart_port *port)
  298. {
  299. struct uart_omap_port *up = to_uart_omap_port(port);
  300. int val;
  301.  
  302. if (up->rs485.flags & SER_RS485_ENABLED) {
  303. /* Enable RS485 TX EN */
  304. val = (up->rs485.flags & SER_RS485_RTS_ON_SEND) ? 0 : 1;
  305. gpio_set_value(up->rs485.gpio_pin, val);
  306. }
  307.  
  308. pm_runtime_get_sync(up->dev);
  309. up->ier &= ~UART_IER_RLSI;
  310. up->port.read_status_mask &= ~UART_LSR_DR;
  311. serial_out(up, UART_IER, up->ier);
  312. pm_runtime_mark_last_busy(up->dev);
  313. pm_runtime_put_autosuspend(up->dev);
  314. }
  315.  
  316. static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
  317. {
  318. struct circ_buf *xmit = &up->port.state->xmit;
  319. int count;
  320.  
  321. if (!(lsr & UART_LSR_THRE))
  322. return;
  323.  
  324. if (up->port.x_char) {
  325. serial_out(up, UART_TX, up->port.x_char);
  326. up->port.icount.tx++;
  327. up->port.x_char = 0;
  328. return;
  329. }
  330. if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
  331. serial_omap_stop_tx(&up->port);
  332. return;
  333. }
  334. count = up->port.fifosize / 4;
  335. do {
  336. serial_out(up, UART_TX, xmit->buf[xmit->tail]);
  337. xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
  338. up->port.icount.tx++;
  339. if (uart_circ_empty(xmit))
  340. break;
  341. } while (--count > 0);
  342.  
  343. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
  344. spin_unlock(&up->port.lock);
  345. uart_write_wakeup(&up->port);
  346. spin_lock(&up->port.lock);
  347. }
  348.  
  349. if (uart_circ_empty(xmit))
  350. serial_omap_stop_tx(&up->port);
  351. }
  352.  
  353. static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
  354. {
  355. if (!(up->ier & UART_IER_THRI)) {
  356. up->ier |= UART_IER_THRI;
  357. serial_out(up, UART_IER, up->ier);
  358. }
  359. }
  360.  
  361. static void serial_omap_start_tx(struct uart_port *port)
  362. {
  363. struct uart_omap_port *up = to_uart_omap_port(port);
  364.  
  365. pm_runtime_get_sync(up->dev);
  366. serial_omap_enable_ier_thri(up);
  367. serial_omap_set_noidle(up);
  368. pm_runtime_mark_last_busy(up->dev);
  369. pm_runtime_put_autosuspend(up->dev);
  370. }
  371.  
  372. static void serial_omap_throttle(struct uart_port *port)
  373. {
  374. struct uart_omap_port *up = to_uart_omap_port(port);
  375. unsigned long flags;
  376.  
  377. pm_runtime_get_sync(up->dev);
  378. spin_lock_irqsave(&up->port.lock, flags);
  379. up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
  380. serial_out(up, UART_IER, up->ier);
  381. spin_unlock_irqrestore(&up->port.lock, flags);
  382. pm_runtime_mark_last_busy(up->dev);
  383. pm_runtime_put_autosuspend(up->dev);
  384. }
  385.  
  386. static void serial_omap_unthrottle(struct uart_port *port)
  387. {
  388. struct uart_omap_port *up = to_uart_omap_port(port);
  389. unsigned long flags;
  390.  
  391. pm_runtime_get_sync(up->dev);
  392. spin_lock_irqsave(&up->port.lock, flags);
  393. up->ier |= UART_IER_RLSI | UART_IER_RDI;
  394. serial_out(up, UART_IER, up->ier);
  395. spin_unlock_irqrestore(&up->port.lock, flags);
  396. pm_runtime_mark_last_busy(up->dev);
  397. pm_runtime_put_autosuspend(up->dev);
  398. }
  399.  
  400. static unsigned int check_modem_status(struct uart_omap_port *up)
  401. {
  402. unsigned int status;
  403.  
  404. status = serial_in(up, UART_MSR);
  405. status |= up->msr_saved_flags;
  406. up->msr_saved_flags = 0;
  407. if ((status & UART_MSR_ANY_DELTA) == 0)
  408. return status;
  409.  
  410. if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
  411. up->port.state != NULL) {
  412. if (status & UART_MSR_TERI)
  413. up->port.icount.rng++;
  414. if (status & UART_MSR_DDSR)
  415. up->port.icount.dsr++;
  416. if (status & UART_MSR_DDCD)
  417. uart_handle_dcd_change
  418. (&up->port, status & UART_MSR_DCD);
  419. if (status & UART_MSR_DCTS)
  420. uart_handle_cts_change
  421. (&up->port, status & UART_MSR_CTS);
  422. wake_up_interruptible(&up->port.state->port.delta_msr_wait);
  423. }
  424.  
  425. return status;
  426. }
  427.  
  428. static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr)
  429. {
  430. unsigned int flag;
  431. unsigned char ch = 0;
  432.  
  433. if (likely(lsr & UART_LSR_DR))
  434. ch = serial_in(up, UART_RX);
  435.  
  436. up->port.icount.rx++;
  437. flag = TTY_NORMAL;
  438.  
  439. if (lsr & UART_LSR_BI) {
  440. flag = TTY_BREAK;
  441. lsr &= ~(UART_LSR_FE | UART_LSR_PE);
  442. up->port.icount.brk++;
  443. /*
  444. * We do the SysRQ and SAK checking
  445. * here because otherwise the break
  446. * may get masked by ignore_status_mask
  447. * or read_status_mask.
  448. */
  449. if (uart_handle_break(&up->port))
  450. return;
  451.  
  452. }
  453.  
  454. if (lsr & UART_LSR_PE) {
  455. flag = TTY_PARITY;
  456. up->port.icount.parity++;
  457. }
  458.  
  459. if (lsr & UART_LSR_FE) {
  460. flag = TTY_FRAME;
  461. up->port.icount.frame++;
  462. }
  463.  
  464. if (lsr & UART_LSR_OE)
  465. up->port.icount.overrun++;
  466.  
  467. #ifdef CONFIG_SERIAL_OMAP_CONSOLE
  468. if (up->port.line == up->port.cons->index) {
  469. /* Recover the break flag from console xmit */
  470. lsr |= up->lsr_break_flag;
  471. }
  472. #endif
  473. uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag);
  474. }
  475.  
  476. static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)
  477. {
  478. unsigned char ch = 0;
  479. unsigned int flag;
  480.  
  481. if (!(lsr & UART_LSR_DR))
  482. return;
  483.  
  484. ch = serial_in(up, UART_RX);
  485. flag = TTY_NORMAL;
  486. up->port.icount.rx++;
  487.  
  488. if (uart_handle_sysrq_char(&up->port, ch))
  489. return;
  490.  
  491. uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
  492. }
  493.  
  494. /**
  495. * serial_omap_irq() - This handles the interrupt from one port
  496. * @irq: uart port irq number
  497. * @dev_id: uart port info
  498. */
  499. static irqreturn_t serial_omap_irq(int irq, void *dev_id)
  500. {
  501. struct uart_omap_port *up = dev_id;
  502. struct tty_struct *tty = up->port.state->port.tty;
  503. unsigned int iir, lsr;
  504. unsigned int type;
  505. irqreturn_t ret = IRQ_NONE;
  506. int max_count = 256;
  507.  
  508. spin_lock(&up->port.lock);
  509. pm_runtime_get_sync(up->dev);
  510.  
  511. do {
  512. iir = serial_in(up, UART_IIR);
  513. if (iir & UART_IIR_NO_INT)
  514. break;
  515.  
  516. ret = IRQ_HANDLED;
  517. lsr = serial_in(up, UART_LSR);
  518.  
  519. /* extract IRQ type from IIR register */
  520. type = iir & 0x3e;
  521.  
  522. switch (type) {
  523. case UART_IIR_MSI:
  524. check_modem_status(up);
  525. break;
  526. case UART_IIR_THRI:
  527. transmit_chars(up, lsr);
  528. break;
  529. case UART_IIR_RX_TIMEOUT:
  530. /* FALLTHROUGH */
  531. case UART_IIR_RDI:
  532. serial_omap_rdi(up, lsr);
  533. break;
  534. case UART_IIR_RLSI:
  535. serial_omap_rlsi(up, lsr);
  536. break;
  537. case UART_IIR_CTS_RTS_DSR:
  538. /* simply try again */
  539. break;
  540. case UART_IIR_XOFF:
  541. /* FALLTHROUGH */
  542. default:
  543. break;
  544. }
  545. } while (!(iir & UART_IIR_NO_INT) && max_count--);
  546.  
  547. spin_unlock(&up->port.lock);
  548.  
  549. tty_flip_buffer_push(tty);
  550.  
  551. pm_runtime_mark_last_busy(up->dev);
  552. pm_runtime_put_autosuspend(up->dev);
  553. up->port_activity = jiffies;
  554.  
  555. return ret;
  556. }
  557.  
  558. static unsigned int serial_omap_tx_empty(struct uart_port *port)
  559. {
  560. struct uart_omap_port *up = to_uart_omap_port(port);
  561. unsigned long flags = 0;
  562. unsigned int ret = 0;
  563.  
  564. pm_runtime_get_sync(up->dev);
  565. dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
  566. spin_lock_irqsave(&up->port.lock, flags);
  567. ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
  568. spin_unlock_irqrestore(&up->port.lock, flags);
  569. pm_runtime_mark_last_busy(up->dev);
  570. pm_runtime_put_autosuspend(up->dev);
  571. return ret;
  572. }
  573.  
  574. static unsigned int serial_omap_get_mctrl(struct uart_port *port)
  575. {
  576. struct uart_omap_port *up = to_uart_omap_port(port);
  577. unsigned int status;
  578. unsigned int ret = 0;
  579.  
  580. pm_runtime_get_sync(up->dev);
  581. status = check_modem_status(up);
  582. pm_runtime_mark_last_busy(up->dev);
  583. pm_runtime_put_autosuspend(up->dev);
  584.  
  585. dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
  586.  
  587. if (status & UART_MSR_DCD)
  588. ret |= TIOCM_CAR;
  589. if (status & UART_MSR_RI)
  590. ret |= TIOCM_RNG;
  591. if (status & UART_MSR_DSR)
  592. ret |= TIOCM_DSR;
  593. if (status & UART_MSR_CTS)
  594. ret |= TIOCM_CTS;
  595. return ret;
  596. }
  597.  
  598. static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
  599. {
  600. struct uart_omap_port *up = to_uart_omap_port(port);
  601. unsigned char mcr = 0, old_mcr;
  602.  
  603. dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
  604. if (mctrl & TIOCM_RTS)
  605. mcr |= UART_MCR_RTS;
  606. if (mctrl & TIOCM_DTR)
  607. mcr |= UART_MCR_DTR;
  608. if (mctrl & TIOCM_OUT1)
  609. mcr |= UART_MCR_OUT1;
  610. if (mctrl & TIOCM_OUT2)
  611. mcr |= UART_MCR_OUT2;
  612. if (mctrl & TIOCM_LOOP)
  613. mcr |= UART_MCR_LOOP;
  614.  
  615. pm_runtime_get_sync(up->dev);
  616. old_mcr = serial_in(up, UART_MCR);
  617. old_mcr &= ~(UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_OUT1 |
  618. UART_MCR_DTR | UART_MCR_RTS);
  619. up->mcr = old_mcr | mcr;
  620. serial_out(up, UART_MCR, up->mcr);
  621. pm_runtime_mark_last_busy(up->dev);
  622. pm_runtime_put_autosuspend(up->dev);
  623.  
  624. if (gpio_is_valid(up->DTR_gpio) &&
  625. !!(mctrl & TIOCM_DTR) != up->DTR_active) {
  626. up->DTR_active = !up->DTR_active;
  627. if (gpio_cansleep(up->DTR_gpio))
  628. schedule_work(&up->qos_work);
  629. else
  630. gpio_set_value(up->DTR_gpio,
  631. up->DTR_active != up->DTR_inverted);
  632. }
  633. }
  634.  
  635. static void serial_omap_break_ctl(struct uart_port *port, int break_state)
  636. {
  637. struct uart_omap_port *up = to_uart_omap_port(port);
  638. unsigned long flags = 0;
  639.  
  640. dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
  641. pm_runtime_get_sync(up->dev);
  642. spin_lock_irqsave(&up->port.lock, flags);
  643. if (break_state == -1)
  644. up->lcr |= UART_LCR_SBC;
  645. else
  646. up->lcr &= ~UART_LCR_SBC;
  647. serial_out(up, UART_LCR, up->lcr);
  648. spin_unlock_irqrestore(&up->port.lock, flags);
  649. pm_runtime_mark_last_busy(up->dev);
  650. pm_runtime_put_autosuspend(up->dev);
  651. }
  652.  
  653. static int serial_omap_startup(struct uart_port *port)
  654. {
  655. struct uart_omap_port *up = to_uart_omap_port(port);
  656. unsigned long flags = 0;
  657. int retval;
  658.  
  659. /*
  660. * Allocate the IRQ
  661. */
  662. retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
  663. up->name, up);
  664. if (retval)
  665. return retval;
  666.  
  667. dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
  668.  
  669. pm_runtime_get_sync(up->dev);
  670. /*
  671. * Clear the FIFO buffers and disable them.
  672. * (they will be reenabled in set_termios())
  673. */
  674. serial_omap_clear_fifos(up);
  675. /* For Hardware flow control */
  676. serial_out(up, UART_MCR, UART_MCR_RTS);
  677.  
  678. /*
  679. * Clear the interrupt registers.
  680. */
  681. (void) serial_in(up, UART_LSR);
  682. if (serial_in(up, UART_LSR) & UART_LSR_DR)
  683. (void) serial_in(up, UART_RX);
  684. (void) serial_in(up, UART_IIR);
  685. (void) serial_in(up, UART_MSR);
  686.  
  687. /*
  688. * Now, initialize the UART
  689. */
  690. serial_out(up, UART_LCR, UART_LCR_WLEN8);
  691. spin_lock_irqsave(&up->port.lock, flags);
  692. /*
  693. * Most PC uarts need OUT2 raised to enable interrupts.
  694. */
  695. up->port.mctrl |= TIOCM_OUT2;
  696. serial_omap_set_mctrl(&up->port, up->port.mctrl);
  697. spin_unlock_irqrestore(&up->port.lock, flags);
  698.  
  699. up->msr_saved_flags = 0;
  700. /*
  701. * Finally, enable interrupts. Note: Modem status interrupts
  702. * are set via set_termios(), which will be occurring imminently
  703. * anyway, so we don't enable them here.
  704. */
  705. up->ier = UART_IER_RLSI | UART_IER_RDI;
  706. serial_out(up, UART_IER, up->ier);
  707.  
  708. /* Enable module level wake up */
  709. serial_out(up, UART_OMAP_WER, OMAP_UART_WER_MOD_WKUP);
  710.  
  711. pm_runtime_mark_last_busy(up->dev);
  712. pm_runtime_put_autosuspend(up->dev);
  713. up->port_activity = jiffies;
  714. return 0;
  715. }
  716.  
  717. static void serial_omap_shutdown(struct uart_port *port)
  718. {
  719. struct uart_omap_port *up = to_uart_omap_port(port);
  720. unsigned long flags = 0;
  721.  
  722. dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
  723.  
  724. pm_runtime_get_sync(up->dev);
  725. /*
  726. * Disable interrupts from this port
  727. */
  728. up->ier = 0;
  729. serial_out(up, UART_IER, 0);
  730.  
  731. spin_lock_irqsave(&up->port.lock, flags);
  732. up->port.mctrl &= ~TIOCM_OUT2;
  733. serial_omap_set_mctrl(&up->port, up->port.mctrl);
  734. spin_unlock_irqrestore(&up->port.lock, flags);
  735.  
  736. /*
  737. * Disable break condition and FIFOs
  738. */
  739. serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
  740. serial_omap_clear_fifos(up);
  741.  
  742. /* if in RS485 mode, make sure we disable the driver */
  743. if (up->rs485.flags & SER_RS485_ENABLED) {
  744. val = (up->rs485.flags & SER_RS485_RTS_AFTER_SEND) ? 1 : 0;
  745. gpio_set_value(up->rs485.gpio_pin, val);
  746. }
  747.  
  748. /*
  749. * Read data port to reset things, and then free the irq
  750. */
  751. if (serial_in(up, UART_LSR) & UART_LSR_DR)
  752. (void) serial_in(up, UART_RX);
  753.  
  754. pm_runtime_mark_last_busy(up->dev);
  755. pm_runtime_put_autosuspend(up->dev);
  756. free_irq(up->port.irq, up);
  757. }
  758.  
  759. static void serial_omap_uart_qos_work(struct work_struct *work)
  760. {
  761. struct uart_omap_port *up = container_of(work, struct uart_omap_port,
  762. qos_work);
  763.  
  764. pm_qos_update_request(&up->pm_qos_request, up->latency);
  765. if (gpio_is_valid(up->DTR_gpio))
  766. gpio_set_value_cansleep(up->DTR_gpio,
  767. up->DTR_active != up->DTR_inverted);
  768. }
  769.  
  770. static void
  771. serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
  772. struct ktermios *old)
  773. {
  774. struct uart_omap_port *up = to_uart_omap_port(port);
  775. unsigned char cval = 0;
  776. unsigned long flags = 0;
  777. unsigned int baud, quot;
  778.  
  779. switch (termios->c_cflag & CSIZE) {
  780. case CS5:
  781. cval = UART_LCR_WLEN5;
  782. break;
  783. case CS6:
  784. cval = UART_LCR_WLEN6;
  785. break;
  786. case CS7:
  787. cval = UART_LCR_WLEN7;
  788. break;
  789. default:
  790. case CS8:
  791. cval = UART_LCR_WLEN8;
  792. break;
  793. }
  794.  
  795. if (termios->c_cflag & CSTOPB)
  796. cval |= UART_LCR_STOP;
  797. if (termios->c_cflag & PARENB)
  798. cval |= UART_LCR_PARITY;
  799. if (!(termios->c_cflag & PARODD))
  800. cval |= UART_LCR_EPAR;
  801.  
  802. /*
  803. * Ask the core to calculate the divisor for us.
  804. */
  805.  
  806. baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
  807. quot = serial_omap_get_divisor(port, baud);
  808.  
  809. /* calculate wakeup latency constraint */
  810. up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8);
  811. up->latency = up->calc_latency;
  812. schedule_work(&up->qos_work);
  813.  
  814. up->dll = quot & 0xff;
  815. up->dlh = quot >> 8;
  816. up->mdr1 = UART_OMAP_MDR1_DISABLE;
  817.  
  818. up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
  819. UART_FCR_ENABLE_FIFO;
  820.  
  821. /*
  822. * Ok, we're now changing the port state. Do it with
  823. * interrupts disabled.
  824. */
  825. pm_runtime_get_sync(up->dev);
  826. spin_lock_irqsave(&up->port.lock, flags);
  827.  
  828. /*
  829. * Update the per-port timeout.
  830. */
  831. uart_update_timeout(port, termios->c_cflag, baud);
  832.  
  833. up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
  834. if (termios->c_iflag & INPCK)
  835. up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
  836. if (termios->c_iflag & (BRKINT | PARMRK))
  837. up->port.read_status_mask |= UART_LSR_BI;
  838.  
  839. /*
  840. * Characters to ignore
  841. */
  842. up->port.ignore_status_mask = 0;
  843. if (termios->c_iflag & IGNPAR)
  844. up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
  845. if (termios->c_iflag & IGNBRK) {
  846. up->port.ignore_status_mask |= UART_LSR_BI;
  847. /*
  848. * If we're ignoring parity and break indicators,
  849. * ignore overruns too (for real raw support).
  850. */
  851. if (termios->c_iflag & IGNPAR)
  852. up->port.ignore_status_mask |= UART_LSR_OE;
  853. }
  854.  
  855. /*
  856. * ignore all characters if CREAD is not set
  857. */
  858. if ((termios->c_cflag & CREAD) == 0)
  859. up->port.ignore_status_mask |= UART_LSR_DR;
  860.  
  861. /*
  862. * Modem status interrupts
  863. */
  864. up->ier &= ~UART_IER_MSI;
  865. if (UART_ENABLE_MS(&up->port, termios->c_cflag))
  866. up->ier |= UART_IER_MSI;
  867. serial_out(up, UART_IER, up->ier);
  868. serial_out(up, UART_LCR, cval); /* reset DLAB */
  869. up->lcr = cval;
  870. up->scr = OMAP_UART_SCR_TX_EMPTY;
  871.  
  872. /* FIFOs and DMA Settings */
  873.  
  874. /* FCR can be changed only when the
  875. * baud clock is not running
  876. * DLL_REG and DLH_REG set to 0.
  877. */
  878. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
  879. serial_out(up, UART_DLL, 0);
  880. serial_out(up, UART_DLM, 0);
  881. serial_out(up, UART_LCR, 0);
  882.  
  883. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
  884.  
  885. up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB;
  886. up->efr &= ~UART_EFR_SCD;
  887. serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
  888.  
  889. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
  890. up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR;
  891. serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
  892. /* FIFO ENABLE, DMA MODE */
  893.  
  894. up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
  895.  
  896. /* Set receive FIFO threshold to 16 characters and
  897. * transmit FIFO threshold to 16 spaces
  898. */
  899. up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
  900. up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK;
  901. up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 |
  902. UART_FCR_ENABLE_FIFO;
  903.  
  904. serial_out(up, UART_FCR, up->fcr);
  905. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
  906.  
  907. serial_out(up, UART_OMAP_SCR, up->scr);
  908.  
  909. /* Reset UART_MCR_TCRTLR: this must be done with the EFR_ECB bit set */
  910. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
  911. serial_out(up, UART_MCR, up->mcr);
  912. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
  913. serial_out(up, UART_EFR, up->efr);
  914. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
  915.  
  916. /* Protocol, Baud Rate, and Interrupt Settings */
  917.  
  918. if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
  919. serial_omap_mdr1_errataset(up, up->mdr1);
  920. else
  921. serial_out(up, UART_OMAP_MDR1, up->mdr1);
  922.  
  923. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
  924. serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
  925.  
  926. serial_out(up, UART_LCR, 0);
  927. serial_out(up, UART_IER, 0);
  928. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
  929.  
  930. serial_out(up, UART_DLL, up->dll); /* LS of divisor */
  931. serial_out(up, UART_DLM, up->dlh); /* MS of divisor */
  932.  
  933. serial_out(up, UART_LCR, 0);
  934. serial_out(up, UART_IER, up->ier);
  935. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
  936.  
  937. serial_out(up, UART_EFR, up->efr);
  938. serial_out(up, UART_LCR, cval);
  939.  
  940. if (baud > 230400 && baud != 3000000)
  941. up->mdr1 = UART_OMAP_MDR1_13X_MODE;
  942. else
  943. up->mdr1 = UART_OMAP_MDR1_16X_MODE;
  944.  
  945. if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
  946. serial_omap_mdr1_errataset(up, up->mdr1);
  947. else
  948. serial_out(up, UART_OMAP_MDR1, up->mdr1);
  949.  
  950. /* Configure flow control */
  951. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
  952.  
  953. /* XON1/XOFF1 accessible mode B, TCRTLR=0, ECB=0 */
  954. serial_out(up, UART_XON1, termios->c_cc[VSTART]);
  955. serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
  956.  
  957. /* Enable access to TCR/TLR */
  958. serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
  959. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
  960. serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
  961.  
  962. serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
  963.  
  964. if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
  965. /* Enable AUTORTS and AUTOCTS */
  966. up->efr |= UART_EFR_CTS | UART_EFR_RTS;
  967.  
  968. /* Ensure MCR RTS is asserted */
  969. up->mcr |= UART_MCR_RTS;
  970. } else {
  971. /* Disable AUTORTS and AUTOCTS */
  972. up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS);
  973. }
  974.  
  975. if (up->port.flags & UPF_SOFT_FLOW) {
  976. /* clear SW control mode bits */
  977. up->efr &= OMAP_UART_SW_CLR;
  978.  
  979. /*
  980. * IXON Flag:
  981. * Enable XON/XOFF flow control on input.
  982. * Receiver compares XON1, XOFF1.
  983. */
  984. if (termios->c_iflag & IXON)
  985. up->efr |= OMAP_UART_SW_RX;
  986.  
  987. /*
  988. * IXOFF Flag:
  989. * Enable XON/XOFF flow control on output.
  990. * Transmit XON1, XOFF1
  991. */
  992. if (termios->c_iflag & IXOFF)
  993. up->efr |= OMAP_UART_SW_TX;
  994.  
  995. /*
  996. * IXANY Flag:
  997. * Enable any character to restart output.
  998. * Operation resumes after receiving any
  999. * character after recognition of the XOFF character
  1000. */
  1001. if (termios->c_iflag & IXANY)
  1002. up->mcr |= UART_MCR_XONANY;
  1003. else
  1004. up->mcr &= ~UART_MCR_XONANY;
  1005. }
  1006. serial_out(up, UART_MCR, up->mcr);
  1007. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
  1008. serial_out(up, UART_EFR, up->efr);
  1009. serial_out(up, UART_LCR, up->lcr);
  1010.  
  1011. serial_omap_set_mctrl(&up->port, up->port.mctrl);
  1012.  
  1013. spin_unlock_irqrestore(&up->port.lock, flags);
  1014. pm_runtime_mark_last_busy(up->dev);
  1015. pm_runtime_put_autosuspend(up->dev);
  1016. dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
  1017. }
  1018.  
  1019. static int serial_omap_set_wake(struct uart_port *port, unsigned int state)
  1020. {
  1021. struct uart_omap_port *up = to_uart_omap_port(port);
  1022.  
  1023. serial_omap_enable_wakeup(up, state);
  1024.  
  1025. return 0;
  1026. }
  1027.  
  1028. static void
  1029. serial_omap_pm(struct uart_port *port, unsigned int state,
  1030. unsigned int oldstate)
  1031. {
  1032. struct uart_omap_port *up = to_uart_omap_port(port);
  1033. unsigned char efr;
  1034.  
  1035. dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
  1036.  
  1037. pm_runtime_get_sync(up->dev);
  1038. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
  1039. efr = serial_in(up, UART_EFR);
  1040. serial_out(up, UART_EFR, efr | UART_EFR_ECB);
  1041. serial_out(up, UART_LCR, 0);
  1042.  
  1043. serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
  1044. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
  1045. serial_out(up, UART_EFR, efr);
  1046. serial_out(up, UART_LCR, 0);
  1047.  
  1048. if (!device_may_wakeup(up->dev)) {
  1049. if (!state)
  1050. pm_runtime_forbid(up->dev);
  1051. else
  1052. pm_runtime_allow(up->dev);
  1053. }
  1054.  
  1055. pm_runtime_mark_last_busy(up->dev);
  1056. pm_runtime_put_autosuspend(up->dev);
  1057. }
  1058.  
  1059. static void serial_omap_release_port(struct uart_port *port)
  1060. {
  1061. dev_dbg(port->dev, "serial_omap_release_port+\n");
  1062. }
  1063.  
  1064. static int serial_omap_request_port(struct uart_port *port)
  1065. {
  1066. dev_dbg(port->dev, "serial_omap_request_port+\n");
  1067. return 0;
  1068. }
  1069.  
  1070. static void serial_omap_config_port(struct uart_port *port, int flags)
  1071. {
  1072. struct uart_omap_port *up = to_uart_omap_port(port);
  1073.  
  1074. dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
  1075. up->port.line);
  1076. up->port.type = PORT_OMAP;
  1077. up->port.flags |= UPF_SOFT_FLOW | UPF_HARD_FLOW;
  1078. }
  1079.  
  1080. static int
  1081. serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
  1082. {
  1083. /* we don't want the core code to modify any port params */
  1084. dev_dbg(port->dev, "serial_omap_verify_port+\n");
  1085. return -EINVAL;
  1086. }
  1087.  
  1088. static const char *
  1089. serial_omap_type(struct uart_port *port)
  1090. {
  1091. struct uart_omap_port *up = to_uart_omap_port(port);
  1092.  
  1093. dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
  1094. return up->name;
  1095. }
  1096.  
  1097. #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
  1098.  
  1099. static inline void wait_for_xmitr(struct uart_omap_port *up)
  1100. {
  1101. unsigned int status, tmout = 10000;
  1102.  
  1103. /* Wait up to 10ms for the character(s) to be sent. */
  1104. do {
  1105. status = serial_in(up, UART_LSR);
  1106.  
  1107. if (status & UART_LSR_BI)
  1108. up->lsr_break_flag = UART_LSR_BI;
  1109.  
  1110. if (--tmout == 0)
  1111. break;
  1112. udelay(1);
  1113. } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
  1114.  
  1115. /* Wait up to 1s for flow control if necessary */
  1116. if (up->port.flags & UPF_CONS_FLOW) {
  1117. tmout = 1000000;
  1118. for (tmout = 1000000; tmout; tmout--) {
  1119. unsigned int msr = serial_in(up, UART_MSR);
  1120.  
  1121. up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
  1122. if (msr & UART_MSR_CTS)
  1123. break;
  1124.  
  1125. udelay(1);
  1126. }
  1127. }
  1128. }
  1129.  
  1130. #ifdef CONFIG_CONSOLE_POLL
  1131.  
  1132. static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
  1133. {
  1134. struct uart_omap_port *up = to_uart_omap_port(port);
  1135.  
  1136. pm_runtime_get_sync(up->dev);
  1137. wait_for_xmitr(up);
  1138. serial_out(up, UART_TX, ch);
  1139. pm_runtime_mark_last_busy(up->dev);
  1140. pm_runtime_put_autosuspend(up->dev);
  1141. }
  1142.  
  1143. static int serial_omap_poll_get_char(struct uart_port *port)
  1144. {
  1145. struct uart_omap_port *up = to_uart_omap_port(port);
  1146. unsigned int status;
  1147.  
  1148. pm_runtime_get_sync(up->dev);
  1149. status = serial_in(up, UART_LSR);
  1150. if (!(status & UART_LSR_DR)) {
  1151. status = NO_POLL_CHAR;
  1152. goto out;
  1153. }
  1154.  
  1155. status = serial_in(up, UART_RX);
  1156.  
  1157. out:
  1158. pm_runtime_mark_last_busy(up->dev);
  1159. pm_runtime_put_autosuspend(up->dev);
  1160.  
  1161. return status;
  1162. }
  1163.  
  1164. #endif /* CONFIG_CONSOLE_POLL */
  1165.  
  1166. #ifdef CONFIG_SERIAL_OMAP_CONSOLE
  1167.  
  1168. static struct uart_omap_port *serial_omap_console_ports[OMAP_MAX_HSUART_PORTS];
  1169.  
  1170. static struct uart_driver serial_omap_reg;
  1171.  
  1172. static void serial_omap_console_putchar(struct uart_port *port, int ch)
  1173. {
  1174. struct uart_omap_port *up = to_uart_omap_port(port);
  1175.  
  1176. wait_for_xmitr(up);
  1177. serial_out(up, UART_TX, ch);
  1178. }
  1179.  
  1180. static void
  1181. serial_omap_console_write(struct console *co, const char *s,
  1182. unsigned int count)
  1183. {
  1184. struct uart_omap_port *up = serial_omap_console_ports[co->index];
  1185. unsigned long flags;
  1186. unsigned int ier;
  1187. int locked = 1;
  1188.  
  1189. pm_runtime_get_sync(up->dev);
  1190.  
  1191. local_irq_save(flags);
  1192. if (up->port.sysrq)
  1193. locked = 0;
  1194. else if (oops_in_progress)
  1195. locked = spin_trylock(&up->port.lock);
  1196. else
  1197. spin_lock(&up->port.lock);
  1198.  
  1199. /*
  1200. * First save the IER then disable the interrupts
  1201. */
  1202. ier = serial_in(up, UART_IER);
  1203. serial_out(up, UART_IER, 0);
  1204.  
  1205. uart_console_write(&up->port, s, count, serial_omap_console_putchar);
  1206.  
  1207. /*
  1208. * Finally, wait for transmitter to become empty
  1209. * and restore the IER
  1210. */
  1211. wait_for_xmitr(up);
  1212. serial_out(up, UART_IER, ier);
  1213. /*
  1214. * The receive handling will happen properly because the
  1215. * receive ready bit will still be set; it is not cleared
  1216. * on read. However, modem control will not, we must
  1217. * call it if we have saved something in the saved flags
  1218. * while processing with interrupts off.
  1219. */
  1220. if (up->msr_saved_flags)
  1221. check_modem_status(up);
  1222.  
  1223. pm_runtime_mark_last_busy(up->dev);
  1224. pm_runtime_put_autosuspend(up->dev);
  1225. if (locked)
  1226. spin_unlock(&up->port.lock);
  1227. local_irq_restore(flags);
  1228. }
  1229.  
  1230. static int __init
  1231. serial_omap_console_setup(struct console *co, char *options)
  1232. {
  1233. struct uart_omap_port *up;
  1234. int baud = 115200;
  1235. int bits = 8;
  1236. int parity = 'n';
  1237. int flow = 'n';
  1238.  
  1239. if (serial_omap_console_ports[co->index] == NULL)
  1240. return -ENODEV;
  1241. up = serial_omap_console_ports[co->index];
  1242.  
  1243. if (options)
  1244. uart_parse_options(options, &baud, &parity, &bits, &flow);
  1245.  
  1246. return uart_set_options(&up->port, co, baud, parity, bits, flow);
  1247. }
  1248.  
  1249. static struct console serial_omap_console = {
  1250. .name = OMAP_SERIAL_NAME,
  1251. .write = serial_omap_console_write,
  1252. .device = uart_console_device,
  1253. .setup = serial_omap_console_setup,
  1254. .flags = CON_PRINTBUFFER,
  1255. .index = -1,
  1256. .data = &serial_omap_reg,
  1257. };
  1258.  
  1259. static void serial_omap_add_console_port(struct uart_omap_port *up)
  1260. {
  1261. serial_omap_console_ports[up->port.line] = up;
  1262. }
  1263.  
  1264. #define OMAP_CONSOLE (&serial_omap_console)
  1265.  
  1266. #else
  1267.  
  1268. #define OMAP_CONSOLE NULL
  1269.  
  1270. static inline void serial_omap_add_console_port(struct uart_omap_port *up)
  1271. {}
  1272.  
  1273. #endif
  1274.  
  1275. static int
  1276. serial_omap_config_rs485(struct uart_port *port, struct serial_rs485 *rs485conf)
  1277. {
  1278. int r = 0;
  1279. int val;
  1280. struct uart_omap_port *p = (struct uart_omap_port *)port;
  1281. spin_lock(&port->lock);
  1282.  
  1283. /* TODO - disable transmitter ? */
  1284.  
  1285. if (rs485conf->flags & SER_RS485_ENABLED) {
  1286. val = (p->rs485.flags & SER_RS485_RTS_AFTER_SEND) ? 1 : 0;
  1287. /* if using GPIO, request the resource and set it up */
  1288. if (rs485conf->flags & SER_RS485_USE_GPIO) {
  1289. /* get gpio resources if not already set */
  1290. if (!(p->rs485.flags & SER_RS485_USE_GPIO) ||
  1291. (p->rs485.gpio_pin != rs485conf->gpio_pin)) {
  1292.  
  1293. r = gpio_request(rs485conf->gpio_pin,
  1294. "RS485 TXE");
  1295. if (r) {
  1296. dev_warn(port->dev,
  1297. "Could not request GPIO %d : %d\n",
  1298. rs485conf->gpio_pin, r);
  1299. r = -EFAULT;
  1300. goto exit_bail;
  1301.  
  1302. }
  1303.  
  1304. r = gpio_direction_output(rs485conf->gpio_pin, val);
  1305. if (r) {
  1306. dev_warn(port->dev,
  1307. "Could not drive GPIO %d : %d\n",
  1308. rs485conf->gpio_pin, r);
  1309. r = -EFAULT;
  1310. goto exit_bail;
  1311. }
  1312. /* free up old pin */
  1313. //TODO: What if old pin is same as current?!!?!?
  1314. //if (p->rs485.flags & SER_RS485_USE_GPIO)
  1315. //gpio_free(p->rs485.gpio_pin);
  1316. }
  1317. } else { /* RTS pin requested */
  1318. dev_warn(port->dev, "Must use GPIO for RS485 Support\n");
  1319. goto exit_bail;
  1320. }
  1321. }
  1322. p->rs485 = *rs485conf;
  1323.  
  1324. exit_bail:
  1325. spin_unlock(&port->lock);
  1326. return r;
  1327.  
  1328. }
  1329.  
  1330. static int
  1331. serial_omap_ioctl(struct uart_port *port, unsigned int cmd, unsigned long arg)
  1332. {
  1333. printk(KERN_NOTICE "OMAPioctl called test: %d=%d\n", cmd, TIOCSRS485);
  1334. struct serial_rs485 rs485conf;
  1335.  
  1336. switch (cmd) {
  1337. case TIOCSRS485:
  1338. if (copy_from_user(&rs485conf, (struct serial_rs485 *)arg,
  1339. sizeof(rs485conf)))
  1340. return -EFAULT;
  1341. serial_omap_config_rs485(port, &rs485conf);
  1342. break;
  1343.  
  1344. case TIOCGRS485:
  1345. if (copy_to_user((struct serial_rs485 *)arg,
  1346. &((struct uart_omap_port *)port)->rs485,
  1347. sizeof(rs485conf)))
  1348. return -EFAULT;
  1349. break;
  1350.  
  1351. default:
  1352. return -ENOIOCTLCMD;
  1353. }
  1354.  
  1355. return 0;
  1356. }
  1357.  
  1358.  
  1359.  
  1360. static struct uart_ops serial_omap_pops = {
  1361. .tx_empty = serial_omap_tx_empty,
  1362. .set_mctrl = serial_omap_set_mctrl,
  1363. .get_mctrl = serial_omap_get_mctrl,
  1364. .stop_tx = serial_omap_stop_tx,
  1365. .start_tx = serial_omap_start_tx,
  1366. .throttle = serial_omap_throttle,
  1367. .unthrottle = serial_omap_unthrottle,
  1368. .stop_rx = serial_omap_stop_rx,
  1369. .enable_ms = serial_omap_enable_ms,
  1370. .break_ctl = serial_omap_break_ctl,
  1371. .startup = serial_omap_startup,
  1372. .shutdown = serial_omap_shutdown,
  1373. .set_termios = serial_omap_set_termios,
  1374. .pm = serial_omap_pm,
  1375. .set_wake = serial_omap_set_wake,
  1376. .type = serial_omap_type,
  1377. .release_port = serial_omap_release_port,
  1378. .request_port = serial_omap_request_port,
  1379. .config_port = serial_omap_config_port,
  1380. .verify_port = serial_omap_verify_port,
  1381. .ioctl = serial_omap_ioctl,
  1382. #ifdef CONFIG_CONSOLE_POLL
  1383. .poll_put_char = serial_omap_poll_put_char,
  1384. .poll_get_char = serial_omap_poll_get_char,
  1385. #endif
  1386. };
  1387.  
  1388. static struct uart_driver serial_omap_reg = {
  1389. .owner = THIS_MODULE,
  1390. .driver_name = "OMAP-SERIAL",
  1391. .dev_name = OMAP_SERIAL_NAME,
  1392. .nr = OMAP_MAX_HSUART_PORTS,
  1393. .cons = OMAP_CONSOLE,
  1394. };
  1395.  
  1396. #ifdef CONFIG_PM_SLEEP
  1397. static int serial_omap_suspend(struct device *dev)
  1398. {
  1399. struct uart_omap_port *up = dev_get_drvdata(dev);
  1400.  
  1401. uart_suspend_port(&serial_omap_reg, &up->port);
  1402. flush_work(&up->qos_work);
  1403.  
  1404. return 0;
  1405. }
  1406.  
  1407. static int serial_omap_resume(struct device *dev)
  1408. {
  1409. struct uart_omap_port *up = dev_get_drvdata(dev);
  1410.  
  1411. uart_resume_port(&serial_omap_reg, &up->port);
  1412.  
  1413. return 0;
  1414. }
  1415. #endif
  1416.  
  1417. static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
  1418. {
  1419. u32 mvr, scheme;
  1420. u16 revision, major, minor;
  1421.  
  1422. mvr = serial_in(up, UART_OMAP_MVER);
  1423.  
  1424. /* Check revision register scheme */
  1425. scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
  1426.  
  1427. switch (scheme) {
  1428. case 0: /* Legacy Scheme: OMAP2/3 */
  1429. /* MINOR_REV[0:4], MAJOR_REV[4:7] */
  1430. major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
  1431. OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
  1432. minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
  1433. break;
  1434. case 1:
  1435. /* New Scheme: OMAP4+ */
  1436. /* MINOR_REV[0:5], MAJOR_REV[8:10] */
  1437. major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
  1438. OMAP_UART_MVR_MAJ_SHIFT;
  1439. minor = (mvr & OMAP_UART_MVR_MIN_MASK);
  1440. break;
  1441. default:
  1442. dev_warn(up->dev,
  1443. "Unknown %s revision, defaulting to highest\n",
  1444. up->name);
  1445. /* highest possible revision */
  1446. major = 0xff;
  1447. minor = 0xff;
  1448. }
  1449.  
  1450. /* normalize revision for the driver */
  1451. revision = UART_BUILD_REVISION(major, minor);
  1452.  
  1453. switch (revision) {
  1454. case OMAP_UART_REV_46:
  1455. up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
  1456. UART_ERRATA_i291_DMA_FORCEIDLE);
  1457. break;
  1458. case OMAP_UART_REV_52:
  1459. up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
  1460. UART_ERRATA_i291_DMA_FORCEIDLE);
  1461. break;
  1462. case OMAP_UART_REV_63:
  1463. up->errata |= UART_ERRATA_i202_MDR1_ACCESS;
  1464. break;
  1465. default:
  1466. break;
  1467. }
  1468. }
  1469.  
  1470. static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
  1471. {
  1472. struct omap_uart_port_info *omap_up_info;
  1473.  
  1474. omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
  1475. if (!omap_up_info)
  1476. return NULL; /* out of memory */
  1477.  
  1478. of_property_read_u32(dev->of_node, "clock-frequency",
  1479. &omap_up_info->uartclk);
  1480. return omap_up_info;
  1481. }
  1482.  
  1483. static int serial_omap_probe(struct platform_device *pdev)
  1484. {
  1485. struct uart_omap_port *up;
  1486. struct resource *mem, *irq;
  1487. struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data;
  1488. int ret;
  1489.  
  1490. if (pdev->dev.of_node)
  1491. omap_up_info = of_get_uart_port_info(&pdev->dev);
  1492.  
  1493. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1494. if (!mem) {
  1495. dev_err(&pdev->dev, "no mem resource?\n");
  1496. return -ENODEV;
  1497. }
  1498.  
  1499. irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1500. if (!irq) {
  1501. dev_err(&pdev->dev, "no irq resource?\n");
  1502. return -ENODEV;
  1503. }
  1504.  
  1505. if (!devm_request_mem_region(&pdev->dev, mem->start, resource_size(mem),
  1506. pdev->dev.driver->name)) {
  1507. dev_err(&pdev->dev, "memory region already claimed\n");
  1508. return -EBUSY;
  1509. }
  1510.  
  1511. if (gpio_is_valid(omap_up_info->DTR_gpio) &&
  1512. omap_up_info->DTR_present) {
  1513. ret = gpio_request(omap_up_info->DTR_gpio, "omap-serial");
  1514. if (ret < 0)
  1515. return ret;
  1516. ret = gpio_direction_output(omap_up_info->DTR_gpio,
  1517. omap_up_info->DTR_inverted);
  1518. if (ret < 0)
  1519. return ret;
  1520. }
  1521.  
  1522. up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
  1523. if (!up)
  1524. return -ENOMEM;
  1525.  
  1526. if (gpio_is_valid(omap_up_info->DTR_gpio) &&
  1527. omap_up_info->DTR_present) {
  1528. up->DTR_gpio = omap_up_info->DTR_gpio;
  1529. up->DTR_inverted = omap_up_info->DTR_inverted;
  1530. } else
  1531. up->DTR_gpio = -EINVAL;
  1532. up->DTR_active = 0;
  1533.  
  1534. up->dev = &pdev->dev;
  1535. up->port.dev = &pdev->dev;
  1536. up->port.type = PORT_OMAP;
  1537. up->port.iotype = UPIO_MEM;
  1538. up->port.irq = irq->start;
  1539.  
  1540. up->port.regshift = 2;
  1541. up->port.fifosize = 64;
  1542. up->port.ops = &serial_omap_pops;
  1543.  
  1544. if (pdev->dev.of_node)
  1545. up->port.line = of_alias_get_id(pdev->dev.of_node, "serial");
  1546. else
  1547. up->port.line = pdev->id;
  1548.  
  1549. if (up->port.line < 0) {
  1550. dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
  1551. up->port.line);
  1552. ret = -ENODEV;
  1553. goto err_port_line;
  1554. }
  1555.  
  1556. up->pins = devm_pinctrl_get_select_default(&pdev->dev);
  1557. if (IS_ERR(up->pins)) {
  1558. dev_warn(&pdev->dev, "did not get pins for uart%i error: %li\n",
  1559. up->port.line, PTR_ERR(up->pins));
  1560. up->pins = NULL;
  1561. }
  1562.  
  1563. sprintf(up->name, "OMAP UART%d", up->port.line);
  1564. up->port.mapbase = mem->start;
  1565. up->port.membase = devm_ioremap(&pdev->dev, mem->start,
  1566. resource_size(mem));
  1567. if (!up->port.membase) {
  1568. dev_err(&pdev->dev, "can't ioremap UART\n");
  1569. ret = -ENOMEM;
  1570. goto err_ioremap;
  1571. }
  1572.  
  1573. up->port.flags = omap_up_info->flags;
  1574. up->port.uartclk = omap_up_info->uartclk;
  1575. if (!up->port.uartclk) {
  1576. up->port.uartclk = DEFAULT_CLK_SPEED;
  1577. dev_warn(&pdev->dev, "No clock speed specified: using default:"
  1578. "%d\n", DEFAULT_CLK_SPEED);
  1579. }
  1580.  
  1581. up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
  1582. up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
  1583. pm_qos_add_request(&up->pm_qos_request,
  1584. PM_QOS_CPU_DMA_LATENCY, up->latency);
  1585. serial_omap_uart_wq = create_singlethread_workqueue(up->name);
  1586. INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
  1587.  
  1588. platform_set_drvdata(pdev, up);
  1589. pm_runtime_enable(&pdev->dev);
  1590. pm_runtime_use_autosuspend(&pdev->dev);
  1591. pm_runtime_set_autosuspend_delay(&pdev->dev,
  1592. omap_up_info->autosuspend_timeout);
  1593.  
  1594. pm_runtime_irq_safe(&pdev->dev);
  1595. pm_runtime_get_sync(&pdev->dev);
  1596.  
  1597. omap_serial_fill_features_erratas(up);
  1598.  
  1599. ui[up->port.line] = up;
  1600. serial_omap_add_console_port(up);
  1601.  
  1602. ret = uart_add_one_port(&serial_omap_reg, &up->port);
  1603. if (ret != 0)
  1604. goto err_add_port;
  1605.  
  1606. pm_runtime_mark_last_busy(up->dev);
  1607. pm_runtime_put_autosuspend(up->dev);
  1608. return 0;
  1609.  
  1610. err_add_port:
  1611. pm_runtime_put(&pdev->dev);
  1612. pm_runtime_disable(&pdev->dev);
  1613. err_ioremap:
  1614. err_port_line:
  1615. dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n",
  1616. pdev->id, __func__, ret);
  1617. return ret;
  1618. }
  1619.  
  1620. static int serial_omap_remove(struct platform_device *dev)
  1621. {
  1622. struct uart_omap_port *up = platform_get_drvdata(dev);
  1623.  
  1624. pm_runtime_put_sync(up->dev);
  1625. pm_runtime_disable(up->dev);
  1626. uart_remove_one_port(&serial_omap_reg, &up->port);
  1627. pm_qos_remove_request(&up->pm_qos_request);
  1628.  
  1629. return 0;
  1630. }
  1631.  
  1632. /*
  1633. * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
  1634. * The access to uart register after MDR1 Access
  1635. * causes UART to corrupt data.
  1636. *
  1637. * Need a delay =
  1638. * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
  1639. * give 10 times as much
  1640. */
  1641. static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
  1642. {
  1643. u8 timeout = 255;
  1644.  
  1645. serial_out(up, UART_OMAP_MDR1, mdr1);
  1646. udelay(2);
  1647. serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
  1648. UART_FCR_CLEAR_RCVR);
  1649. /*
  1650. * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
  1651. * TX_FIFO_E bit is 1.
  1652. */
  1653. while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
  1654. (UART_LSR_THRE | UART_LSR_DR))) {
  1655. timeout--;
  1656. if (!timeout) {
  1657. /* Should *never* happen. we warn and carry on */
  1658. dev_crit(up->dev, "Errata i202: timedout %x\n",
  1659. serial_in(up, UART_LSR));
  1660. break;
  1661. }
  1662. udelay(1);
  1663. }
  1664. }
  1665.  
  1666. #ifdef CONFIG_PM_RUNTIME
  1667. static void serial_omap_restore_context(struct uart_omap_port *up)
  1668. {
  1669. if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
  1670. serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
  1671. else
  1672. serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
  1673.  
  1674. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
  1675. serial_out(up, UART_EFR, UART_EFR_ECB);
  1676. serial_out(up, UART_LCR, 0x0); /* Operational mode */
  1677. serial_out(up, UART_IER, 0x0);
  1678. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
  1679. serial_out(up, UART_DLL, up->dll);
  1680. serial_out(up, UART_DLM, up->dlh);
  1681. serial_out(up, UART_LCR, 0x0); /* Operational mode */
  1682. serial_out(up, UART_IER, up->ier);
  1683. serial_out(up, UART_FCR, up->fcr);
  1684. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
  1685. serial_out(up, UART_MCR, up->mcr);
  1686. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
  1687. serial_out(up, UART_OMAP_SCR, up->scr);
  1688. serial_out(up, UART_EFR, up->efr);
  1689. serial_out(up, UART_LCR, up->lcr);
  1690. if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
  1691. serial_omap_mdr1_errataset(up, up->mdr1);
  1692. else
  1693. serial_out(up, UART_OMAP_MDR1, up->mdr1);
  1694. }
  1695.  
  1696. static int serial_omap_runtime_suspend(struct device *dev)
  1697. {
  1698. struct uart_omap_port *up = dev_get_drvdata(dev);
  1699. struct omap_uart_port_info *pdata = dev->platform_data;
  1700.  
  1701. if (!up)
  1702. return -EINVAL;
  1703.  
  1704. if (!pdata)
  1705. return 0;
  1706.  
  1707. up->context_loss_cnt = serial_omap_get_context_loss_count(up);
  1708.  
  1709. if (device_may_wakeup(dev)) {
  1710. if (!up->wakeups_enabled) {
  1711. serial_omap_enable_wakeup(up, true);
  1712. up->wakeups_enabled = true;
  1713. }
  1714. } else {
  1715. if (up->wakeups_enabled) {
  1716. serial_omap_enable_wakeup(up, false);
  1717. up->wakeups_enabled = false;
  1718. }
  1719. }
  1720.  
  1721. up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
  1722. schedule_work(&up->qos_work);
  1723.  
  1724. return 0;
  1725. }
  1726.  
  1727. static int serial_omap_runtime_resume(struct device *dev)
  1728. {
  1729. struct uart_omap_port *up = dev_get_drvdata(dev);
  1730.  
  1731. int loss_cnt = serial_omap_get_context_loss_count(up);
  1732.  
  1733. if (loss_cnt < 0) {
  1734. dev_err(dev, "serial_omap_get_context_loss_count failed : %d\n",
  1735. loss_cnt);
  1736. serial_omap_restore_context(up);
  1737. } else if (up->context_loss_cnt != loss_cnt) {
  1738. serial_omap_restore_context(up);
  1739. }
  1740. up->latency = up->calc_latency;
  1741. schedule_work(&up->qos_work);
  1742.  
  1743. return 0;
  1744. }
  1745. #endif
  1746.  
  1747. static const struct dev_pm_ops serial_omap_dev_pm_ops = {
  1748. SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
  1749. SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
  1750. serial_omap_runtime_resume, NULL)
  1751. };
  1752.  
  1753. #if defined(CONFIG_OF)
  1754. static const struct of_device_id omap_serial_of_match[] = {
  1755. { .compatible = "ti,omap2-uart" },
  1756. { .compatible = "ti,omap3-uart" },
  1757. { .compatible = "ti,omap4-uart" },
  1758. {},
  1759. };
  1760. MODULE_DEVICE_TABLE(of, omap_serial_of_match);
  1761. #endif
  1762.  
  1763. static struct platform_driver serial_omap_driver = {
  1764. .probe = serial_omap_probe,
  1765. .remove = serial_omap_remove,
  1766. .driver = {
  1767. .name = DRIVER_NAME,
  1768. .pm = &serial_omap_dev_pm_ops,
  1769. .of_match_table = of_match_ptr(omap_serial_of_match),
  1770. },
  1771. };
  1772.  
  1773. static int __init serial_omap_init(void)
  1774. {
  1775. int ret;
  1776.  
  1777. ret = uart_register_driver(&serial_omap_reg);
  1778. if (ret != 0)
  1779. return ret;
  1780. ret = platform_driver_register(&serial_omap_driver);
  1781. if (ret != 0)
  1782. uart_unregister_driver(&serial_omap_reg);
  1783. return ret;
  1784. }
  1785.  
  1786. static void __exit serial_omap_exit(void)
  1787. {
  1788. platform_driver_unregister(&serial_omap_driver);
  1789. uart_unregister_driver(&serial_omap_reg);
  1790. }
  1791.  
  1792. module_init(serial_omap_init);
  1793. module_exit(serial_omap_exit);
  1794.  
  1795. MODULE_DESCRIPTION("OMAP High Speed UART driver");
  1796. MODULE_LICENSE("GPL");
  1797. MODULE_AUTHOR("Texas Instruments Inc");
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