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Nov 24th, 2014
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  1. wire [BW-1:0] bus_array[NUM-1:0];
  2. reg [BW-1:0] and_result;
  3.  
  4. parameter BW = 4;
  5. parameter NUM = 8;
  6.  
  7. integer l;
  8.  
  9. generate
  10. genvar m;
  11. for (m=0; m<BW; m=m+1)
  12. begin : BW_LOOP
  13.  
  14. always @ (*)
  15. begin
  16. and_result[m] = 1'b1;
  17. for (l=0; l<NUM; l=l+1)
  18. and_result[m] = and_result[m] & bus_array[l][m];
  19. end
  20.  
  21. end
  22. endgenerate
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