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- wire [BW-1:0] bus_array[NUM-1:0];
- reg [BW-1:0] and_result;
- parameter BW = 4;
- parameter NUM = 8;
- integer l;
- generate
- genvar m;
- for (m=0; m<BW; m=m+1)
- begin : BW_LOOP
- always @ (*)
- begin
- and_result[m] = 1'b1;
- for (l=0; l<NUM; l=l+1)
- and_result[m] = and_result[m] & bus_array[l][m];
- end
- end
- endgenerate
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