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  1. ============================================================================
  2. Everything You Always Wanted To Know About GAMEBOY *
  3. ============================================================================
  4.  
  5. * but were afraid to ask
  6.  
  7.  
  8. Pan of -ATX- Document Updated by contributions from:
  9. Marat Fayzullin, Pascal Felber, Paul Robson, Martin Korth
  10.  
  11. Last update 12-Mar-98 by kOOPa
  12.  
  13. Forward: The following was typed up for informational purposes regarding
  14. the inner workings on the hand-held game machine known as
  15. GameBoy, manufactured and designed by Nintendo Co., LTD.
  16. This info is presented to inform a user on how their Game Boy
  17. works and what makes it "tick". GameBoy is copyrighted by
  18. Nintendo Co., LTD. Any reference to copyrighted material is
  19. not presented for monetary gain, but for educational purposes
  20. and higher learning.
  21.  
  22. Terms
  23. -----
  24.  
  25. GB = Original GameBoy
  26. GBP = GameBoy Pocket/GameBoy Light
  27. GBC = GameBoy Color
  28. SGB = Super GameBoy
  29.  
  30.  
  31. Game Boy Specs
  32. --------------
  33.  
  34. CPU: 8-bit (Similar to the Z80 processor.)
  35. Main RAM: 8K Byte
  36. Video RAM: 8K Byte
  37. Screen Size 2.6"
  38. Resolution: 160x144 (20x18 tiles)
  39. Max # of sprites: 40
  40. Max # sprites/line: 10
  41. Max sprite size: 8x16
  42. Min sprite size: 8x8
  43. Clock Speed: 4.194304 MHz (4.295454 SGB, 4.194/8.388MHz GBC)
  44. Horiz Sync: 9198 KHz (9420 KHz for SGB)
  45. Vert Sync: 59.73 Hz (61.17 Hz for SGB)
  46. Sound: 4 channels with stereo sound
  47. Power: DC6V 0.7W (DC3V 0.7W for GB Pocket)
  48.  
  49.  
  50. Processor
  51. ---------
  52.  
  53. The GameBoy uses a computer chip similar to an Intel 8080.
  54. It contains all of the instructions of an 8080 except there
  55. are no exchange instructions. In many ways the processor is
  56. more similar to the Zilog Z80 processor. Compared to the
  57. Z80, some instructions have been added and some have been
  58. taken away.
  59.  
  60. The following are added instructions:
  61.  
  62. ADD SP,nn ;nn = signed byte
  63. LDI (HL),A ;Write A to (HL) and increment HL
  64. LDD (HL),A ;Write A to (HL) and decrement HL
  65. LDI A,(HL) ;Write (HL) to A and increment HL
  66. LDD A,(HL) ;Write (HL) to A and decrement HL
  67. LD A,($FF00+nn)
  68. LD A,($FF00+C)
  69. LD ($FF00+nn),A
  70. LD ($FF00+C),A
  71. LD (nnnn),SP
  72. LD HL,SP+nn ;nn = signed byte
  73. STOP ;Stop processor & screen until button press
  74. SWAP r ;Swap high & low nibbles of r
  75.  
  76. The following instructions have been removed:
  77.  
  78. Any command that uses the IX or IY registers.
  79. All IN/OUT instructions.
  80. All exchange instructions.
  81. All commands prefixed by ED (except remapped RETI).
  82. All conditional jumps/calls/rets on parity/overflow and sign flag.
  83.  
  84. The following instructions have different opcodes:
  85.  
  86. LD A,[nnnn]
  87. LD [nnnn],A
  88. RETI
  89.  
  90.  
  91. General Memory Map* Hardware Write Registers
  92. ------------------ ------------------------
  93.  
  94. Interrupt Enable Register
  95. --------------------------- FFFF
  96. Internal RAM
  97. --------------------------- FF80
  98. Empty but unusable for I/O
  99. --------------------------- FF4C
  100. I/O ports
  101. --------------------------- FF00
  102. Empty but unusable for I/O
  103. --------------------------- FEA0
  104. Sprite Attrib Memory (OAM)
  105. --------------------------- FE00
  106. Echo of 8kB Internal RAM
  107. --------------------------- E000
  108. 8kB Internal RAM
  109. --------------------------- C000 -------------------------
  110. 8kB switchable RAM bank / MBC1 ROM/RAM Select
  111. --------------------------- A000 / ------------------------
  112. 8kB Video RAM / / RAM Bank Select
  113. --------------------------- 8000 --/ / -----------------------
  114. 16kB switchable ROM bank 6000 ----/ / ROM Bank Select
  115. --------------------------- 4000 ------/ ----------------------
  116. 16kB ROM bank #0 2000 --------/ RAM Bank enable
  117. --------------------------- 0000 -------------------------------
  118.  
  119. * NOTE: b = bit, B = byte
  120.  
  121.  
  122. Echo of 8kB Internal RAM
  123. ------------------------
  124.  
  125. The addresses E000-FE00 appear to access the internal RAM
  126. the same as C000-DE00. (i.e. If you write a byte to address
  127. E000 it will appear at C000 and E000. Similarly, writing a
  128. byte to C000 will appear at C000 and E000.)
  129.  
  130.  
  131. User I/O
  132. --------
  133.  
  134. There are no empty spaces in the memory map for
  135. implementing input ports except the switchable RAM bank
  136. area (not an option on the Super Smart Card since it's
  137. RAM bank is always enabled).
  138.  
  139. An output only port may be implemented anywhere between
  140. A000-FDFF. If implemented in a RAM area care should be
  141. taken to use an area of RAM not used for anything else.
  142. (FE00 and above can't be used because the CPU doesn't
  143. generate an external /WR for these locations.)
  144.  
  145. If you have a cart with an MBC1, a ROM 4Mbit or smaller,
  146. and a RAM 8Kbyte or smaller (or no RAM) then you can use
  147. pins 6 & 7 of the MBC1 for 2 digital output pins for
  148. whatever purpose you wish. To use them you must first
  149. put the MBC1 into 4MbitROM/32KbyteRAM mode by writing
  150. 01 to 6000. The two least significant bits you write
  151. to 4000 will then be output to these pins.
  152.  
  153.  
  154. Reserved Memory Locations
  155. -------------------------
  156.  
  157. 0000 Restart $00 Address (RST $00 calls this address.)
  158.  
  159. 0008 Restart $08 Address (RST $08 calls this address.)
  160.  
  161. 0010 Restart $10 Address (RST $10 calls this address.)
  162.  
  163. 0018 Restart $18 Address (RST $18 calls this address.)
  164.  
  165. 0020 Restart $20 Address (RST $20 calls this address.)
  166.  
  167. 0028 Restart $28 Address (RST $28 calls this address.)
  168.  
  169. 0030 Restart $30 Address (RST $30 calls this address.)
  170.  
  171. 0038 Restart $38 Address (RST $38 calls this address.)
  172.  
  173. 0040 Vertical Blank Interrupt Start Address
  174.  
  175. 0048 LCDC Status Interrupt Start Address
  176.  
  177. 0050 Timer Overflow Interrupt Start Address
  178.  
  179. 0058 Serial Transfer Completion Interrupt Start Address
  180.  
  181. 0060 High-to-Low of P10-P13 Interrupt Start Address
  182.  
  183. An internal information area is located at 0100-014F in
  184. each cartridge. It contains the following values:
  185.  
  186. 0100-0103 This is the begin code execution point in a
  187. cart. Usually there is a NOP and a JP
  188. instruction here but not always.
  189.  
  190. 0104-0133 Scrolling Nintendo graphic:
  191. CE ED 66 66 CC 0D 00 0B 03 73 00 83 00 0C 00 0D
  192. 00 08 11 1F 88 89 00 0E DC CC 6E E6 DD DD D9 99
  193. BB BB 67 63 6E 0E EC CC DD DC 99 9F BB B9 33 3E
  194. ( PROGRAM WON'T RUN IF CHANGED!!!)
  195.  
  196. 0134-0142 Title of the game in UPPER CASE ASCII. If it
  197. is less than 16 characters then the remaining
  198. bytes are filled with 00's.
  199.  
  200. 0143 $80 = Color GB, $00 or other = not Color GB
  201.  
  202. 0144 Ascii hex digit, high nibble of licensee code (new).
  203. 0145 Ascii hex digit, low nibble of licensee code (new).
  204. (These are normally $00 if [$014B] <> $33.)
  205.  
  206. 0146 GB/SGB Indicator (00 = GameBoy, 03 = Super GameBoy functions)
  207. (Super GameBoy functions won't work if <> $03.)
  208.  
  209. 0147 Cartridge type:
  210. 0 - ROM ONLY 12 - ROM+MBC3+RAM
  211. 1 - ROM+MBC1 13 - ROM+MBC3+RAM+BATT
  212. 2 - ROM+MBC1+RAM 19 - ROM+MBC5
  213. 3 - ROM+MBC1+RAM+BATT 1A - ROM+MBC5+RAM
  214. 5 - ROM+MBC2 1B - ROM+MBC5+RAM+BATT
  215. 6 - ROM+MBC2+BATTERY 1C - ROM+MBC5+RUMBLE
  216. 8 - ROM+RAM 1D - ROM+MBC5+RUMBLE+SRAM
  217. 9 - ROM+RAM+BATTERY 1E - ROM+MBC5+RUMBLE+SRAM+BATT
  218. B - ROM+MMM01 1F - Pocket Camera
  219. C - ROM+MMM01+SRAM FD - Bandai TAMA5
  220. D - ROM+MMM01+SRAM+BATT FE - Hudson HuC-3
  221. F - ROM+MBC3+TIMER+BATT FF - Hudson HuC-1
  222. 10 - ROM+MBC3+TIMER+RAM+BATT
  223. 11 - ROM+MBC3
  224.  
  225. 0148 ROM size:
  226. 0 - 256Kbit = 32KByte = 2 banks
  227. 1 - 512Kbit = 64KByte = 4 banks
  228. 2 - 1Mbit = 128KByte = 8 banks
  229. 3 - 2Mbit = 256KByte = 16 banks
  230. 4 - 4Mbit = 512KByte = 32 banks
  231. 5 - 8Mbit = 1MByte = 64 banks
  232. 6 - 16Mbit = 2MByte = 128 banks
  233. $52 - 9Mbit = 1.1MByte = 72 banks
  234. $53 - 10Mbit = 1.2MByte = 80 banks
  235. $54 - 12Mbit = 1.5MByte = 96 banks
  236.  
  237. 0149 RAM size:
  238. 0 - None
  239. 1 - 16kBit = 2kB = 1 bank
  240. 2 - 64kBit = 8kB = 1 bank
  241. 3 - 256kBit = 32kB = 4 banks
  242. 4 - 1MBit =128kB =16 banks
  243.  
  244. 014A Destination code:
  245. 0 - Japanese
  246. 1 - Non-Japanese
  247.  
  248. 014B Licensee code (old):
  249. 33 - Check 0144/0145 for Licensee code.
  250. 79 - Accolade
  251. A4 - Konami
  252. (Super GameBoy function won't work if <> $33.)
  253.  
  254. 014C Mask ROM Version number (Usually $00)
  255.  
  256. 014D Complement check
  257. (PROGRAM WON'T RUN ON GB IF NOT CORRECT!!!)
  258. (It will run on Super GB, however, if incorrect.)
  259.  
  260. 014E-014F Checksum (higher byte first) produced by
  261. adding all bytes of a cartridge except for two
  262. checksum bytes and taking two lower bytes of
  263. the result. (GameBoy ignores this value.)
  264.  
  265.  
  266. Cartridge Types
  267. ---------------
  268.  
  269. The following define the byte at cart location 0147:
  270.  
  271. ROM ONLY
  272. This is a 32kB (256kb) ROM and occupies 0000-7FFF.
  273.  
  274. MBC1 (Memory Bank Controller 1)
  275. MBC1 has two different maximum memory modes:
  276. 16Mbit ROM/8KByte RAM or 4Mbit ROM/32KByte RAM.
  277.  
  278. The MBC1 defaults to 16Mbit ROM/8KByte RAM mode
  279. on power up. Writing a value (XXXXXXXS - X = Don't
  280. care, S = Memory model select) into 6000-7FFF area
  281. will select the memory model to use. S = 0 selects
  282. 16/8 mode. S = 1 selects 4/32 mode.
  283.  
  284. Writing a value (XXXBBBBB - X = Don't cares, B =
  285. bank select bits) into 2000-3FFF area will select an
  286. appropriate ROM bank at 4000-7FFF. Values of 0 and 1
  287. do the same thing and point to ROM bank 1. Rom bank 0
  288. is not accessible from 4000-7FFF and can only be read
  289. from 0000-3FFF.
  290.  
  291. If memory model is set to 4/32:
  292. Writing a value (XXXXXXBB - X = Don't care, B =
  293. bank select bits) into 4000-5FFF area will select an
  294. appropriate RAM bank at A000-C000. Before you can
  295. read or write to a RAM bank you have to enable it by
  296. writing a XXXX1010 into 0000-1FFF area*. To disable
  297. RAM bank operations write any value but XXXX1010
  298. into 0000-1FFF area. Disabling a RAM bank probably
  299. protects that bank from false writes during power
  300. down of the GameBoy. (NOTE: Nintendo suggests values
  301. $0A to enable and $00 to disable RAM bank!!)
  302.  
  303. If memory model is set to 16/8 mode:
  304. Writing a value (XXXXXXBB - X = Don't care, B =
  305. bank select bits) into 4000-5FFF area will set the
  306. two most significant ROM address lines.
  307.  
  308. * NOTE: The Super Smart Card doesn't require this
  309. operation because it's RAM bank is ALWAYS enabled.
  310. Include this operation anyway to allow your code
  311. to work with both.
  312.  
  313. MBC2 (Memory Bank Controller 2):
  314. This memory controller works much like the MBC1
  315. controller with the following exceptions:
  316.  
  317. MBC2 will work with ROM sizes up to 2Mbit.
  318.  
  319. Writing a value (XXXXBBBB - X = Don't cares, B =
  320. bank select bits) into 2000-3FFF area will select an
  321. appropriate ROM bank at 4000-7FFF.
  322.  
  323. RAM switching is not provided. Unlike the MBC1 which
  324. uses external RAM, MBC2 has 512 x 4 bits of RAM which
  325. is in the controller itself. It still requires an
  326. external battery to save data during power-off though.
  327.  
  328. The least significant bit of the upper address byte
  329. must be zero to enable/disable cart RAM. For example
  330. the following addresses can be used to enable/disable
  331. cart RAM:
  332. 0000-00FF, 0200-02FF, 0400-04FF, ..., 1E00-1EFF.
  333. The suggested address range to use for MBC2 ram
  334. enable/disable is 0000-00FF.
  335.  
  336. The least significant bit of the upper address byte
  337. must be one to select a ROM bank. For example the
  338. following addresses can be used to select a ROM bank:
  339. 2100-21FF, 2300-23FF, 2500-25FF, ..., 3F00-3FFF.
  340. The suggested address range to use for MBC2 rom
  341. bank selection is 2100-21FF.
  342.  
  343. MBC3 (Memory Bank Controller 3):
  344. This controller is similar to MBC1 except it accesses
  345. all 16mbits of ROM without requiring any writes to the
  346. 4000-5FFF area.
  347. Writing a value (XBBBBBBB - X = Don't care, B =
  348. bank select bits) into 2000-3FFF area will select an
  349. appropriate ROM bank at 4000-7FFF.
  350.  
  351. Also, this MBC has a built-in battery-backed Real
  352. Time Clock (RTC) not found in any other MBC. Some
  353. MBC3 carts do not support it (WarioLand II non-color
  354. version) but some do (Harvest Moon/Japanese version.)
  355.  
  356. MBC5 (Memory Bank Controller 5):
  357. This controller is the first MBC that is guaranteed
  358. to run in GameBoy Color double-speed mode but it
  359. appears the other MBC's run fine in GBC double-speed
  360. mode as well.
  361.  
  362. It is similar to the MBC3 (but no RTC) but can
  363. access up to 64mbits of ROM and up to 1mbit of RAM.
  364. The lower 8 bits of the 9-bit rom bank select is
  365. written to the 2000-2FFF area while the upper bit
  366. is written to the least significant bit of the
  367. 3000-3FFF area.
  368.  
  369. Writing a value (XXXXBBBB - X = Don't care, B =
  370. bank select bits) into 4000-5FFF area will select an
  371. appropriate RAM bank at A000-BFFF if the cart
  372. contains RAM. Ram sizes are 64kbit,256kbit, & 1mbit.
  373.  
  374. Also, this is the first MBC that allows rom bank 0
  375. to appear in the 4000-7FFF range by writing $000
  376. to the rom bank select.
  377.  
  378. Rumble Carts:
  379. Rumble carts use an MBC5 memory bank controller.
  380. Rumble carts can only have up to 256kbits of RAM.
  381. The highest RAM address line that allows 1mbit of
  382. RAM on MBC5 non-rumble carts is used as the motor
  383. on/off for the rumble cart.
  384.  
  385. Writing a value (XXXXMBBB - X = Don't care, M =
  386. motor, B = bank select bits) into 4000-5FFF area
  387. will select an appropriate RAM bank at A000-BFFF
  388. if the cart contains RAM. RAM sizes are 64kbit or
  389. 256kbits. To turn the rumble motor on set M = 1,
  390. M = 0 turns it off.
  391.  
  392. HuC1 (Memory Bank / Infrared Controller):
  393. This controller made by Hudson Soft appears to be
  394. very similar to an MBC1 with the main difference
  395. being that it supports infrared LED input / output.
  396. The Japanese cart "Fighting Phoenix" (internal cart
  397. name: SUPER B DAMAN) is known to contain this chip.
  398.  
  399.  
  400.  
  401. Power Up Sequence
  402. -----------------
  403.  
  404. When the GameBoy is powered up, a 256 byte program
  405. starting at memory location 0 is executed. This program
  406. is located in a ROM inside the GameBoy. The first thing
  407. the program does is read the cartridge locations from
  408. $104 to $133 and place this graphic of a Nintendo logo
  409. on the screen at the top. This image is then scrolled
  410. until it is in the middle of the screen. Two musical
  411. notes are then played on the internal speaker. Again,
  412. the cartridge locations $104 to $133 are read but this
  413. time they are compared with a table in the internal rom.
  414. If any byte fails to compare, then the GameBoy stops
  415. comparing bytes and simply halts all operations.
  416.  
  417. GB & GB Pocket:
  418. Next, the GameBoy starts adding all of the bytes
  419. in the cartridge from $134 to $14d. A value of 25
  420. decimal is added to this total. If the least
  421. significant byte of the result is a not a zero,
  422. then the GameBoy will stop doing anything.
  423.  
  424. Super GB:
  425. Even though the GB & GBP check the memory locations
  426. from $134 to $14d, the SGB doesn't.
  427.  
  428. If the above checks pass then the internal ROM is
  429. disabled and cartridge program execution begins at
  430. location $100 with the following register values:
  431.  
  432. AF=$01-GB/SGB, $FF-GBP, $11-GBC
  433. F =$B0
  434. BC=$0013
  435. DE=$00D8
  436. HL=$014D
  437. Stack Pointer=$FFFE
  438. [$FF05] = $00 ; TIMA
  439. [$FF06] = $00 ; TMA
  440. [$FF07] = $00 ; TAC
  441. [$FF10] = $80 ; NR10
  442. [$FF11] = $BF ; NR11
  443. [$FF12] = $F3 ; NR12
  444. [$FF14] = $BF ; NR14
  445. [$FF16] = $3F ; NR21
  446. [$FF17] = $00 ; NR22
  447. [$FF19] = $BF ; NR24
  448. [$FF1A] = $7F ; NR30
  449. [$FF1B] = $FF ; NR31
  450. [$FF1C] = $9F ; NR32
  451. [$FF1E] = $BF ; NR33
  452. [$FF20] = $FF ; NR41
  453. [$FF21] = $00 ; NR42
  454. [$FF22] = $00 ; NR43
  455. [$FF23] = $BF ; NR30
  456. [$FF24] = $77 ; NR50
  457. [$FF25] = $F3 ; NR51
  458. [$FF26] = $F1-GB, $F0-SGB ; NR52
  459. [$FF40] = $91 ; LCDC
  460. [$FF42] = $00 ; SCY
  461. [$FF43] = $00 ; SCX
  462. [$FF45] = $00 ; LYC
  463. [$FF47] = $FC ; BGP
  464. [$FF48] = $FF ; OBP0
  465. [$FF49] = $FF ; OBP1
  466. [$FF4A] = $00 ; WY
  467. [$FF4B] = $00 ; WX
  468. [$FFFF] = $00 ; IE
  469.  
  470. It is not a good idea to assume the above values
  471. will always exist. A later version GameBoy could
  472. contain different values than these at reset.
  473. Always set these registers on reset rather than
  474. assume they are as above.
  475.  
  476. Please note that GameBoy internal RAM on power up
  477. contains random data. All of the GameBoy emulators
  478. tend to set all RAM to value $00 on entry.
  479.  
  480. Cart RAM the first time it is accessed on a real
  481. GameBoy contains random data. It will only contain
  482. known data if the GameBoy code initializes it to
  483. some value.
  484.  
  485. Stop Mode
  486. ---------
  487.  
  488. The STOP command halts the GameBoy processor
  489. and screen until any button is pressed. The GB
  490. and GBP screen goes white with a single dark
  491. horizontal line. The GBC screen goes black.
  492.  
  493.  
  494. Low-Power Mode
  495. --------------
  496.  
  497. It is recommended that the HALT instruction be used
  498. whenever possible to reduce power consumption & extend
  499. the life of the batteries. This command stops the
  500. system clock reducing the power consumption of both
  501. the CPU and ROM.
  502.  
  503. The CPU will remain suspended until an interrupt
  504. occurs at which point the interrupt is serviced and
  505. then the instruction immediately following the HALT
  506. is executed. If interrupts are disabled (DI) then
  507. halt doesn't suspend operation but it does cause
  508. the program counter to stop counting for one
  509. instruction on the GB,GBP, and SGB as mentioned below.
  510.  
  511. Depending on how much CPU time is required by a game,
  512. the HALT instruction can extend battery life anywhere
  513. from 5 to 50% or possibly more.
  514.  
  515. WARNING: The instruction immediately following the
  516. HALT instruction is "skipped" when interrupts are
  517. disabled (DI) on the GB,GBP, and SGB. As a result,
  518. always put a NOP after the HALT instruction. This
  519. instruction skipping doesn't occur when interrupts
  520. are enabled (EI).
  521. This "skipping" does not seem to occur on the
  522. GameBoy Color even in regular GB mode. ($143=$00)
  523.  
  524. EXAMPLES from Martin Korth who documented this problem:
  525. (assuming interrupts disabled for all examples)
  526.  
  527. 1) This code causes the 'a' register to be incremented TWICE.
  528. 76 halt
  529. 3C inc a
  530.  
  531. 2) The next example is a bit more difficult. The following code
  532. 76 halt
  533. FA 34 12 ld a,(1234)
  534.  
  535. is effectively executed as
  536.  
  537. 76 halt
  538. FA FA 34 ld a,(34FA)
  539. 12 ld (de),a
  540.  
  541. 3) Finally an interesting side effect
  542. 76 halt
  543. 76 halt
  544.  
  545. This combination hangs the cpu.
  546. The first HALT causes the second HALT to be repeated, which
  547. therefore causes the following command (=itself) to be
  548. repeated - again and again.
  549. Placing a NOP between the two halts would cause the NOP to
  550. be repeated once, the second HALT wouldn't lock the cpu.
  551.  
  552. Below is suggested code for GameBoy programs:
  553.  
  554. ; **** Main Game Loop ****
  555. Main:
  556. halt ; stop system clock
  557. ; return from halt when interrupted
  558. nop ; (See WARNING above.)
  559.  
  560. ld a,(VblnkFlag)
  561. or a ; V-Blank interrupt ?
  562. jr z,Main ; No, some other interrupt
  563.  
  564. xor a
  565. ld (VblnkFlag),a ; Clear V-Blank flag
  566.  
  567. call Controls ; button inputs
  568. call Game ; game operation
  569.  
  570. jr Main
  571.  
  572. ; **** V-Blank Interrupt Routine ****
  573. Vblnk:
  574. push af
  575. push bc
  576. push de
  577. push hl
  578.  
  579. call SpriteDma ; Do sprite updates
  580.  
  581. ld a,1
  582. ld (VblnkFlag),a
  583.  
  584. pop hl
  585. pop de
  586. pop bc
  587. pop af
  588. reti
  589.  
  590.  
  591. Video
  592. -----
  593.  
  594. The main GameBoy screen buffer (background) consists
  595. of 256x256 pixels or 32x32 tiles (8x8 pixels each). Only
  596. 160x144 pixels can be displayed on the screen. Registers
  597. SCROLLX and SCROLLY hold the coordinates of background to
  598. be displayed in the left upper corner of the screen.
  599. Background wraps around the screen (i.e. when part of it
  600. goes off the screen, it appears on the opposite side.)
  601.  
  602. An area of VRAM known as Background Tile Map contains
  603. the numbers of tiles to be displayed. It is organized as
  604. 32 rows of 32 bytes each. Each byte contains a number of
  605. a tile to be displayed. Tile patterns are taken from the
  606. Tile Data Table located either at $8000-8FFF or
  607. $8800-97FF. In the first case, patterns are numbered with
  608. unsigned numbers from 0 to 255 (i.e. pattern #0 lies at
  609. address $8000). In the second case, patterns have signed
  610. numbers from -128 to 127 (i.e. pattern #0 lies at address
  611. $9000). The Tile Data Table address for the background
  612. can be selected by setting the LCDC register.
  613.  
  614. There are two different Background Tile Maps. One is
  615. located from $9800-9Bff. The other from $9C00-9FFF.
  616. Only one of these can be viewed at any one time. The
  617. currently displayed background can be selected by
  618. setting the LCDC register.
  619.  
  620. Besides background, there is also a "window" overlaying
  621. the background. The window is not scrollable i.e. it is
  622. always displayed starting from its left upper corner. The
  623. location of a window on the screen can be adjusted via
  624. WNDPOSX and WNDPOSY registers. Screen coordinates of the
  625. top left corner of a window are WNDPOSX-7,WNDPOSY. The
  626. tile numbers for the window are stored in the Tile Data
  627. Table. None of the windows tiles are ever transparent.
  628. Both the Background and the window share the same Tile
  629. Data Table.
  630.  
  631. Both background and window can be disabled or enabled
  632. separately via bits in the LCDC register.
  633.  
  634. If the window is used and a scan line interrupt disables
  635. it (either by writing to LCDC or by setting WX > 166)
  636. and a scan line interrupt a little later on enables it
  637. then the window will resume appearing on the screen at the
  638. exact position of the window where it left off earlier.
  639. This way, even if there are only 16 lines of useful graphics
  640. in the window, you could display the first 8 lines at the
  641. top of the screen and the next 8 lines at the bottom if
  642. you wanted to do so.
  643.  
  644. WX may be changed during a scan line interrupt (to either
  645. cause a graphic distortion effect or to disable the window
  646. (WX>166) ) but changes to WY are not dynamic and won't
  647. be noticed until the next screen redraw.
  648.  
  649. The tile images are stored in the Tile Pattern Tables.
  650. Each 8x8 image occupies 16 bytes, where each 2 bytes
  651. represent a line:
  652.  
  653. Tile: Image:
  654.  
  655. .33333.. .33333.. -> 01111100 -> $7C
  656. 22...22. 01111100 -> $7C
  657. 11...11. 22...22. -> 00000000 -> $00
  658. 2222222. <-- digits 11000110 -> $C6
  659. 33...33. represent 11...11. -> 11000110 -> $C6
  660. 22...22. color 00000000 -> $00
  661. 11...11. numbers 2222222. -> 00000000 -> $00
  662. ........ 11111110 -> $FE
  663. 33...33. -> 11000110 -> $C6
  664. 11000110 -> $C6
  665. 22...22. -> 00000000 -> $00
  666. 11000110 -> $C6
  667. 11...11. -> 11000110 -> $C6
  668. 00000000 -> $00
  669. ........ -> 00000000 -> $00
  670. 00000000 -> $00
  671.  
  672. As it was said before, there are two Tile Pattern Tables
  673. at $8000-8FFF and at $8800-97FF. The first one can be used
  674. for sprites, the background, and the window display. Its
  675. tiles are numbered from 0 to 255. The second table can be
  676. used for the background and the window display and its tiles
  677. are numbered from -128 to 127.
  678.  
  679.  
  680. Sprites
  681. ------
  682.  
  683. GameBoy video controller can display up to 40 sprites
  684. either in 8x8 or in 8x16 pixels. Because of a limitation
  685. of hardware, only ten sprites can be displayed per scan
  686. line. Sprite patterns have the same format as tiles, but
  687. they are taken from the Sprite Pattern Table located at
  688. $8000-8FFF and have unsigned numbering. Sprite
  689. attributes reside in the Sprite Attribute Table (OAM
  690. - Object Attribute Memory) at $FE00-FE9F. OAM is divided
  691. into 40 4-byte blocks each of which corresponds to a sprite.
  692.  
  693. In 8x16 sprite mode, the least significant bit of the
  694. sprite pattern number is ignored and treated as 0.
  695.  
  696. When sprites with different x coordinate values overlap,
  697. the one with the smaller x coordinate (closer to the left)
  698. will have priority and appear above any others.
  699.  
  700. When sprites with the same x coordinate values overlap,
  701. they have priority according to table ordering. (i.e.
  702. $FE00 - highest, $FE04 - next highest, etc.)
  703.  
  704. Please note that Sprite X=0, Y=0 hides a sprite. To
  705. display a sprite use the following formulas:
  706.  
  707. SpriteScreenPositionX(Upper left corner of sprite) = SpriteX - 8
  708. SpriteScreenPositionY(Upper left corner of sprite) = SpriteY - 16
  709.  
  710. To display a sprite in the upper left corner of the
  711. screen set sprite X=8, Y=16.
  712.  
  713. Only 10 sprites can be displayed on any one line.
  714. When this limit is exceeded, the lower priority sprites
  715. (priorities listed above) won't be displayed. To keep
  716. unused sprites from affecting onscreen sprites set their
  717. Y coordinate to Y=0 or Y=>144+16. Just setting the X
  718. coordinate to X=0 or X=>160+8 on a sprite will hide it
  719. but it will still affect other sprites sharing the same
  720. lines.
  721.  
  722. Blocks have the following
  723. format:
  724.  
  725. Byte0 Y position on the screen
  726. Byte1 X position on the screen
  727. Byte2 Pattern number 0-255 (Unlike some tile
  728. numbers, sprite pattern numbers are unsigned.
  729. LSB is ignored (treated as 0) in 8x16 mode.)
  730. Byte3 Flags:
  731.  
  732. Bit7 Priority
  733. If this bit is set to 0, sprite is displayed
  734. on top of background & window. If this bit
  735. is set to 1, then sprite will be hidden behind
  736. colors 1, 2, and 3 of the background & window.
  737. (Sprite only prevails over color 0 of BG & win.)
  738. Bit6 Y flip
  739. Sprite pattern is flipped vertically if
  740. this bit is set to 1.
  741. Bit5 X flip
  742. Sprite pattern is flipped horizontally if
  743. this bit is set to 1.
  744. Bit4 Palette number
  745. Sprite colors are taken from OBJ1PAL if
  746. this bit is set to 1 and from OBJ0PAL
  747. otherwise.
  748.  
  749.  
  750. Sprite RAM Bug
  751. --------------
  752.  
  753. There is a flaw in the GameBoy hardware that causes
  754. trash to be written to OAM RAM if the following commands
  755. are used while their 16-bit content is in the range
  756. of $FE00 to $FEFF:
  757.  
  758. inc xx (xx = bc,de, or hl)
  759. dec xx
  760.  
  761. ldi a,(hl)
  762. ldd a,(hl)
  763.  
  764. ldi (hl),a
  765. ldd (hl),a
  766.  
  767. Only sprites 1 & 2 ($FE00 & $FE04) are not affected
  768. by these instructions.
  769.  
  770.  
  771. Sound
  772. -----
  773.  
  774. There are two sound channels connected to the output
  775. terminals SO1 and SO2. There is also a input terminal Vin
  776. connected to the cartridge. It can be routed to either of
  777. both output terminals. GameBoy circuitry allows producing
  778. sound in four different ways:
  779.  
  780. Quadrangular wave patterns with sweep and envelope functions.
  781. Quadrangular wave patterns with envelope functions.
  782. Voluntary wave patterns from wave RAM.
  783. White noise with an envelope function.
  784.  
  785. These four sounds can be controlled independantly and
  786. then mixed separately for each of the output terminals.
  787.  
  788. Sound registers may be set at all times while producing
  789. sound.
  790.  
  791. When setting the initial value of the envelope and
  792. restarting the length counter, set the initial flag to 1
  793. and initialize the data.
  794.  
  795. Under the following situations the Sound ON flag is
  796. reset and the sound output stops:
  797.  
  798. 1. When the sound output is stopped by the length counter.
  799. 2. When overflow occurs at the addition mode while sweep
  800. is operating at sound 1.
  801.  
  802. When the Sound OFF flag for sound 3 (bit 7 of NR30) is
  803. set at 0, the cancellation of the OFF mode must be done
  804. by setting the sound OFF flag to 1. By initializing
  805. sound 3, it starts it's function.
  806.  
  807. When the All Sound OFF flag (bit 7 of NR52) is set to 0,
  808. the mode registers for sounds 1,2,3, and 4 are reset and
  809. the sound output stops. (NOTE: The setting of each sounds
  810. mode register must be done after the All Sound OFF mode
  811. is cancelled. During the All Sound OFF mode, each sound
  812. mode register cannot be set.)
  813.  
  814. NOTE: DURING THE ALL SOUND OFF MODE, GB POWER CONSUMPTION
  815. DROPS BY 16% OR MORE! WHILE YOUR PROGRAMS AREN'T USING
  816. SOUND THEN SET THE ALL SOUND OFF FLAG TO 0. IT DEFAULTS
  817. TO 1 ON RESET.
  818.  
  819. These tend to be the two most important equations in
  820. converting between Hertz and GB frequency registers:
  821. (Sounds will have a 2.4% higher frequency on Super GB.)
  822.  
  823. gb = 2048 - (131072 / Hz)
  824.  
  825. Hz = 131072 / (2048 - gb)
  826.  
  827.  
  828. Timer
  829. -----
  830.  
  831. Sometimes it's useful to have a timer that interrupts at
  832. regular intervals for routines that require periodic or
  833. percise updates. The timer in the GameBoy has a selectable
  834. frequency of 4096, 16384, 65536, or 262144 Hertz. This
  835. frequency increments the Timer Counter (TIMA). When it
  836. overflows, it generates an interrupt. It is then loaded
  837. with the contents of Timer Modulo (TMA). The following
  838. are examples:
  839.  
  840. ;This interval timer interrupts 4096 times per second
  841.  
  842. ld a,-1
  843. ld ($FF06),a ;Set TMA to divide clock by 1
  844. ld a,4
  845. ld ($FF07),a ;Set clock to 4096 Hertz
  846.  
  847. ;This interval timer interrupts 65536 times per second
  848.  
  849. ld a,-4
  850. ld ($FF06),a ;Set TMA to divide clock by 4
  851. ld a,5
  852. ld ($FF07),a ;Set clock to 262144 Hertz
  853.  
  854.  
  855. Serial I/O
  856. ----------
  857.  
  858. The serial I/O port on the Gameboy is a very simple setup
  859. and is crude compared to standard RS-232 (IBM-PC) or RS-485
  860. (Macintosh) serial ports. There are no start or stop bits
  861. so the programmer must be more creative when using this port.
  862.  
  863. During a transfer, a byte is shifted in at the same time
  864. that a byte is shifted out. The rate of the shift is deter-
  865. mined by whether the clock source is internal or external.
  866. If internal, the bits are shifted out at a rate of 8192Hz
  867. (122 microseconds) per bit. The most significant bit is
  868. shifted in and out first.
  869.  
  870. When the internal clock is selected, it drives the clock
  871. pin on the game link port and it stays high when not used.
  872. During a transfer it will go low eight times to clock
  873. in/out each bit.
  874.  
  875. A programmer initates a serial transfer by setting bit 7
  876. of $FF02. This bit may be read and is automatically set
  877. to 0 at the completion of transfer. After this bit is set,
  878. an interrupt will then occur eight bit clocks later if the
  879. serial interrupt is enabled.
  880. If internal clock is selected and serial interrupt is
  881. enabled, this interrupt occurs 122*8 microseconds later.
  882. If external clock is selected and serial interrupt is
  883. enabled, an interrupt will occur eight bit clocks later.
  884.  
  885. Initiating a serial transfer with external clock will
  886. wait forever if no external clock is present. This allows
  887. a certain amount of synchronization with each serial port.
  888.  
  889. The state of the last bit shifted out determines the
  890. state of the output line until another transfer takes
  891. place.
  892.  
  893. If a serial transfer with internal clock is performed
  894. and no external GameBoy is present, a value of $FF will
  895. be received in the transfer.
  896.  
  897. The following code causes $75 to be shifted out the
  898. serial port and a byte to be shifted into $FF01:
  899.  
  900. ld a,$75
  901. ld ($FF01),a
  902. ld a,$81
  903. ld ($FF02),a
  904.  
  905.  
  906. Interrupt Procedure
  907. -------------------
  908.  
  909. The IME (interrupt master enable) flag is reset by DI and
  910. prohibits all interrupts. It is set by EI and acknowledges
  911. the interrupt setting by the IE register.
  912.  
  913. 1. When an interrupt is generated, the IF flag will be set.
  914. 2. If the IME flag is set & the corresponding IE flag is
  915. set, the following 3 steps are performed.
  916. 3. Reset the IME flag and prevent all interrupts.
  917. 4. The PC (program counter) is pushed onto the stack.
  918. 5. Jump to the starting address of the interrupt.
  919.  
  920. Resetting of the IF register, which was the cause of the
  921. interrupt, is done by hardware.
  922.  
  923. During the interrupt, pushing of registers to be used
  924. should be performed by the interrupt routine.
  925.  
  926. Once the interrupt service is in progress, all the
  927. interrupts will be prohibited. However, if the IME flag
  928. and the IE flag are controlled, a number of interrupt
  929. services can be made possible by nesting.
  930.  
  931. Return from an interrupt routine can be performed by
  932. either RETI or RET instruction.
  933.  
  934. The RETI instruction enables interrupts after doing a
  935. return operation.
  936.  
  937. If a RET is used as the final instruction in an interrupt
  938. routine, interrupts will remain disabled unless a EI was
  939. used in the interrupt routine or is used at a later time.
  940.  
  941. The interrupt will be acknowledged during opcode fetch
  942. period of each instruction.
  943.  
  944.  
  945. Interrupt Descriptions
  946. ----------------------
  947.  
  948. The following interrupts only occur if they have been
  949. enabled in the Interrupt Enable register ($FFFF) and
  950. if the interrupts have actually been enabled using the
  951. EI instruction.
  952.  
  953. V-Blank -
  954.  
  955. The V-Blank interrupt occurs ~59.7 times a second
  956. on a regular GB and ~61.1 times a second on a Super
  957. GB (SGB). This interrupt occurs at the beginning of
  958. the V-Blank period. During this period video hardware
  959. is not using video ram so it may be freely accessed.
  960. This period lasts approximately 1.1 milliseconds.
  961.  
  962. LCDC Status -
  963.  
  964. There are various reasons for this interrupt to occur
  965. as described by the STAT register ($FF40). One very
  966. popular reason is to indicate to the user when the
  967. video hardware is about to redraw a given LCD line.
  968. This can be useful for dynamically controlling the SCX/
  969. SCY registers ($FF43/$FF42) to perform special video
  970. effects.
  971.  
  972. Timer Overflow -
  973.  
  974. This interrupt occurs when the TIMA register ($FF05)
  975. changes from $FF to $00.
  976.  
  977. Serial Transfer Completion -
  978.  
  979. This interrupt occurs when a serial transfer has
  980. completed on the game link port.
  981.  
  982. High-to-Low of P10-P13 -
  983.  
  984. This interrupt occurs on a transition of any of the
  985. keypad input lines from high to low. Due to the fact
  986. that keypad "bounce"* is virtually always present,
  987. software should expect this interrupt to occur one
  988. or more times for every button press and one or more
  989. times for every button release.
  990.  
  991. * - Bounce tends to be a side effect of any button
  992. making or breaking a connection. During these
  993. periods, it is very common for a small amount of
  994. oscillation between high & low states to take place.
  995.  
  996. I/O Registers
  997. -------------
  998.  
  999. FF00
  1000. Name - P1
  1001. Contents - Register for reading joy pad info
  1002. and determining system type. (R/W)
  1003.  
  1004. Bit 7 - Not used
  1005. Bit 6 - Not used
  1006. Bit 5 - P15 out port
  1007. Bit 4 - P14 out port
  1008. Bit 3 - P13 in port
  1009. Bit 2 - P12 in port
  1010. Bit 1 - P11 in port
  1011. Bit 0 - P10 in port
  1012.  
  1013. This is the matrix layout for register $FF00:
  1014.  
  1015.  
  1016. P14 P15
  1017. | |
  1018. P10-------O-Right----O-A
  1019. | |
  1020. P11-------O-Left-----O-B
  1021. | |
  1022. P12-------O-Up-------O-Select
  1023. | |
  1024. P13-------O-Down-----O-Start
  1025. | |
  1026.  
  1027. Example code:
  1028.  
  1029. Game: Ms. Pacman
  1030. Address: $3b1
  1031.  
  1032. LD A,$20 <- bit 5 = $20
  1033. LD ($FF00),A <- select P14 by setting it low
  1034. LD A,($FF00)
  1035. LD A,($FF00) <- wait a few cycles
  1036. CPL <- complement A
  1037. AND $0F <- get only first 4 bits
  1038. SWAP A <- swap it
  1039. LD B,A <- store A in B
  1040. LD A,$10
  1041. LD ($FF00),A <- select P15 by setting it low
  1042. LD A,($FF00)
  1043. LD A,($FF00)
  1044. LD A,($FF00)
  1045. LD A,($FF00)
  1046. LD A,($FF00)
  1047. LD A,($FF00) <- Wait a few MORE cycles
  1048. CPL <- complement (invert)
  1049. AND $0F <- get first 4 bits
  1050. OR B <- put A and B together
  1051.  
  1052. LD B,A <- store A in D
  1053. LD A,($FF8B) <- read old joy data from ram
  1054. XOR B <- toggle w/current button bit
  1055. AND B <- get current button bit back
  1056. LD ($FF8C),A <- save in new Joydata storage
  1057. LD A,B <- put original value in A
  1058. LD ($FF8B),A <- store it as old joy data
  1059.  
  1060.  
  1061. LD A,$30 <- deselect P14 and P15
  1062. LD ($FF00),A <- RESET Joypad
  1063. RET <- Return from Subroutine
  1064.  
  1065. The button values using the above method are such:
  1066. $80 - Start $8 - Down
  1067. $40 - Select $4 - Up
  1068. $20 - B $2 - Left
  1069. $10 - A $1 - Right
  1070.  
  1071. Let's say we held down A, Start, and Up.
  1072. The value returned in accumulator A would be $94
  1073.  
  1074.  
  1075. FF01
  1076. Name - SB
  1077. Contents - Serial transfer data (R/W)
  1078.  
  1079. 8 Bits of data to be read/written
  1080.  
  1081. FF02
  1082. Name - SC
  1083. Contents - SIO control (R/W)
  1084.  
  1085. Bit 7 - Transfer Start Flag
  1086. 0: Non transfer
  1087. 1: Start transfer
  1088.  
  1089. Bit 0 - Shift Clock
  1090. 0: External Clock (500KHz Max.)
  1091. 1: Internal Clock (8192Hz)
  1092.  
  1093. Transfer is initiated by setting the
  1094. Transfer Start Flag. This bit may be read
  1095. and is automatically set to 0 at the end of
  1096. Transfer.
  1097.  
  1098. Transmitting and receiving serial data is
  1099. done simultaneously. The received data is
  1100. automatically stored in SB.
  1101.  
  1102. FF04
  1103. Name - DIV
  1104. Contents - Divider Register (R/W)
  1105.  
  1106. This register is incremented 16384 (~16779
  1107. on SGB) times a second. Writing any value
  1108. sets it to $00.
  1109. FF05
  1110. Name - TIMA
  1111. Contents - Timer counter (R/W)
  1112.  
  1113. This timer is incremented by a clock frequency
  1114. specified by the TAC register ($FF07). The timer
  1115. generates an interrupt when it overflows.
  1116.  
  1117. FF06
  1118. Name - TMA
  1119. Contents - Timer Modulo (R/W)
  1120.  
  1121. When the TIMA overflows, this data will be loaded.
  1122.  
  1123. FF07
  1124. Name - TAC
  1125. Contents - Timer Control (R/W)
  1126.  
  1127. Bit 2 - Timer Stop
  1128. 0: Stop Timer
  1129. 1: Start Timer
  1130.  
  1131. Bits 1+0 - Input Clock Select
  1132. 00: 4.096 KHz (~4.194 KHz SGB)
  1133. 01: 262.144 KHz (~268.4 KHz SGB)
  1134. 10: 65.536 KHz (~67.11 KHz SGB)
  1135. 11: 16.384 KHz (~16.78 KHz SGB)
  1136.  
  1137. FF0F
  1138. Name - IF
  1139. Contents - Interrupt Flag (R/W)
  1140.  
  1141. Bit 4: Transition from High to Low of Pin number P10-P13
  1142. Bit 3: Serial I/O transfer complete
  1143. Bit 2: Timer Overflow
  1144. Bit 1: LCDC (see STAT)
  1145. Bit 0: V-Blank
  1146.  
  1147. The priority and jump address for the above 5 interrupts are:
  1148.  
  1149. Interrupt Priority Start Address
  1150.  
  1151. V-Blank 1 $0040
  1152. LCDC Status 2 $0048 - Modes 0, 1, 2
  1153. LYC=LY coincide (selectable)
  1154. Timer Overflow 3 $0050
  1155. Serial Transfer 4 $0058 - when transfer is complete
  1156. Hi-Lo of P10-P13 5 $0060
  1157.  
  1158. * When more than 1 interrupts occur at the same time
  1159. only the interrupt with the highest priority can be
  1160. acknowledged. When an interrupt is used a '0' should
  1161. be stored in the IF register before the IE register
  1162. is set.
  1163.  
  1164.  
  1165. FF10
  1166. Name - NR 10
  1167. Contents - Sound Mode 1 register, Sweep register (R/W)
  1168.  
  1169. Bit 6-4 - Sweep Time
  1170. Bit 3 - Sweep Increase/Decrease
  1171. 0: Addition (frequency increases)
  1172. 1: Subtraction (frequency decreases)
  1173. Bit 2-0 - Number of sweep shift (n: 0-7)
  1174.  
  1175. Sweep Time: 000: sweep off - no freq change
  1176. 001: 7.8 ms (1/128Hz)
  1177. 010: 15.6 ms (2/128Hz)
  1178. 011: 23.4 ms (3/128Hz)
  1179. 100: 31.3 ms (4/128Hz)
  1180. 101: 39.1 ms (5/128Hz)
  1181. 110: 46.9 ms (6/128Hz)
  1182. 111: 54.7 ms (7/128Hz)
  1183.  
  1184. The change of frequency (NR13,NR14) at each shift
  1185. is calculated by the following formula where
  1186. X(0) is initial freq & X(t-1) is last freq:
  1187.  
  1188. X(t) = X(t-1) +/- X(t-1)/2^n
  1189.  
  1190. FF11
  1191. Name - NR 11
  1192. Contents - Sound Mode 1 register, Sound length/Wave pattern duty (R/W)
  1193.  
  1194. Only Bits 7-6 can be read.
  1195.  
  1196. Bit 7-6 - Wave Pattern Duty
  1197. Bit 5-0 - Sound length data (t1: 0-63)
  1198.  
  1199. Wave Duty: 00: 12.5% ( _--------_--------_-------- )
  1200. 01: 25% ( __-------__-------__------- )
  1201. 10: 50% ( ____-----____-----____----- ) (default)
  1202. 11: 75% ( ______---______---______--- )
  1203.  
  1204. Sound Length = (64-t1)*(1/256) seconds
  1205. FF12
  1206. Name - NR 12
  1207. Contents - Sound Mode 1 register, Envelope (R/W)
  1208.  
  1209. Bit 7-4 - Initial volume of envelope
  1210. Bit 3 - Envelope UP/DOWN
  1211. 0: Attenuate
  1212. 1: Amplify
  1213. Bit 2-0 - Number of envelope sweep (n: 0-7)
  1214. (If zero, stop envelope operation.)
  1215.  
  1216. Initial volume of envelope is from 0 to $F.
  1217. Zero being no sound.
  1218.  
  1219. Length of 1 step = n*(1/64) seconds
  1220.  
  1221. FF13
  1222. Name - NR 13
  1223. Contents - Sound Mode 1 register, Frequency lo (W)
  1224.  
  1225. Lower 8 bits of 11 bit frequency (x).
  1226. Next 3 bit are in NR 14 ($FF14)
  1227.  
  1228. FF14
  1229. Name - NR 14
  1230. Contents - Sound Mode 1 register, Frequency hi (R/W)
  1231.  
  1232. Only Bit 6 can be read.
  1233.  
  1234. Bit 7 - Initial (when set, sound restarts)
  1235. Bit 6 - Counter/consecutive selection
  1236. Bit 2-0 - Frequency's higher 3 bits (x)
  1237.  
  1238. Frequency = 4194304/(32*(2048-x)) Hz
  1239. = 131072/(2048-x) Hz
  1240.  
  1241. Counter/consecutive Selection
  1242. 0 = Regardless of the length data in NR11
  1243. sound can be produced consecutively.
  1244. 1 = Sound is generated during the time period
  1245. set by the length data in NR11. After this
  1246. period the sound 1 ON flag (bit 0 of NR52)
  1247. is reset.
  1248.  
  1249. FF16
  1250. Name - NR 21
  1251. Contents - Sound Mode 2 register, Sound Length; Wave Pattern Duty (R/W)
  1252.  
  1253. Only bits 7-6 can be read.
  1254.  
  1255. Bit 7-6 - Wave pattern duty
  1256. Bit 5-0 - Sound length data (t1: 0-63)
  1257.  
  1258. Wave Duty: 00: 12.5% ( _--------_--------_-------- )
  1259. 01: 25% ( __-------__-------__------- )
  1260. 10: 50% ( ____-----____-----____----- ) (default)
  1261. 11: 75% ( ______---______---______--- )
  1262.  
  1263. Sound Length = (64-t1)*(1/256) seconds
  1264.  
  1265. FF17
  1266. Name - NR 22
  1267. Contents - Sound Mode 2 register, envelope (R/W)
  1268.  
  1269. Bit 7-4 - Initial volume of envelope
  1270. Bit 3 - Envelope UP/DOWN
  1271. 0: Attenuate
  1272. 1: Amplify
  1273. Bit 2-0 - Number of envelope sweep (n: 0-7)
  1274. (If zero, stop envelope operation.)
  1275.  
  1276. Initial volume of envelope is from 0 to $F.
  1277. Zero being no sound.
  1278.  
  1279. Length of 1 step = n*(1/64) seconds
  1280.  
  1281. FF18
  1282. Name - NR 23
  1283. Contents - Sound Mode 2 register, frequency lo data (W)
  1284.  
  1285. Frequency's lower 8 bits of 11 bit data (x).
  1286. Next 3 bits are in NR 14 ($FF19).
  1287.  
  1288. FF19
  1289. Name - NR 24
  1290. Contents - Sound Mode 2 register, frequency hi data (R/W)
  1291.  
  1292. Only bit 6 can be read.
  1293.  
  1294. Bit 7 - Initial (when set, sound restarts)
  1295. Bit 6 - Counter/consecutive selection
  1296. Bit 2-0 - Frequency's higher 3 bits (x)
  1297.  
  1298. Frequency = 4194304/(32*(2048-x)) Hz
  1299. = 131072/(2048-x) Hz
  1300.  
  1301. Counter/consecutive Selection
  1302. 0 = Regardless of the length data in NR21
  1303. sound can be produced consecutively.
  1304. 1 = Sound is generated during the time period
  1305. set by the length data in NR21. After this
  1306. period the sound 2 ON flag (bit 1 of NR52)
  1307. is reset.
  1308.  
  1309. FF1A
  1310. Name - NR 30
  1311. Contents - Sound Mode 3 register, Sound on/off (R/W)
  1312.  
  1313. Only bit 7 can be read
  1314.  
  1315. Bit 7 - Sound OFF
  1316. 0: Sound 3 output stop
  1317. 1: Sound 3 output OK
  1318.  
  1319. FF1B
  1320. Name - NR 31
  1321. Contents - Sound Mode 3 register, sound length (R/W)
  1322.  
  1323. Bit 7-0 - Sound length (t1: 0 - 255)
  1324.  
  1325. Sound Length = (256-t1)*(1/2) seconds
  1326.  
  1327. FF1C
  1328. Name - NR 32
  1329. Contents - Sound Mode 3 register, Select output level (R/W)
  1330.  
  1331. Only bits 6-5 can be read
  1332.  
  1333. Bit 6-5 - Select output level
  1334. 00: Mute
  1335. 01: Produce Wave Pattern RAM Data as it is
  1336. (4 bit length)
  1337. 10: Produce Wave Pattern RAM data shifted once
  1338. to the RIGHT (1/2) (4 bit length)
  1339. 11: Produce Wave Pattern RAM data shifted twice
  1340. to the RIGHT (1/4) (4 bit length)
  1341.  
  1342. * - Wave Pattern RAM is located from $FF30-$FF3f.
  1343.  
  1344. FF1D
  1345. Name - NR 33
  1346. Contents - Sound Mode 3 register, frequency's lower data (W)
  1347.  
  1348. Lower 8 bits of an 11 bit frequency (x).
  1349.  
  1350. FF1E
  1351. Name - NR 34
  1352. Contents - Sound Mode 3 register, frequency's higher data (R/W)
  1353.  
  1354. Only bit 6 can be read.
  1355.  
  1356. Bit 7 - Initial (when set, sound restarts)
  1357. Bit 6 - Counter/consecutive flag
  1358. Bit 2-0 - Frequency's higher 3 bits (x).
  1359.  
  1360. Frequency = 4194304/(64*(2048-x)) Hz
  1361. = 65536/(2048-x) Hz
  1362.  
  1363. Counter/consecutive Selection
  1364. 0 = Regardless of the length data in NR31
  1365. sound can be produced consecutively.
  1366. 1 = Sound is generated during the time period
  1367. set by the length data in NR31. After this
  1368. period the sound 3 ON flag (bit 2 of NR52)
  1369. is reset.
  1370.  
  1371. FF20
  1372. Name - NR 41
  1373. Contents - Sound Mode 4 register, sound length (R/W)
  1374.  
  1375. Bit 5-0 - Sound length data (t1: 0-63)
  1376.  
  1377. Sound Length = (64-t1)*(1/256) seconds
  1378.  
  1379. FF21
  1380. Name - NR 42
  1381. Contents - Sound Mode 4 register, envelope (R/W)
  1382.  
  1383. Bit 7-4 - Initial volume of envelope
  1384. Bit 3 - Envelope UP/DOWN
  1385. 0: Attenuate
  1386. 1: Amplify
  1387. Bit 2-0 - Number of envelope sweep (n: 0-7)
  1388. (If zero, stop envelope operation.)
  1389.  
  1390. Initial volume of envelope is from 0 to $F.
  1391. Zero being no sound.
  1392.  
  1393. Length of 1 step = n*(1/64) seconds
  1394.  
  1395. FF22
  1396. Name - NR 43
  1397. Contents - Sound Mode 4 register, polynomial counter (R/W)
  1398.  
  1399. Bit 7-4 - Selection of the shift clock frequency of the
  1400. polynomial counter
  1401. Bit 3 - Selection of the polynomial counter's step
  1402. Bit 2-0 - Selection of the dividing ratio of frequencies
  1403.  
  1404. Selection of the dividing ratio of frequencies:
  1405. 000: f * 1/2^3 * 2
  1406. 001: f * 1/2^3 * 1
  1407. 010: f * 1/2^3 * 1/2
  1408. 011: f * 1/2^3 * 1/3
  1409. 100: f * 1/2^3 * 1/4
  1410. 101: f * 1/2^3 * 1/5
  1411. 110: f * 1/2^3 * 1/6
  1412. 111: f * 1/2^3 * 1/7 f = 4.194304 Mhz
  1413.  
  1414. Selection of the polynomial counter step:
  1415. 0: 15 steps
  1416. 1: 7 steps
  1417.  
  1418. Selection of the shift clock frequency of the polynomial
  1419. counter:
  1420.  
  1421. 0000: dividing ratio of frequencies * 1/2
  1422. 0001: dividing ratio of frequencies * 1/2^2
  1423. 0010: dividing ratio of frequencies * 1/2^3
  1424. 0011: dividing ratio of frequencies * 1/2^4
  1425. : :
  1426. : :
  1427. : :
  1428. 0101: dividing ratio of frequencies * 1/2^14
  1429. 1110: prohibited code
  1430. 1111: prohibited code
  1431.  
  1432. FF23
  1433. Name - NR 44
  1434. Contents - Sound Mode 4 register, counter/consecutive; inital (R/W)
  1435.  
  1436. Only bit 6 can be read.
  1437.  
  1438. Bit 7 - Initial (when set, sound restarts)
  1439. Bit 6 - Counter/consecutive selection
  1440.  
  1441. Counter/consecutive Selection
  1442. 0 = Regardless of the length data in NR41
  1443. sound can be produced consecutively.
  1444. 1 = Sound is generated during the time period
  1445. set by the length data in NR41. After this
  1446. period the sound 4 ON flag (bit 3 of NR52)
  1447. is reset.
  1448.  
  1449. FF24
  1450. Name - NR 50
  1451. Contents - Channel control / ON-OFF / Volume (R/W)
  1452.  
  1453. Bit 7 - Vin->SO2 ON/OFF
  1454. Bit 6-4 - SO2 output level (volume) (# 0-7)
  1455. Bit 3 - Vin->SO1 ON/OFF
  1456. Bit 2-0 - SO1 output level (volume) (# 0-7)
  1457.  
  1458. Vin->SO1 (Vin->SO2)
  1459.  
  1460. By synthesizing the sound from sound 1
  1461. through 4, the voice input from Vin
  1462. terminal is put out.
  1463. 0: no output
  1464. 1: output OK
  1465.  
  1466. FF25
  1467. Name - NR 51
  1468. Contents - Selection of Sound output terminal (R/W)
  1469.  
  1470. Bit 7 - Output sound 4 to SO2 terminal
  1471. Bit 6 - Output sound 3 to SO2 terminal
  1472. Bit 5 - Output sound 2 to SO2 terminal
  1473. Bit 4 - Output sound 1 to SO2 terminal
  1474. Bit 3 - Output sound 4 to SO1 terminal
  1475. Bit 2 - Output sound 3 to SO1 terminal
  1476. Bit 1 - Output sound 2 to SO1 terminal
  1477. Bit 0 - Output sound 1 to SO1 terminal
  1478.  
  1479. FF26
  1480. Name - NR 52 (Value at reset: $F1-GB, $F0-SGB)
  1481. Contents - Sound on/off (R/W)
  1482.  
  1483. Bit 7 - All sound on/off
  1484. 0: stop all sound circuits
  1485. 1: operate all sound circuits
  1486. Bit 3 - Sound 4 ON flag
  1487. Bit 2 - Sound 3 ON flag
  1488. Bit 1 - Sound 2 ON flag
  1489. Bit 0 - Sound 1 ON flag
  1490.  
  1491. Bits 0 - 3 of this register are meant to
  1492. be status bits to be read. Writing to these
  1493. bits does NOT enable/disable sound.
  1494.  
  1495. If your GB programs don't use sound then
  1496. write $00 to this register to save 16% or
  1497. more on GB power consumption.
  1498. FF30 - FF3F
  1499. Name - Wave Pattern RAM
  1500. Contents - Waveform storage for arbitrary sound data
  1501.  
  1502. This storage area holds 32 4-bit samples
  1503. that are played back upper 4 bits first.
  1504.  
  1505. FF40
  1506. Name - LCDC (value $91 at reset)
  1507. Contents - LCD Control (R/W)
  1508.  
  1509. Bit 7 - LCD Control Operation *
  1510. 0: Stop completely (no picture on screen)
  1511. 1: operation
  1512.  
  1513. Bit 6 - Window Tile Map Display Select
  1514. 0: $9800-$9BFF
  1515. 1: $9C00-$9FFF
  1516.  
  1517. Bit 5 - Window Display
  1518. 0: off
  1519. 1: on
  1520.  
  1521. Bit 4 - BG & Window Tile Data Select
  1522. 0: $8800-$97FF
  1523. 1: $8000-$8FFF <- Same area as OBJ
  1524.  
  1525. Bit 3 - BG Tile Map Display Select
  1526. 0: $9800-$9BFF
  1527. 1: $9C00-$9FFF
  1528.  
  1529. Bit 2 - OBJ (Sprite) Size
  1530. 0: 8*8
  1531. 1: 8*16 (width*height)
  1532.  
  1533. Bit 1 - OBJ (Sprite) Display
  1534. 0: off
  1535. 1: on
  1536.  
  1537. Bit 0 - BG Display
  1538. 0: off
  1539. 1: on
  1540.  
  1541. * - Stopping LCD operation (bit 7 from 1 to 0)
  1542. must be performed during V-blank to work
  1543. properly. V-blank can be confirmed when the
  1544. value of LY is greater than or equal to 144.
  1545.  
  1546. FF41
  1547. Name - STAT
  1548. Contents - LCDC Status (R/W)
  1549.  
  1550. Bits 6-3 - Interrupt Selection By LCDC Status
  1551.  
  1552. Bit 6 - LYC=LY Coincidence (Selectable)
  1553. Bit 5 - Mode 10
  1554. Bit 4 - Mode 01
  1555. Bit 3 - Mode 00
  1556. 0: Non Selection
  1557. 1: Selection
  1558.  
  1559. Bit 2 - Coincidence Flag
  1560. 0: LYC not equal to LCDC LY
  1561. 1: LYC = LCDC LY
  1562.  
  1563. Bit 1-0 - Mode Flag
  1564. 00: During H-Blank
  1565. 01: During V-Blank
  1566. 10: During Searching OAM-RAM
  1567. 11: During Transfering Data to LCD Driver
  1568.  
  1569. STAT shows the current status of the LCD controller.
  1570. Mode 00: When the flag is 00 it is the H-Blank period
  1571. and the CPU can access the display RAM
  1572. ($8000-$9FFF).
  1573.  
  1574. Mode 01: When the flag is 01 it is the V-Blank period
  1575. and the CPU can access the display RAM
  1576. ($8000-$9FFF).
  1577.  
  1578. Mode 10: When the flag is 10 then the OAM is being
  1579. used ($FE00-$FE9F). The CPU cannot access
  1580. the OAM during this period
  1581.  
  1582. Mode 11: When the flag is 11 both the OAM and display
  1583. RAM are being used. The CPU cannot access
  1584. either during this period.
  1585.  
  1586.  
  1587. The following are typical when the display is enabled:
  1588.  
  1589. Mode 0 000___000___000___000___000___000___000________________
  1590. Mode 1 _______________________________________11111111111111__
  1591. Mode 2 ___2_____2_____2_____2_____2_____2___________________2_
  1592. Mode 3 ____33____33____33____33____33____33__________________3
  1593.  
  1594.  
  1595. The Mode Flag goes through the values 0, 2,
  1596. and 3 at a cycle of about 109uS. 0 is present
  1597. about 48.6uS, 2 about 19uS, and 3 about 41uS. This
  1598. is interrupted every 16.6ms by the VBlank (1).
  1599. The mode flag stays set at 1 for about 1.08 ms.
  1600. (Mode 0 is present between 201-207 clks, 2 about
  1601. 77-83 clks, and 3 about 169-175 clks. A complete
  1602. cycle through these states takes 456 clks.
  1603. VBlank lasts 4560 clks. A complete screen refresh
  1604. occurs every 70224 clks.)
  1605.  
  1606. FF42
  1607. Name - SCY
  1608. Contents - Scroll Y (R/W)
  1609.  
  1610. 8 Bit value $00-$FF to scroll BG Y screen
  1611. position.
  1612.  
  1613. FF43
  1614. Name - SCX
  1615. Contents - Scroll X (R/W)
  1616.  
  1617. 8 Bit value $00-$FF to scroll BG X screen
  1618. position.
  1619.  
  1620. FF44
  1621. Name - LY
  1622. Contents - LCDC Y-Coordinate (R)
  1623.  
  1624. The LY indicates the vertical line to which
  1625. the present data is transferred to the LCD
  1626. Driver. The LY can take on any value between
  1627. 0 through 153. The values between 144 and 153
  1628. indicate the V-Blank period. Writing will
  1629. reset the counter.
  1630.  
  1631. FF45
  1632. Name - LYC
  1633. Contents - LY Compare (R/W)
  1634.  
  1635. The LYC compares itself with the LY. If the
  1636. values are the same it causes the STAT to set
  1637. the coincident flag.
  1638.  
  1639. FF46
  1640. Name - DMA
  1641. Contents - DMA Transfer and Start Address (W)
  1642.  
  1643. The DMA Transfer (40*28 bit) from internal ROM or RAM
  1644. ($0000-$F19F) to the OAM (address $FE00-$FE9F) can be
  1645. performed. It takes 160 microseconds for the transfer.
  1646.  
  1647. 40*28 bit = #140 or #$8C. As you can see, it only
  1648. transfers $8C bytes of data. OAM data is $A0 bytes
  1649. long, from $0-$9F.
  1650.  
  1651. But if you examine the OAM data you see that 4 bits are
  1652. not in use.
  1653.  
  1654. 40*32 bit = #$A0, but since 4 bits for each OAM is not
  1655. used it's 40*28 bit.
  1656.  
  1657. It transfers all the OAM data to OAM RAM.
  1658.  
  1659. The DMA transfer start address can be designated every
  1660. $100 from address $0000-$F100. That means $0000, $0100,
  1661. $0200, $0300....
  1662.  
  1663. As can be seen by looking at register $FF41 Sprite RAM
  1664. ($FE00 - $FE9F) is not always available. A simple routine
  1665. that many games use to write data to Sprite memory is shown
  1666. below. Since it copies data to the sprite RAM at the appro-
  1667. priate times it removes that responsibility from the main
  1668. program.
  1669. All of the memory space, except high ram ($FF80-$FFFE),
  1670. is not accessible during DMA. Because of this, the routine
  1671. below must be copied & executed in high ram. It is usually
  1672. called from a V-blank Interrupt.
  1673.  
  1674. Example program:
  1675.  
  1676. org $40
  1677. jp VBlank
  1678.  
  1679. org $ff80
  1680. VBlank:
  1681. push af <- Save A reg & flags
  1682. ld a,BASE_ADRS <- transfer data from BASE_ADRS
  1683. ld ($ff46),a <- put A into DMA registers
  1684. ld a,28h <- loop length
  1685. Wait: <- We need to wait 160 microseconds.
  1686. dec a <- 4 cycles - decrease A by 1
  1687. jr nz,Wait <- 12 cycles - branch if Not Zero to Wait
  1688. pop af <- Restore A reg & flags
  1689. reti <- Return from interrupt
  1690.  
  1691.  
  1692. FF47
  1693. Name - BGP
  1694. Contents - BG & Window Palette Data (R/W)
  1695.  
  1696. Bit 7-6 - Data for Dot Data 11 (Normally darkest color)
  1697. Bit 5-4 - Data for Dot Data 10
  1698. Bit 3-2 - Data for Dot Data 01
  1699. Bit 1-0 - Data for Dot Data 00 (Normally lightest color)
  1700.  
  1701. This selects the shade of grays to use for
  1702. the background (BG) & window pixels. Since
  1703. each pixel uses 2 bits, the corresponding
  1704. shade will be selected from here.
  1705.  
  1706. FF48
  1707. Name - OBP0
  1708. Contents - Object Palette 0 Data (R/W)
  1709.  
  1710. This selects the colors for sprite palette 0.
  1711. It works exactly as BGP ($FF47) except each
  1712. each value of 0 is transparent.
  1713.  
  1714. FF49
  1715. Name - OBP1
  1716. Contents - Object Palette 1 Data (R/W)
  1717.  
  1718. This Selects the colors for sprite palette 1.
  1719. It works exactly as OBP0 ($FF48).
  1720. See BGP for details.
  1721.  
  1722. FF4A
  1723. Name - WY
  1724. Contents - Window Y Position (R/W)
  1725.  
  1726. 0 <= WY <= 143
  1727.  
  1728. WY must be greater than or equal to 0 and
  1729. must be less than or equal to 143 for
  1730. window to be visible.
  1731.  
  1732. FF4B
  1733. Name - WX
  1734. Contents - Window X Position (R/W)
  1735.  
  1736. 0 <= WX <= 166
  1737.  
  1738. WX must be greater than or equal to 0 and
  1739. must be less than or equal to 166 for
  1740. window to be visible.
  1741.  
  1742. WX is offset from absolute screen coordinates
  1743. by 7. Setting the window to WX=7, WY=0 will
  1744. put the upper left corner of the window at
  1745. absolute screen coordinates 0,0.
  1746.  
  1747.  
  1748. Lets say WY = 70 and WX = 87.
  1749. The window would be positioned as so:
  1750.  
  1751. 0 80 159
  1752. ______________________________________
  1753. 0 | |
  1754. | | |
  1755. | |
  1756. | Background Display |
  1757. | Here |
  1758. | |
  1759. | |
  1760. 70 | - +------------------|
  1761. | | 80,70 |
  1762. | | |
  1763. | | Window Display |
  1764. | | Here |
  1765. | | |
  1766. | | |
  1767. 143 |___________________|__________________|
  1768.  
  1769.  
  1770. OBJ Characters (Sprites) can still enter the
  1771. window. None of the window colors are
  1772. transparent so any background tiles under the
  1773. window are hidden.
  1774.  
  1775. FFFF
  1776. Name - IE
  1777. Contents - Interrupt Enable (R/W)
  1778.  
  1779. Bit 4: Transition from High to Low of Pin
  1780. number P10-P13.
  1781. Bit 3: Serial I/O transfer complete
  1782. Bit 2: Timer Overflow
  1783. Bit 1: LCDC (see STAT)
  1784. Bit 0: V-Blank
  1785.  
  1786. 0: disable
  1787. 1: enable
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