module RS232_TEST(
    input CLOCK_50, RESET, RX,
    output SAMPLE,
    output [7:0] LED
    );

    // Internal signals
    wire [7:0] data;
    wire data_ready;
    wire sample;
    reg data_read, data_read_next;
    reg [3:0] state, state_next;
    reg [7:0] led_data, led_data_next;

    // Define states
    localparam [3:0]
        Start = 0,
        Idle = 1,
        Read = 2,
        Wait = 3;

    // Define assignments
    assign SAMPLE = sample;
    assign LED = led_data;

    // Call instance of module
    RS232 receiver1 (.CLOCK_50(CLOCK_50), .RESET(RESET), .RX(RX), .DATA_OUT(data), .DATA_READ(data_read), .DATA_READY(data_ready), .SAMPLE(sample));

    // Sequential logic
    always @(posedge CLOCK_50)
    begin
        if(!RESET)
        begin
            data_read <= 0;
            led_data <= 0;
            state <= 0;
        end
        else
        begin
            data_read <= data_read_next;
            led_data <= led_data_next;
            state <= state_next;
        end
    end

    always @*
    begin
    data_read_next = data_read;
    led_data_next = led_data;
    state_next = state;

    case(state)
        Start:
        begin
            data_read_next = 0;
            led_data_next = 0;
            state_next = Idle;
        end

        Idle:
        begin
            data_read_next = 0;
            led_data_next = led_data;
            if(data_ready)
            begin
                state_next = Read;
            end
            else
            begin
                data_read_next = 0;
                state_next = Idle;
            end
        end

        Read:
        begin
            led_data_next = data;
            data_read_next = 1;
            state_next = Wait;
        end

        Wait:
        begin
            data_read_next = 1;
            if(data_ready)
            begin
                data_read_next = 1;
                state_next = Wait;
            end
            else
            begin
                data_read_next = 0;
                state_next = Idle;
            end
        end

    endcase
    end

endmodule