module pare (HEX1,HEX0,KEY, LEDR);
        input [1:0]KEY;
        output [17:0]LEDR;
        output [0:6]HEX1,HEX0;

        wire rollover,rollover1,rollover2;
        wire [3:0]jedinica, desetica;

        assign LEDR[17]=rollover1;
        counter  countevery151 (KEY[1],KEY[0],jedinica,rollover1);
        defparam countevery151.n = 4;
        defparam countevery151.k = 0;
        counter  countevery152 (rollover1,KEY[0],desetica,rollover2);
        defparam countevery152.n = 4;
        defparam countevery152.k = 0;

        b2d_ssd JED(jedinica,HEX0);
        b2d_ssd DES(desetica,HEX1);
endmodule

module counter (Clock, Reset_n, Q,rollover);
        parameter n = 8;
        parameter k = 20;
        input Clock, Reset_n;
        output reg[n-1:0] Q;
        output reg rollover;

        always @(posedge Clock or negedge Reset_n)
        begin

                if (!Reset_n)
                begin
                        Q <= 4'b1001;
                        rollover <=0;
                end

                else
                begin
                        Q <= Q - 4'b0001;
                        rollover <=0;
                        if (Q==k)
                                begin
                                Q<=4'b0000;
                                rollover<=1;
                                end
                end
        end

endmodule



module b2d_ssd (X, SSD);
  input [3:0] X;
  output reg [0:6] SSD;

  always begin
    case(X)
      0:SSD=7'b0000001;
      1:SSD=7'b1001111;
      2:SSD=7'b0010010;
      3:SSD=7'b0000110;
      4:SSD=7'b1001100;
      5:SSD=7'b0100100;
      6:SSD=7'b0100000;
      7:SSD=7'b0001111;
      8:SSD=7'b0000000;
      9:SSD=7'b0001100;
    endcase
  end
endmodule