#define CS_SRAM_PIN 15

extern volatile uint32_t PIN_OUT;
extern volatile uint32_t PIN_OUT_SET;
extern volatile uint32_t PIN_OUT_CLEAR;

extern volatile uint32_t PIN_DIR;
extern volatile uint32_t PIN_DIR_OUTPUT;
extern volatile uint32_t PIN_DIR_INPUT;

extern volatile uint32_t PIN_IN;

extern volatile uint32_t PIN_0;
extern volatile uint32_t PIN_2;

#define SPI          0
#define HSPI         1

// function added
void ICACHE_FLASH_ATTR spi_clock(uint8 spi_no, uint16 prediv, uint8 cntdiv){
   if(spi_no > 1) return;
   if((prediv==0)|(cntdiv==0)){
      WRITE_PERI_REG(SPI_CLOCK(spi_no), SPI_CLK_EQU_SYSCLK);
   } else {
      WRITE_PERI_REG(SPI_CLOCK(spi_no),
               (((prediv-1)&SPI_CLKDIV_PRE)<<SPI_CLKDIV_PRE_S)|
               (((cntdiv-1)&SPI_CLKCNT_N)<<SPI_CLKCNT_N_S)|
               (((cntdiv>>1)&SPI_CLKCNT_H)<<SPI_CLKCNT_H_S)|
               ((0&SPI_CLKCNT_L)<<SPI_CLKCNT_L_S));
   }
}

//Initialize the SPI port to talk to the chip.
void ICACHE_FLASH_ATTR spiRamInit() {
   char dummy[64];

   // gpio init
   WRITE_PERI_REG(PERIPHS_IO_MUX, 0x105|(clock_div_flag<<9)); //Set bit 9 if 80MHz sysclock required
   PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDI_U, 2); //GPIO12 is HSPI MISO pin (Master Data In)
   PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTCK_U, 2); //GPIO13 is HSPI MOSI pin (Master Data Out)
   PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTMS_U, 2); //GPIO14 is HSPI CLK pin (Clock)

   spi_clock(HSPI, 4, 1); //20MHz   - 80Mhz/4/1
   PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDO_U, FUNC_GPIO15);   // configure SPI CS (set manually)*/

   PIN_DIR_OUTPUT |= (1<<CS_SRAM_PIN);
   PIN_OUT_SET |= (1<<CS_SRAM_PIN);
   //Dummy read to clear any weird state the SPI ram chip may be in
   spiRamRead(0x0, dummy, 64);

}

//Read bytes from a memory location. The max amount of bytes that can be read is 64.
void spiRamRead(int addr, char *buff, int len) {
   int *p=(int*)buff;
   int d;
   int i=0;

   spi_clock(HSPI, 4, 2); //10MHz   - 80Mhz/4/2
   PIN_OUT_CLEAR |= (1<<CS_SRAM_PIN);   // select CS

   while(READ_PERI_REG(SPI_CMD(HSPI))&SPI_USR) ;

   CLEAR_PERI_REG_MASK(SPI_USER(HSPI), SPI_FLASH_MODE|SPI_USR_MOSI);
   SET_PERI_REG_MASK(SPI_USER(HSPI), SPI_CS_SETUP|SPI_CS_HOLD|SPI_USR_COMMAND|SPI_USR_ADDR|SPI_USR_MISO);

   WRITE_PERI_REG(SPI_USER1(HSPI), ((0&SPI_USR_MOSI_BITLEN)<<SPI_USR_MOSI_BITLEN_S)| //no data out
         ((((8*len)-1)&SPI_USR_MISO_BITLEN)<<SPI_USR_MISO_BITLEN_S)| //len bits of data in
         ((23&SPI_USR_ADDR_BITLEN)<<SPI_USR_ADDR_BITLEN_S)); //address is 24 bits A0-A23
   WRITE_PERI_REG(SPI_ADDR(HSPI), addr<<8); //write address
   WRITE_PERI_REG(SPI_USER2(HSPI), (((7&SPI_USR_COMMAND_BITLEN)<<SPI_USR_COMMAND_BITLEN_S) | 0x03));

   SET_PERI_REG_MASK(SPI_CMD(HSPI), SPI_USR);
   while(READ_PERI_REG(SPI_CMD(HSPI))&SPI_USR) ;
   //Unaligned dest address. Copy 8bit at a time
   while (len>0) {
      d=READ_PERI_REG(SPI_W(HSPI, i));
      buff[i*4+0]=(d>>0)&0xff;
      if (len>=1) buff[i*4+1]=(d>>8)&0xff;
      if (len>=2) buff[i*4+2]=(d>>16)&0xff;
      if (len>=3) buff[i*4+3]=(d>>24)&0xff;
      len-=4;
      i++;
   }
   PIN_OUT_SET |= (1<<CS_SRAM_PIN);   // deselect CS
}

//Write bytes to a memory location. The max amount of bytes that can be written is 64.
void spiRamWrite(int addr, char *buff, int len) {
   int i;
   int d;

   spi_clock(HSPI, 4, 2); //10MHz   - 80Mhz/4/1
   PIN_OUT_CLEAR |= (1<<CS_SRAM_PIN);   // select CS

   while(READ_PERI_REG(SPI_CMD(HSPI))&SPI_USR) ;

   CLEAR_PERI_REG_MASK(SPI_USER(HSPI), SPI_FLASH_MODE|SPI_USR_MISO);
   SET_PERI_REG_MASK(SPI_USER(HSPI), SPI_CS_SETUP|SPI_CS_HOLD|SPI_USR_COMMAND|SPI_USR_ADDR|SPI_USR_MOSI);

   WRITE_PERI_REG(SPI_USER1(HSPI), ((((8*len)-1)&SPI_USR_MOSI_BITLEN)<<SPI_USR_MOSI_BITLEN_S)| //len bitsbits of data out
         ((0&SPI_USR_MISO_BITLEN)<<SPI_USR_MISO_BITLEN_S)| //no data in
         ((23&SPI_USR_ADDR_BITLEN)<<SPI_USR_ADDR_BITLEN_S)); //address is 24 bits A0-A23
   WRITE_PERI_REG(SPI_ADDR(HSPI), addr<<8); //write address
   WRITE_PERI_REG(SPI_USER2(HSPI), (((7&SPI_USR_COMMAND_BITLEN)<<SPI_USR_COMMAND_BITLEN_S) | 0x02));

   //Assume unaligned src: Copy byte-wise.
   for (i=0; i<(len+3)/4; i++) {
      d=buff[i*4+0]<<0;
      d|=buff[i*4+1]<<8;
      d|=buff[i*4+2]<<16;
      d|=buff[i*4+3]<<24;
      WRITE_PERI_REG(SPI_W(HSPI, (i)), d);
   }
   SET_PERI_REG_MASK(SPI_CMD(HSPI), SPI_USR);

   PIN_OUT_SET |= (1<<CS_SRAM_PIN);   // deselect CS
} - See more at: http://www.esp8266.com/viewtopic.php?f=6&t=9577#sthash.6MTN0ujN.dpuf