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  1. From 8ed7614d02a6fa3845de56ec3a8e899c55b4a7f9 Mon Sep 17 00:00:00 2001
  2. From: Fabio Estevam <festevam@gmail.com>
  3. Date: Sun, 28 Aug 2016 23:39:52 -0300
  4. Subject: [PATCH] imx6ulevk: Remove spl support
  5.  
  6. Signed-off-by: Fabio Estevam <festevam@gmail.com>
  7. ---
  8. board/freescale/mx6ul_14x14_evk/imximage.cfg | 88 +++++++++++
  9. board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 172 ----------------------
  10. configs/mx6ul_14x14_evk_defconfig | 3 +-
  11. 3 files changed, 89 insertions(+), 174 deletions(-)
  12. create mode 100644 board/freescale/mx6ul_14x14_evk/imximage.cfg
  13.  
  14. diff --git a/board/freescale/mx6ul_14x14_evk/imximage.cfg b/board/freescale/mx6ul_14x14_evk/imximage.cfg
  15. new file mode 100644
  16. index 0000000..f413753
  17. --- /dev/null
  18. +++ b/board/freescale/mx6ul_14x14_evk/imximage.cfg
  19. @@ -0,0 +1,88 @@
  20. +/*
  21. + * Copyright (C) 2015 Freescale Semiconductor, Inc.
  22. + *
  23. + * SPDX-License-Identifier: GPL-2.0+
  24. + *
  25. + * Refer docs/README.imxmage for more details about how-to configure
  26. + * and create imximage boot image
  27. + *
  28. + * The syntax is taken as close as possible with the kwbimage
  29. + */
  30. +
  31. +#define __ASSEMBLY__
  32. +#include <config.h>
  33. +
  34. +/* image version */
  35. +
  36. +IMAGE_VERSION 2
  37. +
  38. +/*
  39. + * Boot Device : one of
  40. + * spi/sd/nand/onenand, qspi/nor
  41. + */
  42. +BOOT_FROM sd
  43. +
  44. +/* New DDR type MT41K256M16TW-107 */
  45. +
  46. +/* Enable all clocks */
  47. +DATA 4 0x020c4068 0xffffffff
  48. +DATA 4 0x020c406c 0xffffffff
  49. +DATA 4 0x020c4070 0xffffffff
  50. +DATA 4 0x020c4074 0xffffffff
  51. +DATA 4 0x020c4078 0xffffffff
  52. +DATA 4 0x020c407c 0xffffffff
  53. +DATA 4 0x020c4080 0xffffffff
  54. +
  55. +DATA 4 0x020E04B4 0x000C0000
  56. +DATA 4 0x020E04AC 0x00000000
  57. +DATA 4 0x020E027C 0x00000030
  58. +DATA 4 0x020E0250 0x00000030
  59. +DATA 4 0x020E024C 0x00000030
  60. +DATA 4 0x020E0490 0x00000030
  61. +DATA 4 0x020E0288 0x00000030
  62. +DATA 4 0x020E0270 0x00000000
  63. +DATA 4 0x020E0260 0x00000030
  64. +DATA 4 0x020E0264 0x00000030
  65. +DATA 4 0x020E04A0 0x00000030
  66. +DATA 4 0x020E0494 0x00020000
  67. +DATA 4 0x020E0280 0x00000030
  68. +DATA 4 0x020E0284 0x00000030
  69. +DATA 4 0x020E04B0 0x00020000
  70. +DATA 4 0x020E0498 0x00000030
  71. +DATA 4 0x020E04A4 0x00000030
  72. +DATA 4 0x020E0244 0x00000030
  73. +DATA 4 0x020E0248 0x00000030
  74. +DATA 4 0x021B001C 0x00008000
  75. +DATA 4 0x021B0800 0xA1390003
  76. +DATA 4 0x021B080C 0x00000000
  77. +DATA 4 0x021B083C 0x41570155
  78. +DATA 4 0x021B0848 0x4040474A
  79. +DATA 4 0x021B0850 0x40405550
  80. +DATA 4 0x021B081C 0x33333333
  81. +DATA 4 0x021B0820 0x33333333
  82. +DATA 4 0x021B082C 0xf3333333
  83. +DATA 4 0x021B0830 0xf3333333
  84. +DATA 4 0x021B08C0 0x00921012
  85. +DATA 4 0x021B08b8 0x00000800
  86. +DATA 4 0x021B0004 0x0002002D
  87. +DATA 4 0x021B0008 0x1B333030
  88. +DATA 4 0x021B000C 0x676B52F3
  89. +DATA 4 0x021B0010 0xB66D0B63
  90. +DATA 4 0x021B0014 0x01FF00DB
  91. +DATA 4 0x021B0018 0x00201740
  92. +DATA 4 0x021B001C 0x00008000
  93. +DATA 4 0x021B002C 0x000026D2
  94. +DATA 4 0x021B0030 0x006B1023
  95. +DATA 4 0x021B0040 0x0000004F
  96. +DATA 4 0x021B0000 0x84180000
  97. +DATA 4 0x021B0890 0x23400A38
  98. +DATA 4 0x021B001C 0x02008032
  99. +DATA 4 0x021B001C 0x00008033
  100. +DATA 4 0x021B001C 0x00048031
  101. +DATA 4 0x021B001C 0x15208030
  102. +DATA 4 0x021B001C 0x04008040
  103. +DATA 4 0x021B0020 0x00000800
  104. +DATA 4 0x021B0818 0x00000227
  105. +DATA 4 0x021B0004 0x0002552D
  106. +DATA 4 0x021B0404 0x00011006
  107. +DATA 4 0x021B001C 0x00000000
  108. diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
  109. index c213861..ba64886 100644
  110. --- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
  111. +++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
  112. @@ -694,175 +694,3 @@ int checkboard(void)
  113.  
  114. return 0;
  115. }
  116. -
  117. -#ifdef CONFIG_SPL_BUILD
  118. -#include <libfdt.h>
  119. -#include <spl.h>
  120. -#include <asm/arch/mx6-ddr.h>
  121. -
  122. -
  123. -static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
  124. - .grp_addds = 0x00000030,
  125. - .grp_ddrmode_ctl = 0x00020000,
  126. - .grp_b0ds = 0x00000030,
  127. - .grp_ctlds = 0x00000030,
  128. - .grp_b1ds = 0x00000030,
  129. - .grp_ddrpke = 0x00000000,
  130. - .grp_ddrmode = 0x00020000,
  131. -#ifdef CONFIG_TARGET_MX6UL_9X9_EVK
  132. - .grp_ddr_type = 0x00080000,
  133. -#else
  134. - .grp_ddr_type = 0x000c0000,
  135. -#endif
  136. -};
  137. -
  138. -#ifdef CONFIG_TARGET_MX6UL_9X9_EVK
  139. -static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
  140. - .dram_dqm0 = 0x00000030,
  141. - .dram_dqm1 = 0x00000030,
  142. - .dram_ras = 0x00000030,
  143. - .dram_cas = 0x00000030,
  144. - .dram_odt0 = 0x00000000,
  145. - .dram_odt1 = 0x00000000,
  146. - .dram_sdba2 = 0x00000000,
  147. - .dram_sdclk_0 = 0x00000030,
  148. - .dram_sdqs0 = 0x00003030,
  149. - .dram_sdqs1 = 0x00003030,
  150. - .dram_reset = 0x00000030,
  151. -};
  152. -
  153. -static struct mx6_mmdc_calibration mx6_mmcd_calib = {
  154. - .p0_mpwldectrl0 = 0x00000000,
  155. - .p0_mpdgctrl0 = 0x20000000,
  156. - .p0_mprddlctl = 0x4040484f,
  157. - .p0_mpwrdlctl = 0x40405247,
  158. - .mpzqlp2ctl = 0x1b4700c7,
  159. -};
  160. -
  161. -static struct mx6_lpddr2_cfg mem_ddr = {
  162. - .mem_speed = 800,
  163. - .density = 2,
  164. - .width = 16,
  165. - .banks = 4,
  166. - .rowaddr = 14,
  167. - .coladdr = 10,
  168. - .trcd_lp = 1500,
  169. - .trppb_lp = 1500,
  170. - .trpab_lp = 2000,
  171. - .trasmin = 4250,
  172. -};
  173. -
  174. -struct mx6_ddr_sysinfo ddr_sysinfo = {
  175. - .dsize = 0,
  176. - .cs_density = 18,
  177. - .ncs = 1,
  178. - .cs1_mirror = 0,
  179. - .walat = 0,
  180. - .ralat = 5,
  181. - .mif3_mode = 3,
  182. - .bi_on = 1,
  183. - .rtt_wr = 0, /* LPDDR2 does not need rtt_wr rtt_nom */
  184. - .rtt_nom = 0,
  185. - .sde_to_rst = 0, /* LPDDR2 does not need this field */
  186. - .rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
  187. - .ddr_type = DDR_TYPE_LPDDR2,
  188. -};
  189. -
  190. -#else
  191. -static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
  192. - .dram_dqm0 = 0x00000030,
  193. - .dram_dqm1 = 0x00000030,
  194. - .dram_ras = 0x00000030,
  195. - .dram_cas = 0x00000030,
  196. - .dram_odt0 = 0x00000030,
  197. - .dram_odt1 = 0x00000030,
  198. - .dram_sdba2 = 0x00000000,
  199. - .dram_sdclk_0 = 0x00000008,
  200. - .dram_sdqs0 = 0x00000038,
  201. - .dram_sdqs1 = 0x00000030,
  202. - .dram_reset = 0x00000030,
  203. -};
  204. -
  205. -static struct mx6_mmdc_calibration mx6_mmcd_calib = {
  206. - .p0_mpwldectrl0 = 0x00070007,
  207. - .p0_mpdgctrl0 = 0x41490145,
  208. - .p0_mprddlctl = 0x40404546,
  209. - .p0_mpwrdlctl = 0x4040524D,
  210. -};
  211. -
  212. -struct mx6_ddr_sysinfo ddr_sysinfo = {
  213. - .dsize = 0,
  214. - .cs_density = 20,
  215. - .ncs = 1,
  216. - .cs1_mirror = 0,
  217. - .rtt_wr = 2,
  218. - .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
  219. - .walat = 1, /* Write additional latency */
  220. - .ralat = 5, /* Read additional latency */
  221. - .mif3_mode = 3, /* Command prediction working mode */
  222. - .bi_on = 1, /* Bank interleaving enabled */
  223. - .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
  224. - .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
  225. - .ddr_type = DDR_TYPE_DDR3,
  226. -};
  227. -
  228. -static struct mx6_ddr3_cfg mem_ddr = {
  229. - .mem_speed = 800,
  230. - .density = 4,
  231. - .width = 16,
  232. - .banks = 8,
  233. - .rowaddr = 15,
  234. - .coladdr = 10,
  235. - .pagesz = 2,
  236. - .trcd = 1375,
  237. - .trcmin = 4875,
  238. - .trasmin = 3500,
  239. -};
  240. -#endif
  241. -
  242. -static void ccgr_init(void)
  243. -{
  244. - struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  245. -
  246. - writel(0xFFFFFFFF, &ccm->CCGR0);
  247. - writel(0xFFFFFFFF, &ccm->CCGR1);
  248. - writel(0xFFFFFFFF, &ccm->CCGR2);
  249. - writel(0xFFFFFFFF, &ccm->CCGR3);
  250. - writel(0xFFFFFFFF, &ccm->CCGR4);
  251. - writel(0xFFFFFFFF, &ccm->CCGR5);
  252. - writel(0xFFFFFFFF, &ccm->CCGR6);
  253. - writel(0xFFFFFFFF, &ccm->CCGR7);
  254. -}
  255. -
  256. -static void spl_dram_init(void)
  257. -{
  258. - mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
  259. - mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
  260. -}
  261. -
  262. -void board_init_f(ulong dummy)
  263. -{
  264. - /* setup AIPS and disable watchdog */
  265. - arch_cpu_init();
  266. -
  267. - ccgr_init();
  268. -
  269. - /* iomux and setup of i2c */
  270. - board_early_init_f();
  271. -
  272. - /* setup GP timer */
  273. - timer_init();
  274. -
  275. - /* UART clocks enabled and gd valid - init serial console */
  276. - preloader_console_init();
  277. -
  278. - /* DDR initialization */
  279. - spl_dram_init();
  280. -
  281. - /* Clear the BSS. */
  282. - memset(__bss_start, 0, __bss_end - __bss_start);
  283. -
  284. - /* load/boot image from boot device */
  285. - board_init_r(NULL, 0);
  286. -}
  287. -#endif
  288. diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig
  289. index c65bdbf..0df002d 100644
  290. --- a/configs/mx6ul_14x14_evk_defconfig
  291. +++ b/configs/mx6ul_14x14_evk_defconfig
  292. @@ -1,8 +1,7 @@
  293. CONFIG_ARM=y
  294. CONFIG_ARCH_MX6=y
  295. CONFIG_TARGET_MX6UL_14X14_EVK=y
  296. -CONFIG_SPL=y
  297. -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
  298. +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_evk/imximage.cfg"
  299. CONFIG_BOOTDELAY=3
  300. CONFIG_HUSH_PARSER=y
  301. CONFIG_CMD_BOOTZ=y
  302. --
  303. 1.9.1
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