library IEEE;
use IEEE.STD_LOGIC_1164.all;
USE ieee.numeric_std.ALL;

use work.my_package.all;

entity landmark_1 is
  generic
        (data_length :integer := 8;
        address_length:integer:=3 );
        port ( clk:in std_logic;
        index: in unsigned(address_length-1 downto 0);
        vin:in std_logic;
        rst:in std_logic;
        flag: in std_logic;
        din: in signed(data_length -1 downto 0);
        --dout: out big_matrix(0 to 3);
        done: out std_logic
        );
end landmark_1;

architecture TB_ARCHITECTURE of landmark_1 is


component ram IS
    generic
    (
        ADDRESS_WIDTH   : integer := 3;
        DATA_WIDTH  : integer := 8
    );
    port
    (
        clock           : IN  std_logic;
        data            : IN  signed(DATA_WIDTH - 1 DOWNTO 0);
        write_address           : IN  unsigned(ADDRESS_WIDTH - 1 DOWNTO 0);
        read_address            : IN  unsigned(ADDRESS_WIDTH - 1 DOWNTO 0);
        we          : IN  std_logic;
        q           : OUT signed(DATA_WIDTH - 1 DOWNTO 0)
    );
end component;

signal inp1,inp2: matrix1_t(0 to address_length);
signal out_temp: signed(data_length-1 downto 0);
signal out_temp_2: signed(data_length-1 downto 0);

--to_integer(unsigned(i))

begin
--i<=std_logic_vector(to_unsigned(k,address_length));
read1:ram generic map( ADDRESS_WIDTH=>address_length, DATA_WIDTH=>data_length) port map (clk,din,index,index,vin,out_temp);
inp1(to_integer(index))<=out_temp;

process (clk)
  begin
  if (clk'event and clk='1') then
    if (flag='1') then out_temp_2<=inp1(0)+inp1(1);
    end if;
  end if;
end process ;

end TB_ARCHITECTURE;