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-- Company:
-- Engineer:
--
-- Create Date:    14:52:37 11/30/2015
-- Design Name:
-- Module Name:    sek - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;



-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity sek is
    Port ( iCLK : in  STD_LOGIC;
           inRST : in  STD_LOGIC;
			  inSTART : in  STD_LOGIC;
			  inSTOP : in  STD_LOGIC;
			  inCONTINUE : in  STD_LOGIC;
			  oSEC : out  STD_LOGIC_VECTOR(7 downto 0);
           oTC : out  STD_LOGIC);
end sek;

architecture Behavioral of sek is
	signal sCNT : STD_LOGIC_VECTOR(7 downto 0);
	signal sCNT2 : STD_LOGIC_VECTOR(7 downto 0);

	signal sCNTREG1 : STD_LOGIC_VECTOR(7 downto 0);
	signal sCNTREG1_NEXT : STD_LOGIC_VECTOR(7 downto 0);

	signal sCNTREG2 : STD_LOGIC_VECTOR(7 downto 0);
	signal sCNTREG2_NEXT : STD_LOGIC_VECTOR(7 downto 0);

	signal sMUX : STD_LOGIC_VECTOR(7 downto 0);

	signal sCMP : STD_LOGIC;
	signal sCMP2 : STD_LOGIC;

	signal sSTATE : STD_LOGIC;
	signal sSTATE_NEXT : STD_LOGIC;

	signal sJOY : STD_LOGIC_VECTOR(3 downto 0);
	signal sENC : STD_LOGIC_VECTOR(1 downto 0);

	constant C_24_MHZ : STD_LOGIC_VECTOR(24 downto 0) := "1011011100011011000000000";
	constant C_100_HZ : STD_LOGIC_VECTOR(7 downto 0) := "00000110";
begin


process (iCLK) begin
	if (iCLK'event and iCLK = '1') then
		if (inRST = '0') then
			sCNTREG1 <= (others => '0');
		else
			sCNTREG1 <= sCNTREG1_NEXT;
		end if;
	end if;
end process;


process (iCLK) begin
	if (iCLK'event and iCLK = '1') then
		if (inRST = '0') then
			sCNTREG2 <= (others => '0');
		else
			sCNTREG2 <= sCNTREG2_NEXT;
		end if;
	end if;
end process;

process (iCLK) begin
	if (iCLK'event and iCLK = '1') then
		if (inRST = '0') then
			sSTATE <=  '0';
		else
			sSTATE <= sSTATE_NEXT;
		end if;
	end if;
end process;

sSTATE_NEXT <= '0' when inSTOP = '1' else '1';

-- comparator
sCMP <= '1' when sCNT = C_100_HZ else '0';

-- Inc
sCNT <= sCNTREG1 + 1;

-- mux
--sCNTREG1_NEXT <= sCNT when sCMP = '0' else (others => '0');
sMUX <= 				 sCNT when sCMP = '0' else (others => '0');


--sJOY <= inSTOP & inCONTINUE  & inSTART & '0';

-- prior encoder
--sENC <=
	--"11" when sJOY(3) = '1' else
	--"10" when sJOY(2) = '1' else
	--"01" when sJOY(1) = '1' else
	--"00";

sCNTREG1_NEXT <=
	(others => '0') when sSTATE = '0' and inSTART = '1' else -- resetuj veliki brojac na 0
	sCNTREG1 when inSTOP = '1' else
	--sMUX when inSTART = '1' or inCONTINUE = '1' else
	sMUX;
	--sCNTREG1 when sENC = "11" else
	--sMUX when sENC = "10" else
	--(others => '0') when sENC = "01" else
	--sMUX;


-- out 1
oTC <= sCMP;


-- Inc 2
sCNT2 <= sCNTREG2 + 1;

-- mux 2
sCNTREG2_NEXT <=
	(others => '0') when sSTATE = '0' and inSTART = '1' else
	sCNT2 when sCMP = '1' else
	sCNTREG2;


-- out 2
oSEC <= sCNTREG2;

end Behavioral;