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-- Company:
-- Engineer:
--
-- Create Date:    14:47:43 06/20/2010
-- Design Name:
-- Module Name:    UART_TX - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity UART_TX is
    Port ( CLK : in  STD_LOGIC;
           TX_PIN : out  STD_LOGIC;
           INPUT : in  integer range 0 to 255;
              PUSH : in STD_LOGIC);
end UART_TX;

architecture Behavioral of UART_TX is
    SIGNAL rts : STD_LOGIC := '1';
    SIGNAL bit_cnt : integer range 0 to 12;
    SIGNAL outbuf  : STD_LOGIC_VECTOR (8 downto 1);
begin
    PROCESS ( CLK, PUSH, RTS )
    BEGIN
        IF (rts='1') THEN
            IF RISING_EDGE(CLK) THEN
                CASE bit_cnt IS
                    WHEN 0 =>
                        TX_PIN <= '0'; --START BIT
                        bit_cnt <= bit_cnt + 1;
                    WHEN 9 =>
                        TX_PIN <= '1'; --STOP BIT
                        bit_cnt <= 0;
                        rts <= '0';
                    WHEN OTHERS =>
                        TX_PIN <= outbuf(bit_cnt);
                        bit_cnt <= bit_cnt + 1;
                END CASE;
            END IF;
        END IF;

        IF PUSH='1' THEN
            rts<='1';
        END IF;
    END PROCESS;

    outbuf <= conv_std_logic_vector(INPUT,8);
end Behavioral;