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skrock

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skrock
Mar 30th, 2013
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  1. --------------------------------------------------------------
  2. VERT
  3. DCL IN[0]
  4. DCL IN[1]
  5. DCL OUT[0], POSITION
  6. DCL OUT[1], GENERIC[0]
  7. 0: MOV OUT[0], IN[0]
  8. 1: MOV OUT[1], IN[1]
  9. 2: END
  10. --------------------------------------------------------------
  11. bytecode 26 dw -- 5 gprs ---------------------
  12. shader 0 -- C
  13. 0000 00000000 84C00000 CALL_FS @0
  14. 0002 00000005 A01C0000 ALU 8 @10
  15. 0010 00000001 00600C90 1 MOV R3.x, R1.x
  16. 0012 00000401 20600C90 MOV R3.y, R1.y
  17. 0014 00000801 40600C90 MOV R3.z, R1.z
  18. 0016 80000C01 60600C90 MOV R3.w, R1.w
  19. 0018 00000002 00800C90 2 MOV R4.x, R2.x
  20. 0020 00000402 20800C90 MOV R4.y, R2.y
  21. 0022 00000802 40800C90 MOV R4.z, R2.z
  22. 0024 80000C02 60800C90 MOV R4.w, R2.w
  23. 0004 C001A03C 95000688 EXPORT_DONE POS 60 R3.xyzw ES:3
  24. 0006 C0024000 95000688 EXPORT_DONE PARAM 0 R4.xyzw ES:3
  25. 0008 00000000 88000000 CF_END @0
  26. --------------------------------------
  27. ______________________________________________________________
  28. --------------------------------------------------------------
  29. VERT
  30. DCL IN[0]
  31. DCL OUT[0], POSITION
  32. 0: MOV OUT[0], IN[0]
  33. 1: END
  34. STREAMOUT
  35. 0: MEM_STREAM0_BUF0[0..0] <- OUT[0].x
  36. --------------------------------------------------------------
  37. bytecode 20 dw -- 3 gprs ---------------------
  38. shader 1 -- C
  39. 0000 00000000 84C00000 CALL_FS @0
  40. 0002 00000006 A00C0000 ALU 4 @12
  41. 0012 00000001 00400C90 1 MOV R2.x, R1.x
  42. 0014 00000401 20400C90 MOV R2.y, R1.y
  43. 0016 00000801 40400C90 MOV R2.z, R1.z
  44. 0018 80000C01 60400C90 MOV R2.w, R1.w
  45. 0004 40010000 90001FFF MEM_STREAM0_BUF0 WRITE 0 R2.x___ ES:1
  46. 0006 C001203C 95000688 EXPORT_DONE POS 60 R2.xyzw ES:3
  47. 0008 C0004000 95000FFF EXPORT_DONE PARAM 0 R0.____ ES:3
  48. 0010 00000000 88000000 CF_END @0
  49. --------------------------------------
  50. ______________________________________________________________
  51. --------------------------------------------------------------
  52. VERT
  53. DCL IN[0]
  54. DCL OUT[0], POSITION
  55. DCL OUT[1], GENERIC[19]
  56. DCL CONST[0]
  57. DCL TEMP[0..6], LOCAL
  58. IMM[0] FLT32 { 0.0000, 0.0000, 0.0000, 0.0000}
  59. IMM[1] UINT32 {0, 1, 0, 0}
  60. 0: MOV TEMP[0], IMM[0].xxxx
  61. 1: MOV TEMP[1].x, IN[0].xxxx
  62. 2: MOV TEMP[2].x, IMM[1].xxxx
  63. 3: MOV TEMP[3].x, IMM[1].yyyy
  64. 4: BGNLOOP :0
  65. 5: USEQ TEMP[4].x, TEMP[1].xxxx, IMM[1].xxxx
  66. 6: IF TEMP[4].xxxx :0
  67. 7: BRK
  68. 8: ENDIF
  69. 9: MOV TEMP[3].x, CONST[0].xxxx
  70. 10: MOV TEMP[5].x, IMM[1].xxxx
  71. 11: BGNLOOP :0
  72. 12: USGE TEMP[6].x, TEMP[5].xxxx, CONST[0].xxxx
  73. 13: IF TEMP[6].xxxx :0
  74. 14: BRK
  75. 15: ENDIF
  76. 16: UADD TEMP[2].x, TEMP[2].xxxx, IMM[1].yyyy
  77. 17: UADD TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
  78. 18: ENDLOOP :0
  79. 19: MOV TEMP[1].x, IMM[1].xxxx
  80. 20: ENDLOOP :0
  81. 21: MOV TEMP[1].z, TEMP[3].xxxx
  82. 22: MOV TEMP[1].y, TEMP[2].xxxx
  83. 23: MOV TEMP[1].x, IN[0].xxxx
  84. 24: MOV OUT[1], TEMP[1]
  85. 25: MOV OUT[0], TEMP[0]
  86. 26: END
  87. STREAMOUT
  88. 0: MEM_STREAM0_BUF0[0..0] <- OUT[1].x
  89. 1: MEM_STREAM0_BUF0[1..1] <- OUT[1].y
  90. 2: MEM_STREAM0_BUF0[2..2] <- OUT[1].z
  91. --------------------------------------------------------------
  92. bytecode 102 dw -- 13 gprs ---------------------
  93. shader 2 -- C
  94. 0000 00000000 84C00000 CALL_FS @0
  95. 0002 00000018 A0180000 ALU 7 @48
  96. 0048 000000F8 00800C90 1 MOV R4.x, 0
  97. 0050 000000F8 20800C90 MOV R4.y, 0
  98. 0052 000000F8 40800C90 MOV R4.z, 0
  99. 0054 800000F8 60800C90 MOV R4.w, 0
  100. 0056 80000001 00A00C90 2 MOV R5.x, R1.x
  101. 0058 800000F8 00C00C90 3 MOV R6.x, 0
  102. 0060 800004FA 00E00C90 4 MOV R7.x, 1
  103. 0004 00000011 81800000 LOOP_START_DX10 @34
  104. 0006 0000001F A4040000 ALU_PUSH_BEFORE 2 @62
  105. 0062 801F0005 01001D10 5 SETE_INT R8.x, R5.x, 0
  106. 0064 801F00FE 0180229C 6 MP PRED_SETNE_INT R12.x, PV.x, 0
  107. 0008 00000007 82800001 JUMP @14 POP:1
  108. 0010 00000010 82400000 LOOP_BREAK @32
  109. 0012 00000007 83800001 POP @14 POP:1
  110. 0014 40000021 A0040000 ALU 2 @66 KC0[CB0:0-16]
  111. 0066 80000080 00E00C90 7 MOV R7.x, KC0[0].x
  112. 0068 800000F8 01200C90 8 MOV R9.x, 0
  113. 0016 0000000F 81800000 LOOP_START_DX10 @30
  114. 0018 40000023 A4040000 ALU_PUSH_BEFORE 2 @70 KC0[CB0:0-16]
  115. 0070 80100009 01401F90 9 SETGE_UINT R10.x, R9.x, KC0[0].x
  116. 0072 801F00FE 0180229C 10 MP PRED_SETNE_INT R12.x, PV.x, 0
  117. 0020 0000000D 82800001 JUMP @26 POP:1
  118. 0022 0000000E 82400000 LOOP_BREAK @28
  119. 0024 0000000D 83800001 POP @26 POP:1
  120. 0026 00000025 A0040000 ALU 2 @74
  121. 0074 809F4006 00C01A10 11 ADD_INT R6.x, R6.x, 1
  122. 0076 809F4009 01201A10 12 ADD_INT R9.x, R9.x, 1
  123. 0028 00000009 81400000 LOOP_END @18
  124. 0030 00000027 A0000000 ALU 1 @78
  125. 0078 800000F8 00A00C90 13 MOV R5.x, 0
  126. 0032 00000003 81400000 LOOP_END @6
  127. 0034 00000028 A0280000 ALU 11 @80
  128. 0080 00000001 00B00C90 14 MOV R5.x, R1.x BS:4
  129. 0082 00000006 20A80C90 MOV R5.y, R6.x BS:2
  130. 0084 80000007 40A00C90 MOV R5.z, R7.x
  131. 0086 000000FE 00600C90 15 MOV R3.x, PV.x
  132. 0088 000004FE 20600C90 MOV R3.y, PV.y
  133. 0090 000008FE 40600C90 MOV R3.z, PV.z
  134. 0092 80000C05 60600C90 MOV R3.w, R5.w
  135. 0094 00000004 00400C90 16 MOV R2.x, R4.x
  136. 0096 00000404 20400C90 MOV R2.y, R4.y
  137. 0098 00000804 40400C90 MOV R2.z, R4.z
  138. 0100 80000C04 60400C90 MOV R2.w, R4.w
  139. 0036 40018000 90001FFF MEM_STREAM0_BUF0 WRITE 0 R3.x___ ES:1
  140. 0038 40018000 90002FFF MEM_STREAM0_BUF0 WRITE 0 R3._y__ ES:1
  141. 0040 40018000 90004FFF MEM_STREAM0_BUF0 WRITE 0 R3.__z_ ES:1
  142. 0042 C001203C 95000688 EXPORT_DONE POS 60 R2.xyzw ES:3
  143. 0044 C001C000 95000688 EXPORT_DONE PARAM 0 R3.xyzw ES:3
  144. 0046 00000000 88000000 CF_END @0
  145. --------------------------------------
  146. ______________________________________________________________
  147. input:
  148. shift_count 64
  149. starting_x 0
  150.  
  151. actual output:
  152. iteration_count 1
  153. shift_reg 1
  154.  
  155. expected output:
  156. iteration_count 0
  157. shift_reg 1
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