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Sep 16th, 2015
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  1. /*
  2.  * File:   main.c
  3.  * Author: LEO
  4.  *
  5.  * Created on 16 de septiembre de 2015, 16:46
  6.  */
  7.  
  8. #include <xc.h>
  9. #include <stdio.h>
  10. #include <stdlib.h>
  11. #include <timers.h>
  12.  
  13. // CONFIG1H
  14. #pragma config FOSC = INTIO67   // Oscillator Selection bits (Internal oscillator block, port function on RA6 and RA7)
  15. #pragma config FCMEN = OFF      // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
  16. #pragma config IESO = OFF       // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)
  17.  
  18. // CONFIG2L
  19. #pragma config PWRT = OFF       // Power-up Timer Enable bit (PWRT disabled)
  20. #pragma config BOREN = SBORDIS  // Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled))
  21. #pragma config BORV = 18        // Brown Out Reset Voltage bits (VBOR set to 1.8 V nominal)
  22.  
  23. // CONFIG2H
  24. #pragma config WDTEN = OFF      // Watchdog Timer Enable bit (WDT is controlled by SWDTEN bit of the WDTCON register)
  25. #pragma config WDTPS = 32768    // Watchdog Timer Postscale Select bits (1:32768)
  26.  
  27. // CONFIG3H
  28. #pragma config CCP2MX = PORTC   // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
  29. #pragma config PBADEN = OFF     // PORTB A/D Enable bit (PORTB<4:0> pins are configured as digital I/O on Reset)
  30. #pragma config LPT1OSC = OFF    // Low-Power Timer1 Oscillator Enable bit (Timer1 configured for higher power operation)
  31. #pragma config HFOFST = OFF     // HFINTOSC Fast Start-up (The system clock is held off until the HFINTOSC is stable.)
  32. #pragma config MCLRE = OFF      // MCLR Pin Enable bit (RE3 input pin enabled; MCLR disabled)
  33.  
  34. // CONFIG4L
  35. #pragma config STVREN = OFF     // Stack Full/Underflow Reset Enable bit (Stack full/underflow will not cause Reset)
  36. #pragma config LVP = ON         // Single-Supply ICSP Enable bit (Single-Supply ICSP enabled)
  37. #pragma config XINST = OFF      // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))
  38.  
  39. // CONFIG5L
  40. #pragma config CP0 = OFF        // Code Protection Block 0 (Block 0 (000800-001FFFh) not code-protected)
  41. #pragma config CP1 = OFF        // Code Protection Block 1 (Block 1 (002000-003FFFh) not code-protected)
  42. #pragma config CP2 = OFF        // Code Protection Block 2 (Block 2 (004000-005FFFh) not code-protected)
  43. #pragma config CP3 = OFF        // Code Protection Block 3 (Block 3 (006000-007FFFh) not code-protected)
  44.  
  45. // CONFIG5H
  46. #pragma config CPB = OFF        // Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected)
  47. #pragma config CPD = OFF        // Data EEPROM Code Protection bit (Data EEPROM not code-protected)
  48.  
  49. // CONFIG6L
  50. #pragma config WRT0 = OFF       // Write Protection Block 0 (Block 0 (000800-001FFFh) not write-protected)
  51. #pragma config WRT1 = OFF       // Write Protection Block 1 (Block 1 (002000-003FFFh) not write-protected)
  52. #pragma config WRT2 = OFF       // Write Protection Block 2 (Block 2 (004000-005FFFh) not write-protected)
  53. #pragma config WRT3 = OFF       // Write Protection Block 3 (Block 3 (006000-007FFFh) not write-protected)
  54.  
  55. // CONFIG6H
  56. #pragma config WRTC = OFF       // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected)
  57. #pragma config WRTB = OFF       // Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected)
  58. #pragma config WRTD = OFF       // Data EEPROM Write Protection bit (Data EEPROM not write-protected)
  59.  
  60. // CONFIG7L
  61. #pragma config EBTR0 = OFF      // Table Read Protection Block 0 (Block 0 (000800-001FFFh) not protected from table reads executed in other blocks)
  62. #pragma config EBTR1 = OFF      // Table Read Protection Block 1 (Block 1 (002000-003FFFh) not protected from table reads executed in other blocks)
  63. #pragma config EBTR2 = OFF      // Table Read Protection Block 2 (Block 2 (004000-005FFFh) not protected from table reads executed in other blocks)
  64. #pragma config EBTR3 = OFF      // Table Read Protection Block 3 (Block 3 (006000-007FFFh) not protected from table reads executed in other blocks)
  65.  
  66. // CONFIG7H
  67. #pragma config EBTRB = OFF      // Boot Block Table Read Protection bit (Boot Block (000000-0007FFh) not protected from table reads executed in other blocks)
  68.  
  69. #define led1red         LATAbits.LATA4
  70. #define led1green       LATAbits.LATA5
  71. #define led1blue        LATEbits.LATE0
  72.  
  73. #define led2red         LATEbits.LATE1
  74. #define led2green       LATEbits.LATE2
  75. #define led2blue        LATAbits.LATA7
  76.  
  77. #define led3red         LATAbits.LATA6
  78. #define led3green       LATCbits.LATC0
  79. #define led3blue        LATCbits.LATC1
  80.  
  81. #define led4red         LATCbits.LATC2
  82. #define led4green       LATCbits.LATC3
  83. #define led4blue        LATDbits.LATD0
  84.  
  85. #define led5red         LATDbits.LATD1
  86. #define led5green       LATDbits.LATD2
  87. #define led5blue        LATDbits.LATD3
  88.  
  89. #define led6red         LATCbits.LATC4
  90. #define led6green       LATCbits.LATC6
  91. #define led6blue        LATDbits.LATD4
  92.  
  93. #define led7red         LATDbits.LATD5
  94. #define led7green       LATDbits.LATD6
  95. #define led7blue        LATDbits.LATD7
  96.  
  97. #define led8red         LATBbits.LATB0
  98. #define led8green       LATBbits.LATB1
  99. #define led8blue        LATBbits.LATB2
  100.  
  101. #define led9red         LATBbits.LATB3
  102. #define led9green       LATBbits.LATB4
  103. #define led9blue        LATBbits.LATB5
  104.  
  105.  
  106. //demas pines utilizados
  107. #define MCLR            PORTEbits.RE3
  108. #define PGC             LATBbits.LATB6
  109. #define PGD             LATBbits.LATB7
  110. #define ANALOG0         PORTAbits.RA0
  111. #define ANALOG1         PORTAbits.RA1
  112. #define ANALOG2         PORTAbits.RA2
  113. #define ANALOG3         PORTAbits.RA3
  114.  
  115. #define     duty1red    dutys[0]
  116. #define     duty1green  dutys[1]
  117. #define     duty1blue   dutys[2]
  118. #define     duty2red    dutys[3]
  119. #define     duty2green  dutys[4]
  120. #define     duty2blue   dutys[5]
  121. #define     duty3red    dutys[6]
  122. #define     duty3green  dutys[7]
  123. #define     duty3blue   dutys[8]
  124. #define     duty4red    dutys[9]
  125. #define     duty4green  dutys[10]
  126. #define     duty4blue   dutys[11]
  127. #define     duty5red    dutys[12]
  128. #define     duty5green  dutys[13]
  129. #define     duty5blue   dutys[14]    
  130. #define     duty6red    dutys[15]
  131. #define     duty6green  dutys[16]    
  132. #define     duty6blue   dutys[17]
  133. #define     duty7red    dutys[18]
  134. #define     duty7green  dutys[19]      
  135. #define     duty7blue   dutys[20]
  136. #define     duty8red    dutys[21]
  137. #define     duty8green  dutys[22]
  138. #define     duty8blue   dutys[23]
  139. #define     duty9red    dutys[24]
  140. #define     duty9green  dutys[25]
  141. #define     duty9blue   dutys[26]
  142.  
  143. unsigned char dutys[27] = { 245,100,100,
  144.                             10,10,10,
  145.                             10,10,10,
  146.                             10,10,10,
  147.                             10,10,10,
  148.                             10,150,10,
  149.                             10,10,10,
  150.                             10,10,10,
  151.                             100,100,100
  152. };
  153. unsigned char anchodepulso=0;
  154.  
  155. void interrupt YourHighPriorityISRCode(){
  156.     if(INTCONbits.TMR0IF){
  157.         anchodepulso++;
  158.  
  159.         if(anchodepulso<=duty1red){
  160.             led1red=1;
  161.         }else led1red=0;
  162.  
  163.         if(anchodepulso<=duty1green){
  164.             led1green=1;
  165.         }else led1green=0;
  166.          if(anchodepulso<=duty1blue){
  167.             led1blue=1;
  168.         }else led1blue=0;  
  169.        
  170.         if(anchodepulso<=duty2red){
  171.             led2red=1;
  172.         }else led2red=0;
  173.         if(anchodepulso<=duty2green){
  174.             led2green=1;
  175.         }else led2green=0;
  176.         if(anchodepulso<=duty2blue){
  177.             led2blue=1;
  178.         }else led2blue=0;
  179.        
  180.         if(anchodepulso<=duty3red){
  181.             led3red=1;
  182.         }else led3red=0;
  183.         if(anchodepulso<=duty3green){
  184.             led3green=1;
  185.         }else led3green=0;
  186.         if(anchodepulso<=duty3blue){
  187.             led3blue=1;
  188.         }else led3blue=0;
  189.        
  190.         if(anchodepulso<=duty4red){
  191.             led4red=1;
  192.         }else led4red=0;
  193.         if(anchodepulso<=duty4green){
  194.             led4green=1;
  195.         }else led4green=0;
  196.         if(anchodepulso<=duty4blue){
  197.             led4blue=1;
  198.         }else led4blue=0;
  199.        
  200.         if(anchodepulso<=duty5red){
  201.             led5red=1;
  202.         }else led5red=0;
  203.         if(anchodepulso<=duty5green){
  204.             led5green=1;
  205.         }else led5green=0;
  206.         if(anchodepulso<=duty5blue){
  207.             led5blue=1;
  208.         }else led5blue=0;
  209.        
  210.         if(anchodepulso<=duty6red){
  211.             led6red=1;
  212.         }else led6red=0;
  213.         if(anchodepulso<=duty6green){
  214.             led6green=1;
  215.         }else led6green=0;
  216.         if(anchodepulso<=duty6blue){
  217.             led6blue=1;
  218.         }else led6blue=0;
  219.        
  220.         if(anchodepulso<=duty7red){
  221.             led7red=1;
  222.         }else led7red=0;
  223.         if(anchodepulso<=duty7green){
  224.             led7green=1;
  225.         }else led7green=0;
  226.         if(anchodepulso<=duty7blue){
  227.             led7blue=1;
  228.         }else led7blue=0;
  229.        
  230.         if(anchodepulso<=duty8red){
  231.             led8red=1;
  232.         }else led8red=0;
  233.         if(anchodepulso<=duty8green){
  234.             led8green=1;
  235.         }else led8green=0;
  236.         if(anchodepulso<=duty8blue){
  237.             led8blue=1;
  238.         }else led8blue=0;
  239.        
  240.         if(anchodepulso<=duty9red){
  241.             led9red=1;
  242.         }else led9red=0;
  243.         if(anchodepulso<=duty9green){
  244.             led9green=1;
  245.         }else led9green=0;
  246.         if(anchodepulso<=duty9blue){
  247.             led9blue=1;
  248.         }else led9blue=0;
  249.         if(anchodepulso==255){
  250.             anchodepulso==0;
  251.         }
  252.         WriteTimer0(255);
  253.         INTCONbits.TMR0IF=0;
  254.         //TMR0H = 0;
  255.         //TMR0L= 255;
  256.     }    
  257.     INTCONbits.GIEH = 1; //IMPORTANTE HABILITARLAS PORQ SE DESHABILITAN CON INTERRUP
  258. }
  259.  
  260. void interrupt low_priority YourLowPriorityISRCode(){
  261.  
  262.     INTCONbits.GIEL = 1;//IMPORTANTE HABILITARLAS PORQ SE DESHABILITAN CON INTERRUP
  263. }
  264.  
  265.  
  266. int main(int argc, char** argv) {
  267.     OSCCONbits.IDLEN=0;
  268.     OSCCONbits.IRCF =0b111; //oscilador interno de 16Mhz
  269.     while(OSCCONbits.OSTS); // sino esta corriendo con oscilador interno quedarse aca
  270.     while(!OSCCONbits.IOFS); // espera que frecuencia del clok sea estable
  271.     OSCCONbits.SCS = 0b11; // clock del sistema sea interno
  272.     OSCTUNEbits.INTSRC=1;
  273.     OSCTUNEbits.PLLEN= 1; //habilito PLL osea que en 16Mhz con PLL DE 4 --> Fosc= 64MHz
  274.     OSCTUNEbits.TUN= 0; //oscilador funcione calibrado de fabrica
  275.    
  276.     INTCONbits.TMR0IE=0;
  277.     INTCONbits.INT0IE = 0;
  278.     INTCONbits.RBIE = 0;
  279.     INTCONbits.PEIE_GIEL=1;
  280.     INTCONbits.GIE_GIEH=1;
  281.    
  282.     INTCON2bits.RBPU=0;
  283.     INTCON2bits.TMR0IP=0;
  284.     INTCON2bits.RBIP=0;
  285.    
  286.     INTCON3bits.INT2E=0;
  287.     INTCON3bits.INT1E=0;
  288.     INTCON3bits.INT1IP=0;
  289.     INTCON3bits.INT2IP=0;
  290.    
  291.     PIE1bits.ADIE=0;
  292.     PIE1bits.PSPIE=0;
  293.     PIE1bits.RCIE=0; //INT DEL EUSART
  294.     PIE1bits.TXIE=0; //INT DEL EUSART
  295.     PIE1bits.CCP1IE=0;
  296.     PIE1bits.TMR1IE=0;
  297.     PIE1bits.TMR2IE=0;
  298.    
  299.     PIE2bits.BCLIE=0;
  300.     PIE2bits.C1IE=0;
  301.     PIE2bits.C2IE=0;
  302.     PIE2bits.EEIE=0;
  303.     PIE2bits.HLVDIE=0;
  304.     PIE2bits.TMR3IE=0;
  305.     PIE2bits.CCP2IE=0;
  306.    
  307.     TRISB = 0b00000000; // 6 PWM DOS OCUPADOS POR PROGRAMACION RB6 Y RB7
  308.     TRISC = 0b10000000; // 6 PWM DOS OCUPADOS POR USART RC6 Y RC7
  309.     TRISD = 0b00000000; // 8 PWM
  310.     TRISE = 0b1000;     // 3 PWM  RE3 ES MCLR
  311.     TRISA = 0b00000011; // 4 PWM , SOBRAN 4 ADC RA0  RA1 RA2 Y RA3
  312.  
  313.     T0CONbits.T08BIT = 1;
  314.     T0CONbits.T0CS=0;
  315.     T0CONbits.PSA= 1; // SIN PRESCALER OSEA PRESCALER =1
  316.     TMR0L= 244; // desborda cada 75uS , cuando llega a 100 veces cumple un periodo de 13,333 KHz
  317.     INTCONbits.TMR0IE=1;
  318.    
  319.     while(1){
  320.        
  321.     }
  322.  
  323.     return EXIT_SUCCESS;
  324. }
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