From 5072db08867a7240fb33c9d9d99b3d8119ff62ec Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@nxp.com>
Date: Mon, 29 Aug 2016 16:40:28 -0300
Subject: [PATCH 2/2] mx6ul_14x14_evk: Pass refsel and refr fields to avoid hang

When running a NXP 4.1 kernel with U-Boot mainline on a mx6ul-evk,
we observe a hang when going into the lowest operational point of cpufreq.

After comparing the SPL DDR initialization against the DCD table
from NXP U-Boot, the key difference that causes the hang is the
MDREF register setting.

In the DDR3 MX6UL boards we have the following configuration
for MDREF in NXP U-Boot:

DATA 4 0x021B0020 0x00000800

,which means:

REF_SEL = 0 -->Periodic refresh cycle: 64kHz
REFR = 1 ---> Refresh Rate - 2 refreshes

So adjust the MDREF initialization for mx6ul_evk accordingly
to fix the kernel hang issue at low bus frequency.

Reported-by: Eric Nelson <eric@nelint.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
---
 board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
index c213861..111aadc 100644
--- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
+++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
@@ -804,6 +804,8 @@ struct mx6_ddr_sysinfo ddr_sysinfo = {
 	.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
 	.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
 	.ddr_type = DDR_TYPE_DDR3,
+	.refsel = 0,		/* Refresh cycles at 64KHz */
+	.refr = 1,		/* 2 refresh commands per refresh cycle */
 };

 static struct mx6_ddr3_cfg mem_ddr = {
--
1.9.1