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- --------------------------------------------------------------------------------
- Release 14.7 Trace (lin64)
- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
- /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/trce -intstyle ise -v 3 -s 2 -n
- 3 -fastpaths -xml orpsoc_top.twx orpsoc_top.ncd -o orpsoc_top.twr
- orpsoc_top.pcf
- Design file: orpsoc_top.ncd
- Physical constraint file: orpsoc_top.pcf
- Device,package,speed: xc7a100t,csg324,C,-2 (PRODUCTION 1.10 2013-10-13)
- Report level: verbose report
- Environment Variable Effect
- -------------------- ------
- NONE No environment variables were set
- --------------------------------------------------------------------------------
- INFO:Timing:2698 - No timing constraints found, doing default enumeration.
- INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
- INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
- option. All paths that are not constrained will be reported in the
- unconstrained paths section(s) of the report.
- INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
- a 50 Ohm transmission line loading model. For the details of this model,
- and for more information on accounting for different loading conditions,
- please see the device datasheet.
- Data Sheet report:
- -----------------
- All values displayed in nanoseconds (ns)
- Setup/Hold to clock sys_clk_pad_i
- -------------------+------------+------------+------------+------------+------------------+--------+
- |Max Setup to| Process |Max Hold to | Process | | Clock |
- Source | clk (edge) | Corner | clk (edge) | Corner |Internal Clock(s) | Phase |
- -------------------+------------+------------+------------+------------+------------------+--------+
- cellram_data_io<0> | 5.096(R)| SLOW | -1.918(R)| FAST |wb_clk | 0.000|
- cellram_data_io<1> | 5.515(R)| SLOW | -2.217(R)| FAST |wb_clk | 0.000|
- cellram_data_io<2> | 5.705(R)| SLOW | -2.079(R)| FAST |wb_clk | 0.000|
- cellram_data_io<3> | 5.068(R)| SLOW | -1.788(R)| FAST |wb_clk | 0.000|
- cellram_data_io<4> | 6.257(R)| SLOW | -1.875(R)| FAST |wb_clk | 0.000|
- cellram_data_io<5> | 5.225(R)| SLOW | -1.875(R)| FAST |wb_clk | 0.000|
- cellram_data_io<6> | 5.421(R)| SLOW | -1.803(R)| FAST |wb_clk | 0.000|
- cellram_data_io<7> | 5.258(R)| SLOW | -1.832(R)| FAST |wb_clk | 0.000|
- cellram_data_io<8> | 5.431(R)| SLOW | -1.926(R)| FAST |wb_clk | 0.000|
- cellram_data_io<9> | 5.962(R)| SLOW | -2.051(R)| FAST |wb_clk | 0.000|
- cellram_data_io<10>| 5.492(R)| SLOW | -1.994(R)| FAST |wb_clk | 0.000|
- cellram_data_io<11>| 5.219(R)| SLOW | -1.753(R)| FAST |wb_clk | 0.000|
- cellram_data_io<12>| 5.445(R)| SLOW | -1.900(R)| FAST |wb_clk | 0.000|
- cellram_data_io<13>| 4.810(R)| SLOW | -1.950(R)| FAST |wb_clk | 0.000|
- cellram_data_io<14>| 5.318(R)| SLOW | -1.670(R)| FAST |wb_clk | 0.000|
- cellram_data_io<15>| 5.572(R)| SLOW | -1.738(R)| FAST |wb_clk | 0.000|
- gpio0_io<0> | 4.224(R)| SLOW | -1.927(R)| FAST |wb_clk | 0.000|
- gpio0_io<1> | 4.249(R)| SLOW | -1.941(R)| FAST |wb_clk | 0.000|
- gpio0_io<2> | 3.937(R)| SLOW | -1.824(R)| FAST |wb_clk | 0.000|
- gpio0_io<3> | 4.166(R)| SLOW | -1.915(R)| FAST |wb_clk | 0.000|
- gpio0_io<4> | 5.077(R)| SLOW | -2.041(R)| FAST |wb_clk | 0.000|
- gpio0_io<5> | 4.432(R)| SLOW | -1.979(R)| FAST |wb_clk | 0.000|
- gpio0_io<6> | 4.186(R)| SLOW | -1.921(R)| FAST |wb_clk | 0.000|
- gpio0_io<7> | 4.525(R)| SLOW | -2.064(R)| FAST |wb_clk | 0.000|
- rst_n_pad_i | 5.464(R)| SLOW | -2.243(R)| FAST |wb_clk | 0.000|
- uart0_srx_pad_i | 3.903(R)| SLOW | -1.776(R)| FAST |wb_clk | 0.000|
- -------------------+------------+------------+------------+------------+------------------+--------+
- Clock sys_clk_pad_i to Pad
- -------------------+-----------------+------------+-----------------+------------+------------------+--------+
- |Max (slowest) clk| Process |Min (fastest) clk| Process | | Clock |
- Destination | (edge) to PAD | Corner | (edge) to PAD | Corner |Internal Clock(s) | Phase |
- -------------------+-----------------+------------+-----------------+------------+------------------+--------+
- cellram_adr_o<0> | 5.979(R)| SLOW | 1.913(R)| FAST |wb_clk | 0.000|
- cellram_adr_o<1> | 6.381(R)| SLOW | 2.164(R)| FAST |wb_clk | 0.000|
- cellram_adr_o<2> | 5.992(R)| SLOW | 1.956(R)| FAST |wb_clk | 0.000|
- cellram_adr_o<3> | 6.047(R)| SLOW | 1.985(R)| FAST |wb_clk | 0.000|
- cellram_adr_o<4> | 6.510(R)| SLOW | 2.224(R)| FAST |wb_clk | 0.000|
- cellram_adr_o<5> | 5.881(R)| SLOW | 1.944(R)| FAST |wb_clk | 0.000|
- cellram_adr_o<6> | 6.310(R)| SLOW | 2.117(R)| FAST |wb_clk | 0.000|
- cellram_adr_o<7> | 5.402(R)| SLOW | 1.645(R)| FAST |wb_clk | 0.000|
- cellram_adr_o<8> | 5.819(R)| SLOW | 1.945(R)| FAST |wb_clk | 0.000|
- cellram_adr_o<9> | 5.809(R)| SLOW | 1.880(R)| FAST |wb_clk | 0.000|
- cellram_adr_o<10> | 5.830(R)| SLOW | 1.958(R)| FAST |wb_clk | 0.000|
- cellram_adr_o<11> | 5.782(R)| SLOW | 1.857(R)| FAST |wb_clk | 0.000|
- cellram_adr_o<12> | 5.616(R)| SLOW | 1.748(R)| FAST |wb_clk | 0.000|
- cellram_adr_o<13> | 5.499(R)| SLOW | 1.747(R)| FAST |wb_clk | 0.000|
- cellram_adr_o<14> | 5.363(R)| SLOW | 1.676(R)| FAST |wb_clk | 0.000|
- cellram_adr_o<15> | 5.514(R)| SLOW | 1.716(R)| FAST |wb_clk | 0.000|
- cellram_adr_o<16> | 5.244(R)| SLOW | 1.591(R)| FAST |wb_clk | 0.000|
- cellram_adr_o<17> | 5.506(R)| SLOW | 1.724(R)| FAST |wb_clk | 0.000|
- cellram_adr_o<18> | 6.003(R)| SLOW | 1.985(R)| FAST |wb_clk | 0.000|
- cellram_adr_o<19> | 6.110(R)| SLOW | 1.970(R)| FAST |wb_clk | 0.000|
- cellram_adr_o<20> | 6.065(R)| SLOW | 1.991(R)| FAST |wb_clk | 0.000|
- cellram_adr_o<21> | 5.369(R)| SLOW | 1.633(R)| FAST |wb_clk | 0.000|
- cellram_adr_o<22> | 6.376(R)| SLOW | 2.177(R)| FAST |wb_clk | 0.000|
- cellram_adv_n_o | 5.511(R)| SLOW | 1.714(R)| FAST |wb_clk | 0.000|
- cellram_ce_n_o | 5.498(R)| SLOW | 1.732(R)| FAST |wb_clk | 0.000|
- cellram_cre_o | 5.498(R)| SLOW | 1.674(R)| FAST |wb_clk | 0.000|
- cellram_data_io<0> | 10.006(R)| SLOW | 1.755(R)| FAST |wb_clk | 0.000|
- cellram_data_io<1> | 10.103(R)| SLOW | 1.776(R)| FAST |wb_clk | 0.000|
- cellram_data_io<2> | 10.238(R)| SLOW | 1.733(R)| FAST |wb_clk | 0.000|
- cellram_data_io<3> | 9.882(R)| SLOW | 1.690(R)| FAST |wb_clk | 0.000|
- cellram_data_io<4> | 9.855(R)| SLOW | 1.699(R)| FAST |wb_clk | 0.000|
- cellram_data_io<5> | 9.291(R)| SLOW | 1.511(R)| FAST |wb_clk | 0.000|
- cellram_data_io<6> | 9.512(R)| SLOW | 1.667(R)| FAST |wb_clk | 0.000|
- cellram_data_io<7> | 9.631(R)| SLOW | 1.606(R)| FAST |wb_clk | 0.000|
- cellram_data_io<8> | 10.813(R)| SLOW | 1.860(R)| FAST |wb_clk | 0.000|
- cellram_data_io<9> | 10.958(R)| SLOW | 1.861(R)| FAST |wb_clk | 0.000|
- cellram_data_io<10>| 11.212(R)| SLOW | 1.843(R)| FAST |wb_clk | 0.000|
- cellram_data_io<11>| 10.102(R)| SLOW | 1.721(R)| FAST |wb_clk | 0.000|
- cellram_data_io<12>| 8.896(R)| SLOW | 1.562(R)| FAST |wb_clk | 0.000|
- cellram_data_io<13>| 9.136(R)| SLOW | 1.633(R)| FAST |wb_clk | 0.000|
- cellram_data_io<14>| 9.252(R)| SLOW | 1.579(R)| FAST |wb_clk | 0.000|
- cellram_data_io<15>| 9.169(R)| SLOW | 1.565(R)| FAST |wb_clk | 0.000|
- cellram_lb_n_o | 5.868(R)| SLOW | 1.888(R)| FAST |wb_clk | 0.000|
- cellram_oe_n_o | 6.267(R)| SLOW | 2.116(R)| FAST |wb_clk | 0.000|
- cellram_ub_n_o | 6.029(R)| SLOW | 1.991(R)| FAST |wb_clk | 0.000|
- cellram_we_n_o | 5.571(R)| SLOW | 1.747(R)| FAST |wb_clk | 0.000|
- gpio0_io<0> | 5.752(R)| SLOW | 1.792(R)| FAST |wb_clk | 0.000|
- gpio0_io<1> | 5.753(R)| SLOW | 1.732(R)| FAST |wb_clk | 0.000|
- gpio0_io<2> | 5.753(R)| SLOW | 1.711(R)| FAST |wb_clk | 0.000|
- gpio0_io<3> | 5.650(R)| SLOW | 1.612(R)| FAST |wb_clk | 0.000|
- gpio0_io<4> | 6.455(R)| SLOW | 2.084(R)| FAST |wb_clk | 0.000|
- gpio0_io<5> | 6.506(R)| SLOW | 1.918(R)| FAST |wb_clk | 0.000|
- gpio0_io<6> | 5.823(R)| SLOW | 1.823(R)| FAST |wb_clk | 0.000|
- gpio0_io<7> | 5.897(R)| SLOW | 1.734(R)| FAST |wb_clk | 0.000|
- uart0_stx_pad_o | 7.950(R)| SLOW | 2.729(R)| FAST |wb_clk | 0.000|
- -------------------+-----------------+------------+-----------------+------------+------------------+--------+
- Clock to Setup on destination clock sys_clk_pad_i
- ---------------+---------+---------+---------+---------+
- | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
- Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
- ---------------+---------+---------+---------+---------+
- sys_clk_pad_i | 13.480| | | |
- ---------------+---------+---------+---------+---------+
- Analysis completed Tue Apr 15 10:52:25 2014
- --------------------------------------------------------------------------------
- Trace Settings:
- -------------------------
- Trace Settings
- Peak Memory Usage: 865 MB
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