----------------------------------------------------------------------------------
-- Company: Ladecadence.net
-- Engineer: David Pello
--
-- Create Date:     11:35:28 11/27/2010
-- Design Name:     MBC5 GameBoy Mapper Clone
-- Module Name:     MBC5VHDL - Behavioral
-- Project Name:
-- Target Devices:  xc9536
-- Tool versions:   ISE 12.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- This code is licensed under the terms of the GNU General Public License (GPL)
-- version 2 or above; see http://www.fsf.org/licensing/licenses/gpl.html
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity MBC5VHDL is
    port(       not_reset   :   in      std_logic;
            not_cs      :   in      std_logic;
            not_wr      :   in      std_logic;
            data        :   in      std_logic_vector(7 downto 0);
            addr        :   in      std_logic_vector(15 downto 12);
            rom_addr    :   out     std_logic_vector(22 downto 14);
            ram_addr    :   out     std_logic_vector(16 downto 13);
            not_ram_cs  :   out     std_logic );
end MBC5VHDL;

architecture Behavioral of MBC5VHDL is
    signal ram_e_code:      std_logic;
    signal ram_e_regsel:        std_logic;
    signal romh_regsel:     std_logic;
    signal roml_regsel:     std_logic;
    signal ram_regsel:      std_logic;
    signal ram_e_regsync:       std_logic;
    signal roml_regsync:        std_logic;
    signal romh_regsync:        std_logic;
    signal ram_regsync:     std_logic;

    signal ram_e_q0:        std_logic := '0';

    signal ramq0:           std_logic := '0';
    signal ramq1:           std_logic := '0';
    signal ramq2:           std_logic := '0';
    signal ramq3:           std_logic := '0';
    signal romlq0:          std_logic := '0';
    signal romlq1:          std_logic := '0';
    signal romlq2:          std_logic := '0';
    signal romlq3:          std_logic := '0';
    signal romlq4:          std_logic := '0';
    signal romlq5:          std_logic := '0';
    signal romlq6:          std_logic := '0';
    signal romlq7:          std_logic := '0';

    signal romhq0:          std_logic := '0';

    signal bank0map:        std_logic;

begin
        -- RAM enable   (0000h - 1FFFh)
        ram_e_code <= data(3) and (not data(2)) and data(1) and (not data(0));
        ram_e_regsel <= (not addr(13)) and (not addr(14));
        ram_e_regsync <= ram_e_regsel and not_cs and (not not_wr);

        -- ROM high     (3000h-3FFFh)
        romh_regsel <= addr(12) and addr(13) and (not addr(14));
        romh_regsync <= romh_regsel and not_cs and (not not_wr);

        -- ROM low      (2000h-2FFFh)
        roml_regsel <=  (not addr(12)) and addr(13) and (not addr(14));
        roml_regsync <= roml_regsel and not_cs and (not not_wr);

        -- RAM          (4000h-5FFFh)
        ram_regsel <= (not addr(13)) and addr(14);
        ram_regsync <= ram_regsel and not_cs and (not not_wr);

        -- REGISTERS
        -- ---------

        -- RAM enable register
        ram_enable:process(ram_e_regsync, not_reset) is
        begin
            if rising_edge(ram_e_regsync) then
                ram_e_q0 <= (ram_e_code) and not_reset;
            end if;
        end process ram_enable;

        -- RAM 16 register
        ram16reg:process(ram_regsync, not_reset) is
        begin
            if rising_edge(ram_regsync) then
                ramq3 <= data(3) and not_reset;
            end if;
        end process ram16reg;

        -- RAM 15 register
        ram15reg:process(ram_regsync, not_reset) is
        begin
            if rising_edge(ram_regsync) then
                ramq2 <= data(2) and not_reset;
            end if;
        end process ram15reg;

        -- RAM 14 register
        ram14reg:process(ram_regsync, not_reset) is
        begin
            if rising_edge(ram_regsync) then
                ramq1 <= data(1) and not_reset;
            end if;
        end process ram14reg;

        -- RAM 13 register
        ram13reg:process(ram_regsync, not_reset) is
        begin
            if rising_edge(ram_regsync) then
                ramq0 <= data(0) and not_reset;
            end if;
        end process ram13reg;

        -- ROM High registers
        -- ------------------

        -- ROM 22 register
        romh22reg:process(romh_regsync, not_reset) is
        begin
            if rising_edge(romh_regsync) then
                romhq0 <= data(0) and not_reset;
            end if;
        end process romh22reg;

        -- ROM Low registers
        -- -----------------

        -- ROM 21 register
        roml21reg:process(roml_regsync, not_reset) is
        begin
            if rising_edge(roml_regsync) then
                romlq7 <= data(7) and not_reset;
            end if;
        end process roml21reg;

        -- ROM 20 register
        roml20reg:process(roml_regsync, not_reset) is
        begin
            if rising_edge(roml_regsync) then
                romlq6 <= data(6) and not_reset;
            end if;
        end process roml20reg;

        -- ROM 19 register
        roml19reg:process(roml_regsync, not_reset) is
        begin
            if rising_edge(roml_regsync) then
                romlq5 <= data(5) and not_reset;
            end if;
        end process roml19reg;

        -- ROM 18 register
        roml18reg:process(roml_regsync, not_reset) is
        begin
            if rising_edge(roml_regsync) then
                romlq4 <= data(4) and not_reset;
            end if;
        end process roml18reg;

        -- ROM 17 register
        roml17reg:process(roml_regsync, not_reset) is
        begin
            if rising_edge(roml_regsync) then
                romlq3 <= data(3) and not_reset;
            end if;
        end process roml17reg;

        -- ROM 16 register
        roml16reg:process(roml_regsync, not_reset) is
        begin
            if rising_edge(roml_regsync) then
                romlq2 <= data(2) and not_reset;
            end if;
        end process roml16reg;

        -- ROM 15 register
        roml15reg:process(roml_regsync, not_reset) is
        begin
            if rising_edge(roml_regsync) then
                romlq1 <= data(1) and not_reset;
            end if;
        end process roml15reg;

        -- ROM 14 register
        roml14reg:process(roml_regsync, not_reset) is
        begin
            if rising_edge(roml_regsync) then
                romlq0 <= data(0) and not_reset;
            end if;
        end process roml14reg;

        -- Outputs
        -- -------
        not_ram_cs <=   not ram_e_q0;

        ram_addr(16) <= ramq3;
        ram_addr(15) <= ramq2;
        ram_addr(14) <= ramq1;
        ram_addr(13) <= ramq0;

        rom_addr(22) <= romhq0 and addr(14);

        rom_addr(21) <= romlq7 and addr(14);
        rom_addr(20) <= romlq6 and addr(14);
        rom_addr(19) <= romlq5 and addr(14);
        rom_addr(18) <= romlq4 and addr(14);
        rom_addr(17) <= romlq3 and addr(14);
        rom_addr(16) <= romlq2 and addr(14);
        rom_addr(15) <= romlq1 and addr(14);
        -- rom14 line is special because it has to map bank 0 correctly
        bank0map <= not(romlq1 or romlq2 or romlq3 or romlq4 or romlq5 or romlq6 or romlq7);
        rom_addr(14) <= (romlq0 or bank0map) and addr(14);

end architecture Behavioral;