library IEEE;
use IEEE.std_logic_1164.all;
entity ajinkya is
port(a:in std_logic_vector(0 to 3);
sel: in std_logic_vector(0 to 1);
y:out std_logic);
end ajinkya;
architecture aj1 of ajinkya is
begin
process(a,sel)
begin
case sel is
 when "00"=> y <=a(0);
 when "01"=> y <=a(1);
 when "10"=> y <=a(2);
 when "11"=> y <=a(3);
 end case;
 end process;
end aj1;