LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY mem8x4_tb IS
END mem8x4_tb;

ARCHITECTURE behavior OF mem8x4_tb IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT memorie8x4
    PORT(
            clk: in std_logic;
         cs : IN  std_logic;
         rw : IN  std_logic;
         address : IN  std_logic_vector(2 downto 0);
         output : INOUT  std_logic_vector(3 downto 0)
        );
    END COMPONENT;


   --Inputs
    signal clk : std_logic := '0';
   signal cs : std_logic := '0'; -- default neselectat
   signal rw : std_logic := '1'; -- default read mode
   signal address : std_logic_vector(2 downto 0) := (others => '0'); -- default adresa 0

   signal output : std_logic_vector(3 downto 0) := "0000";

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: memorie8x4 PORT MAP (
             clk => clk,
          cs => cs,
          rw => rw,
          address => address,
          output => output
        );

    process
    begin
        clk <= '0';
        wait for 2 ns;
        clk <= '1';
        wait for 2 ns;
    end process;

   -- vreau sa citesc o valoare din memorie, dupa care sa inchid chip-ul,
    -- sa scriu o valoare in memorie, sa inchid chip-ul, sa trec in read
    -- si sa citesc daca valoarea a fost scrisa
    process
    begin

        wait for 10 ns;
        address <= "010"; -- selectez adresa
        rw <= '1'; -- trec in modul read
        cs <= '1'; -- activez memoria -> citesc output-ul
        wait for 10 ns;
        cs <= '0'; -- dezactivez memoria
        rw <= '0'; -- trec in modul write
        output <= "0110"; -- scriu ceva la output
        cs <= '1'; -- activez memoria, se scrie in memorie
        wait for 10 ns;
        cs <= '0'; -- dezactivez memoria
        rw <= '1'; -- trec in modul read
        address <= "001";
        cs <= '1';
        wait for 10 ns;
        address <= "010";
        --cs <= '1'; -- activez memoria, citesc valoarea de la output
        wait for 10 ns;
        wait;
    end process;


END;