LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    use ieee.numeric_std.ALL;
    use ieee.std_logic_arith.all;

entity UART is
    port (
        clk_10mhz: in STD_LOGIC;
        uart_clk: out STD_LOGIC;
        txPin: out STD_LOGIC
    );
end entity;

architecture Test of UART is
    signal txStart: STD_LOGIC := '0';
    signal txIdle: STD_LOGIC;
    signal txData: STD_LOGIC_VECTOR(7 downto 0);

    component TX is
        port (
            clk_in: in STD_LOGIC;
            start: in STD_LOGIC;
            data: in STD_LOGIC_VECTOR(7 downto 0);
            tx: out STD_LOGIC;
            txIdle: out STD_LOGIC;
            debug_clk: out STD_LOGIC
        );
    end component TX;


begin
    process (clk_10mhz)
        variable clkDividerCounter : integer range 0 to 10000000;
        variable textToSend : string(1 to 31) := " " & LF & CR;
        variable currentCharacterIndex : integer range 1 to 31 := 1;
        variable startSending : std_logic := '0';
        variable characterReceivedByTX : std_logic := '1';
    begin
        if (rising_edge(clk_10mhz)) then
            if (startSending = '1') then
                if (txIdle = '0') then
                    characterReceivedByTX := '1';
                end if;

                if (txIdle = '1' and characterReceivedByTX = '1') then
                    txData <= CONV_STD_LOGIC_VECTOR(character'pos(textToSend(currentCharacterIndex)),8);
                    txStart <= '1';

                    if (currentCharacterIndex < 31) then
                        currentCharacterIndex := currentCharacterIndex + 1;
                        characterReceivedByTX := '0';
                    else
                        txStart <= '0';
                        currentCharacterIndex := 1;
                        startSending := '0';
                    end if;
                end if;
            else
                if (clkDividerCounter < 10000000) then
                    clkDividerCounter := clkDividerCounter + 1;
                    startSending := '0';
                else
                    clkDividerCounter := 0;
                    startSending := '1';
                end if;
            end if;
        end if;
    end process;


    u1: TX port map (clk_10mhz, txStart, txData, txPin, txIdle, uart_clk);
end Test;