API tools faq
paste
Advertisement
Guest User

agd5f-latest.patch

a guest
Aug 6th, 2013
95
0
Never
Add comment
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
Diff 40.48 KB | None | 0 0
raw download clone embed print report
  1. diff --git a/drivers/gpu/drm/radeon/btc_dpm.c b/drivers/gpu/drm/radeon/btc_dpm.c
  2. index 0bfd55e..9953e1f 100644
  3. --- a/drivers/gpu/drm/radeon/btc_dpm.c
  4. +++ b/drivers/gpu/drm/radeon/btc_dpm.c
  5. @@ -2548,9 +2548,6 @@ int btc_dpm_init(struct radeon_device *rdev)
  6.  {
  7.     struct rv7xx_power_info *pi;
  8.     struct evergreen_power_info *eg_pi;
  9. -   int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
  10. -   u16 data_offset, size;
  11. -   u8 frev, crev;
  12.     struct atom_clock_dividers dividers;
  13.     int ret;
  14.  
  15. @@ -2633,16 +2630,7 @@ int btc_dpm_init(struct radeon_device *rdev)
  16.     eg_pi->vddci_control =
  17.         radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 0);
  18.  
  19. -   if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
  20. -                                   &frev, &crev, &data_offset)) {
  21. -       pi->sclk_ss = true;
  22. -       pi->mclk_ss = true;
  23. -       pi->dynamic_ss = true;
  24. -   } else {
  25. -       pi->sclk_ss = false;
  26. -       pi->mclk_ss = false;
  27. -       pi->dynamic_ss = true;
  28. -   }
  29. +   rv770_get_engine_memory_ss(rdev);
  30.  
  31.     pi->asi = RV770_ASI_DFLT;
  32.     pi->pasi = CYPRESS_HASI_DFLT;
  33. @@ -2659,8 +2647,7 @@ int btc_dpm_init(struct radeon_device *rdev)
  34.  
  35.     pi->dynamic_pcie_gen2 = true;
  36.  
  37. -   if (pi->gfx_clock_gating &&
  38. -       (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE))
  39. +   if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
  40.         pi->thermal_protection = true;
  41.     else
  42.         pi->thermal_protection = false;
  43. diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
  44. index 6dacec4..8928bd1 100644
  45. --- a/drivers/gpu/drm/radeon/cik.c
  46. +++ b/drivers/gpu/drm/radeon/cik.c
  47. @@ -2587,9 +2587,11 @@ u32 cik_compute_ring_get_rptr(struct radeon_device *rdev,
  48.     if (rdev->wb.enabled) {
  49.         rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
  50.     } else {
  51. +       mutex_lock(&rdev->srbm_mutex);
  52.         cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0);
  53.         rptr = RREG32(CP_HQD_PQ_RPTR);
  54.         cik_srbm_select(rdev, 0, 0, 0, 0);
  55. +       mutex_unlock(&rdev->srbm_mutex);
  56.     }
  57.     rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift;
  58.  
  59. @@ -2604,9 +2606,11 @@ u32 cik_compute_ring_get_wptr(struct radeon_device *rdev,
  60.     if (rdev->wb.enabled) {
  61.         wptr = le32_to_cpu(rdev->wb.wb[ring->wptr_offs/4]);
  62.     } else {
  63. +       mutex_lock(&rdev->srbm_mutex);
  64.         cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0);
  65.         wptr = RREG32(CP_HQD_PQ_WPTR);
  66.         cik_srbm_select(rdev, 0, 0, 0, 0);
  67. +       mutex_unlock(&rdev->srbm_mutex);
  68.     }
  69.     wptr = (wptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift;
  70.  
  71. @@ -2897,6 +2901,7 @@ static int cik_cp_compute_resume(struct radeon_device *rdev)
  72.     WREG32(CP_CPF_DEBUG, tmp);
  73.  
  74.     /* init the pipes */
  75. +   mutex_lock(&rdev->srbm_mutex);
  76.     for (i = 0; i < (rdev->mec.num_pipe * rdev->mec.num_mec); i++) {
  77.         int me = (i < 4) ? 1 : 2;
  78.         int pipe = (i < 4) ? i : (i - 4);
  79. @@ -2919,6 +2924,7 @@ static int cik_cp_compute_resume(struct radeon_device *rdev)
  80.         WREG32(CP_HPD_EOP_CONTROL, tmp);
  81.     }
  82.     cik_srbm_select(rdev, 0, 0, 0, 0);
  83. +   mutex_unlock(&rdev->srbm_mutex);
  84.  
  85.     /* init the queues.  Just two for now. */
  86.     for (i = 0; i < 2; i++) {
  87. @@ -2972,6 +2978,7 @@ static int cik_cp_compute_resume(struct radeon_device *rdev)
  88.         mqd->static_thread_mgmt23[0] = 0xffffffff;
  89.         mqd->static_thread_mgmt23[1] = 0xffffffff;
  90.  
  91. +       mutex_lock(&rdev->srbm_mutex);
  92.         cik_srbm_select(rdev, rdev->ring[idx].me,
  93.                 rdev->ring[idx].pipe,
  94.                 rdev->ring[idx].queue, 0);
  95. @@ -3099,6 +3106,7 @@ static int cik_cp_compute_resume(struct radeon_device *rdev)
  96.         WREG32(CP_HQD_ACTIVE, mqd->queue_state.cp_hqd_active);
  97.  
  98.         cik_srbm_select(rdev, 0, 0, 0, 0);
  99. +       mutex_unlock(&rdev->srbm_mutex);
  100.  
  101.         radeon_bo_kunmap(rdev->ring[idx].mqd_obj);
  102.         radeon_bo_unreserve(rdev->ring[idx].mqd_obj);
  103. @@ -4320,6 +4328,7 @@ static int cik_pcie_gart_enable(struct radeon_device *rdev)
  104.  
  105.     /* XXX SH_MEM regs */
  106.     /* where to put LDS, scratch, GPUVM in FSA64 space */
  107. +   mutex_lock(&rdev->srbm_mutex);
  108.     for (i = 0; i < 16; i++) {
  109.         cik_srbm_select(rdev, 0, 0, 0, i);
  110.         /* CP and shaders */
  111. @@ -4335,6 +4344,7 @@ static int cik_pcie_gart_enable(struct radeon_device *rdev)
  112.         /* XXX SDMA RLC - todo */
  113.     }
  114.     cik_srbm_select(rdev, 0, 0, 0, 0);
  115. +   mutex_unlock(&rdev->srbm_mutex);
  116.  
  117.     cik_pcie_gart_tlb_flush(rdev);
  118.     DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
  119. @@ -5954,6 +5964,8 @@ static int cik_startup(struct radeon_device *rdev)
  120.     struct radeon_ring *ring;
  121.     int r;
  122.  
  123. +   cik_mc_program(rdev);
  124. +
  125.     if (rdev->flags & RADEON_IS_IGP) {
  126.         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||
  127.             !rdev->mec_fw || !rdev->sdma_fw || !rdev->rlc_fw) {
  128. @@ -5985,7 +5997,6 @@ static int cik_startup(struct radeon_device *rdev)
  129.     if (r)
  130.         return r;
  131.  
  132. -   cik_mc_program(rdev);
  133.     r = cik_pcie_gart_enable(rdev);
  134.     if (r)
  135.         return r;
  136. @@ -6194,7 +6205,7 @@ int cik_suspend(struct radeon_device *rdev)
  137.     radeon_vm_manager_fini(rdev);
  138.     cik_cp_enable(rdev, false);
  139.     cik_sdma_enable(rdev, false);
  140. -   r600_uvd_rbc_stop(rdev);
  141. +   r600_uvd_stop(rdev);
  142.     radeon_uvd_suspend(rdev);
  143.     cik_irq_suspend(rdev);
  144.     radeon_wb_disable(rdev);
  145. @@ -6358,6 +6369,7 @@ void cik_fini(struct radeon_device *rdev)
  146.     radeon_vm_manager_fini(rdev);
  147.     radeon_ib_pool_fini(rdev);
  148.     radeon_irq_kms_fini(rdev);
  149. +   r600_uvd_stop(rdev);
  150.     radeon_uvd_fini(rdev);
  151.     cik_pcie_gart_fini(rdev);
  152.     r600_vram_scratch_fini(rdev);
  153. @@ -6978,7 +6990,7 @@ int cik_uvd_resume(struct radeon_device *rdev)
  154.  
  155.     /* programm the VCPU memory controller bits 0-27 */
  156.     addr = rdev->uvd.gpu_addr >> 3;
  157. -   size = RADEON_GPU_PAGE_ALIGN(rdev->uvd.fw_size + 4) >> 3;
  158. +   size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 4) >> 3;
  159.     WREG32(UVD_VCPU_CACHE_OFFSET0, addr);
  160.     WREG32(UVD_VCPU_CACHE_SIZE0, size);
  161.  
  162. diff --git a/drivers/gpu/drm/radeon/cypress_dpm.c b/drivers/gpu/drm/radeon/cypress_dpm.c
  163. index 9bcdd17..7e5d0b5 100644
  164. --- a/drivers/gpu/drm/radeon/cypress_dpm.c
  165. +++ b/drivers/gpu/drm/radeon/cypress_dpm.c
  166. @@ -2038,9 +2038,6 @@ int cypress_dpm_init(struct radeon_device *rdev)
  167.  {
  168.     struct rv7xx_power_info *pi;
  169.     struct evergreen_power_info *eg_pi;
  170. -   int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
  171. -   uint16_t data_offset, size;
  172. -   uint8_t frev, crev;
  173.     struct atom_clock_dividers dividers;
  174.     int ret;
  175.  
  176. @@ -2092,16 +2089,7 @@ int cypress_dpm_init(struct radeon_device *rdev)
  177.     eg_pi->vddci_control =
  178.         radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 0);
  179.  
  180. -   if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
  181. -                                   &frev, &crev, &data_offset)) {
  182. -       pi->sclk_ss = true;
  183. -       pi->mclk_ss = true;
  184. -       pi->dynamic_ss = true;
  185. -   } else {
  186. -       pi->sclk_ss = false;
  187. -       pi->mclk_ss = false;
  188. -       pi->dynamic_ss = true;
  189. -   }
  190. +   rv770_get_engine_memory_ss(rdev);
  191.  
  192.     pi->asi = RV770_ASI_DFLT;
  193.     pi->pasi = CYPRESS_HASI_DFLT;
  194. @@ -2122,8 +2110,7 @@ int cypress_dpm_init(struct radeon_device *rdev)
  195.  
  196.     pi->dynamic_pcie_gen2 = true;
  197.  
  198. -   if (pi->gfx_clock_gating &&
  199. -       (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE))
  200. +   if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
  201.         pi->thermal_protection = true;
  202.     else
  203.         pi->thermal_protection = false;
  204. diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
  205. index 038dcac..d5b49e3 100644
  206. --- a/drivers/gpu/drm/radeon/evergreen.c
  207. +++ b/drivers/gpu/drm/radeon/evergreen.c
  208. @@ -5106,6 +5106,8 @@ static int evergreen_startup(struct radeon_device *rdev)
  209.     /* enable aspm */
  210.     evergreen_program_aspm(rdev);
  211.  
  212. +   evergreen_mc_program(rdev);
  213. +
  214.     if (ASIC_IS_DCE5(rdev)) {
  215.         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
  216.             r = ni_init_microcode(rdev);
  217. @@ -5133,7 +5135,6 @@ static int evergreen_startup(struct radeon_device *rdev)
  218.     if (r)
  219.         return r;
  220.  
  221. -   evergreen_mc_program(rdev);
  222.     if (rdev->flags & RADEON_IS_AGP) {
  223.         evergreen_agp_enable(rdev);
  224.     } else {
  225. @@ -5291,10 +5292,10 @@ int evergreen_resume(struct radeon_device *rdev)
  226.  int evergreen_suspend(struct radeon_device *rdev)
  227.  {
  228.     r600_audio_fini(rdev);
  229. +   r600_uvd_stop(rdev);
  230.     radeon_uvd_suspend(rdev);
  231.     r700_cp_stop(rdev);
  232.     r600_dma_stop(rdev);
  233. -   r600_uvd_rbc_stop(rdev);
  234.     evergreen_irq_suspend(rdev);
  235.     radeon_wb_disable(rdev);
  236.     evergreen_pcie_gart_disable(rdev);
  237. @@ -5429,6 +5430,7 @@ void evergreen_fini(struct radeon_device *rdev)
  238.     radeon_ib_pool_fini(rdev);
  239.     radeon_irq_kms_fini(rdev);
  240.     evergreen_pcie_gart_fini(rdev);
  241. +   r600_uvd_stop(rdev);
  242.     radeon_uvd_fini(rdev);
  243.     r600_vram_scratch_fini(rdev);
  244.     radeon_gem_fini(rdev);
  245. diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c
  246. index bb9ea36..b0e2800 100644
  247. --- a/drivers/gpu/drm/radeon/evergreen_hdmi.c
  248. +++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c
  249. @@ -148,18 +148,40 @@ static void evergreen_audio_set_dto(struct drm_encoder *encoder, u32 clock)
  250.     struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
  251.     struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
  252.     u32 base_rate = 24000;
  253. +   u32 max_ratio = clock / base_rate;
  254. +   u32 dto_phase;
  255. +   u32 dto_modulo = clock;
  256. +   u32 wallclock_ratio;
  257. +   u32 dto_cntl;
  258.  
  259.     if (!dig || !dig->afmt)
  260.         return;
  261.  
  262. +   if (max_ratio >= 8) {
  263. +       dto_phase = 192 * 1000;
  264. +       wallclock_ratio = 3;
  265. +   } else if (max_ratio >= 4) {
  266. +       dto_phase = 96 * 1000;
  267. +       wallclock_ratio = 2;
  268. +   } else if (max_ratio >= 2) {
  269. +       dto_phase = 48 * 1000;
  270. +       wallclock_ratio = 1;
  271. +   } else {
  272. +       dto_phase = 24 * 1000;
  273. +       wallclock_ratio = 0;
  274. +   }
  275. +   dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
  276. +   dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);
  277. +   WREG32(DCCG_AUDIO_DTO0_CNTL, dto_cntl);
  278. +
  279.     /* XXX two dtos; generally use dto0 for hdmi */
  280.     /* Express [24MHz / target pixel clock] as an exact rational
  281.      * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
  282.      * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
  283.      */
  284.     WREG32(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL(radeon_crtc->crtc_id));
  285. -   WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 100);
  286. -   WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100);
  287. +   WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase);
  288. +   WREG32(DCCG_AUDIO_DTO0_MODULE, dto_modulo);
  289.  }
  290.  
  291.  
  292. diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
  293. index a7baf67..0d582ac 100644
  294. --- a/drivers/gpu/drm/radeon/evergreend.h
  295. +++ b/drivers/gpu/drm/radeon/evergreend.h
  296. @@ -497,6 +497,9 @@
  297.  #define DCCG_AUDIO_DTO0_MODULE            0x05b4
  298.  #define DCCG_AUDIO_DTO0_LOAD              0x05b8
  299.  #define DCCG_AUDIO_DTO0_CNTL              0x05bc
  300. +#       define DCCG_AUDIO_DTO_WALLCLOCK_RATIO(x) (((x) & 7) << 0)
  301. +#       define DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK 7
  302. +#       define DCCG_AUDIO_DTO_WALLCLOCK_RATIO_SHIFT 0
  303.  
  304.  #define DCCG_AUDIO_DTO1_PHASE             0x05c0
  305.  #define DCCG_AUDIO_DTO1_MODULE            0x05c4
  306. diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
  307. index 56bd4f3..12cebe4 100644
  308. --- a/drivers/gpu/drm/radeon/ni.c
  309. +++ b/drivers/gpu/drm/radeon/ni.c
  310. @@ -2079,6 +2079,8 @@ static int cayman_startup(struct radeon_device *rdev)
  311.     /* enable aspm */
  312.     evergreen_program_aspm(rdev);
  313.  
  314. +   evergreen_mc_program(rdev);
  315. +
  316.     if (rdev->flags & RADEON_IS_IGP) {
  317.         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
  318.             r = ni_init_microcode(rdev);
  319. @@ -2107,7 +2109,6 @@ static int cayman_startup(struct radeon_device *rdev)
  320.     if (r)
  321.         return r;
  322.  
  323. -   evergreen_mc_program(rdev);
  324.     r = cayman_pcie_gart_enable(rdev);
  325.     if (r)
  326.         return r;
  327. @@ -2286,7 +2287,7 @@ int cayman_suspend(struct radeon_device *rdev)
  328.     radeon_vm_manager_fini(rdev);
  329.     cayman_cp_enable(rdev, false);
  330.     cayman_dma_stop(rdev);
  331. -   r600_uvd_rbc_stop(rdev);
  332. +   r600_uvd_stop(rdev);
  333.     radeon_uvd_suspend(rdev);
  334.     evergreen_irq_suspend(rdev);
  335.     radeon_wb_disable(rdev);
  336. @@ -2418,6 +2419,7 @@ void cayman_fini(struct radeon_device *rdev)
  337.     radeon_vm_manager_fini(rdev);
  338.     radeon_ib_pool_fini(rdev);
  339.     radeon_irq_kms_fini(rdev);
  340. +   r600_uvd_stop(rdev);
  341.     radeon_uvd_fini(rdev);
  342.     cayman_pcie_gart_fini(rdev);
  343.     r600_vram_scratch_fini(rdev);
  344. diff --git a/drivers/gpu/drm/radeon/ni_dpm.c b/drivers/gpu/drm/radeon/ni_dpm.c
  345. index 4f9b9bc..f0f5f74 100644
  346. --- a/drivers/gpu/drm/radeon/ni_dpm.c
  347. +++ b/drivers/gpu/drm/radeon/ni_dpm.c
  348. @@ -4067,9 +4067,6 @@ int ni_dpm_init(struct radeon_device *rdev)
  349.     struct rv7xx_power_info *pi;
  350.     struct evergreen_power_info *eg_pi;
  351.     struct ni_power_info *ni_pi;
  352. -   int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
  353. -   u16 data_offset, size;
  354. -   u8 frev, crev;
  355.     struct atom_clock_dividers dividers;
  356.     int ret;
  357.  
  358. @@ -4162,16 +4159,7 @@ int ni_dpm_init(struct radeon_device *rdev)
  359.     eg_pi->vddci_control =
  360.         radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 0);
  361.  
  362. -   if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
  363. -                                   &frev, &crev, &data_offset)) {
  364. -       pi->sclk_ss = true;
  365. -       pi->mclk_ss = true;
  366. -       pi->dynamic_ss = true;
  367. -   } else {
  368. -       pi->sclk_ss = false;
  369. -       pi->mclk_ss = false;
  370. -       pi->dynamic_ss = true;
  371. -   }
  372. +   rv770_get_engine_memory_ss(rdev);
  373.  
  374.     pi->asi = RV770_ASI_DFLT;
  375.     pi->pasi = CYPRESS_HASI_DFLT;
  376. @@ -4188,8 +4176,7 @@ int ni_dpm_init(struct radeon_device *rdev)
  377.  
  378.     pi->dynamic_pcie_gen2 = true;
  379.  
  380. -   if (pi->gfx_clock_gating &&
  381. -       (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE))
  382. +   if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
  383.         pi->thermal_protection = true;
  384.     else
  385.         pi->thermal_protection = false;
  386. diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
  387. index 10f712e..af84804 100644
  388. --- a/drivers/gpu/drm/radeon/r600.c
  389. +++ b/drivers/gpu/drm/radeon/r600.c
  390. @@ -2697,12 +2697,29 @@ int r600_uvd_rbc_start(struct radeon_device *rdev)
  391.     return 0;
  392.  }
  393.  
  394. -void r600_uvd_rbc_stop(struct radeon_device *rdev)
  395. +void r600_uvd_stop(struct radeon_device *rdev)
  396.  {
  397.     struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
  398.  
  399.     /* force RBC into idle state */
  400.     WREG32(UVD_RBC_RB_CNTL, 0x11010101);
  401. +
  402. +   /* Stall UMC and register bus before resetting VCPU */
  403. +   WREG32_P(UVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
  404. +   WREG32_P(UVD_RB_ARB_CTRL, 1 << 3, ~(1 << 3));
  405. +   mdelay(1);
  406. +
  407. +   /* put VCPU into reset */
  408. +   WREG32(UVD_SOFT_RESET, VCPU_SOFT_RESET);
  409. +   mdelay(5);
  410. +
  411. +   /* disable VCPU clock */
  412. +   WREG32(UVD_VCPU_CNTL, 0x0);
  413. +
  414. +   /* Unstall UMC and register bus */
  415. +   WREG32_P(UVD_LMI_CTRL2, 0, ~(1 << 8));
  416. +   WREG32_P(UVD_RB_ARB_CTRL, 0, ~(1 << 3));
  417. +
  418.     ring->ready = false;
  419.  }
  420.  
  421. @@ -2722,6 +2739,11 @@ int r600_uvd_init(struct radeon_device *rdev)
  422.     /* disable interupt */
  423.     WREG32_P(UVD_MASTINT_EN, 0, ~(1 << 1));
  424.  
  425. +   /* Stall UMC and register bus before resetting VCPU */
  426. +   WREG32_P(UVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
  427. +   WREG32_P(UVD_RB_ARB_CTRL, 1 << 3, ~(1 << 3));
  428. +   mdelay(1);
  429. +
  430.     /* put LMI, VCPU, RBC etc... into reset */
  431.     WREG32(UVD_SOFT_RESET, LMI_SOFT_RESET | VCPU_SOFT_RESET |
  432.            LBSI_SOFT_RESET | RBC_SOFT_RESET | CSM_SOFT_RESET |
  433. @@ -2751,10 +2773,6 @@ int r600_uvd_init(struct radeon_device *rdev)
  434.     WREG32(UVD_MPC_SET_ALU, 0);
  435.     WREG32(UVD_MPC_SET_MUX, 0x88);
  436.  
  437. -   /* Stall UMC */
  438. -   WREG32_P(UVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
  439. -   WREG32_P(UVD_RB_ARB_CTRL, 1 << 3, ~(1 << 3));
  440. -
  441.     /* take all subblocks out of reset, except VCPU */
  442.     WREG32(UVD_SOFT_RESET, VCPU_SOFT_RESET);
  443.     mdelay(5);
  444. @@ -3312,6 +3330,8 @@ static int r600_startup(struct radeon_device *rdev)
  445.     /* enable pcie gen2 link */
  446.     r600_pcie_gen2_enable(rdev);
  447.  
  448. +   r600_mc_program(rdev);
  449. +
  450.     if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
  451.         r = r600_init_microcode(rdev);
  452.         if (r) {
  453. @@ -3324,7 +3344,6 @@ static int r600_startup(struct radeon_device *rdev)
  454.     if (r)
  455.         return r;
  456.  
  457. -   r600_mc_program(rdev);
  458.     if (rdev->flags & RADEON_IS_AGP) {
  459.         r600_agp_enable(rdev);
  460.     } else {
  461. diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c
  462. index f48240b..f264df5 100644
  463. --- a/drivers/gpu/drm/radeon/r600_hdmi.c
  464. +++ b/drivers/gpu/drm/radeon/r600_hdmi.c
  465. @@ -226,10 +226,29 @@ void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock)
  466.     struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  467.     struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
  468.     u32 base_rate = 24000;
  469. +   u32 max_ratio = clock / base_rate;
  470. +   u32 dto_phase;
  471. +   u32 dto_modulo = clock;
  472. +   u32 wallclock_ratio;
  473. +   u32 dto_cntl;
  474.  
  475.     if (!dig || !dig->afmt)
  476.         return;
  477.  
  478. +   if (max_ratio >= 8) {
  479. +       dto_phase = 192 * 1000;
  480. +       wallclock_ratio = 3;
  481. +   } else if (max_ratio >= 4) {
  482. +       dto_phase = 96 * 1000;
  483. +       wallclock_ratio = 2;
  484. +   } else if (max_ratio >= 2) {
  485. +       dto_phase = 48 * 1000;
  486. +       wallclock_ratio = 1;
  487. +   } else {
  488. +       dto_phase = 24 * 1000;
  489. +       wallclock_ratio = 0;
  490. +   }
  491. +
  492.     /* there are two DTOs selected by DCCG_AUDIO_DTO_SELECT.
  493.      * doesn't matter which one you use.  Just use the first one.
  494.      */
  495. @@ -242,9 +261,21 @@ void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock)
  496.         /* according to the reg specs, this should DCE3.2 only, but in
  497.          * practice it seems to cover DCE3.0 as well.
  498.          */
  499. -       WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 100);
  500. -       WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100);
  501. -       WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */
  502. +       if (dig->dig_encoder == 0) {
  503. +           dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
  504. +           dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);
  505. +           WREG32(DCCG_AUDIO_DTO0_CNTL, dto_cntl);
  506. +           WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase);
  507. +           WREG32(DCCG_AUDIO_DTO0_MODULE, dto_modulo);
  508. +           WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */
  509. +       } else {
  510. +           dto_cntl = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
  511. +           dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);
  512. +           WREG32(DCCG_AUDIO_DTO1_CNTL, dto_cntl);
  513. +           WREG32(DCCG_AUDIO_DTO1_PHASE, dto_phase);
  514. +           WREG32(DCCG_AUDIO_DTO1_MODULE, dto_modulo);
  515. +           WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */
  516. +       }
  517.     } else {
  518.         /* according to the reg specs, this should be DCE2.0 and DCE3.0 */
  519.         WREG32(AUDIO_DTO, AUDIO_DTO_PHASE(base_rate / 10) |
  520. diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
  521. index 8e3fe81..7c78083 100644
  522. --- a/drivers/gpu/drm/radeon/r600d.h
  523. +++ b/drivers/gpu/drm/radeon/r600d.h
  524. @@ -933,6 +933,9 @@
  525.  #define DCCG_AUDIO_DTO0_LOAD              0x051c
  526.  #       define DTO_LOAD                   (1 << 31)
  527.  #define DCCG_AUDIO_DTO0_CNTL              0x0520
  528. +#       define DCCG_AUDIO_DTO_WALLCLOCK_RATIO(x) (((x) & 7) << 0)
  529. +#       define DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK 7
  530. +#       define DCCG_AUDIO_DTO_WALLCLOCK_RATIO_SHIFT 0
  531.  
  532.  #define DCCG_AUDIO_DTO1_PHASE             0x0524
  533.  #define DCCG_AUDIO_DTO1_MODULE            0x0528
  534. diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
  535. index 2f08219..274b8e1 100644
  536. --- a/drivers/gpu/drm/radeon/radeon.h
  537. +++ b/drivers/gpu/drm/radeon/radeon.h
  538. @@ -1468,7 +1468,6 @@ struct radeon_uvd {
  539.     void            *cpu_addr;
  540.     uint64_t        gpu_addr;
  541.     void            *saved_bo;
  542. -   unsigned        fw_size;
  543.     atomic_t        handles[RADEON_MAX_UVD_HANDLES];
  544.     struct drm_file     *filp[RADEON_MAX_UVD_HANDLES];
  545.     struct delayed_work idle_work;
  546. @@ -2066,6 +2065,7 @@ struct radeon_device {
  547.     const struct firmware *mec_fw;  /* CIK MEC firmware */
  548.     const struct firmware *sdma_fw; /* CIK SDMA firmware */
  549.     const struct firmware *smc_fw;  /* SMC firmware */
  550. +   const struct firmware *uvd_fw;  /* UVD firmware */
  551.     struct r600_blit r600_blit;
  552.     struct r600_vram_scratch vram_scratch;
  553.     int msi_enabled; /* msi enabled */
  554. @@ -2095,6 +2095,8 @@ struct radeon_device {
  555.     /* ACPI interface */
  556.     struct radeon_atif      atif;
  557.     struct radeon_atcs      atcs;
  558. +   /* srbm instance registers */
  559. +   struct mutex            srbm_mutex;
  560.  };
  561.  
  562.  int radeon_device_init(struct radeon_device *rdev,
  563. diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
  564. index 902479f..3d61d5a 100644
  565. --- a/drivers/gpu/drm/radeon/radeon_asic.h
  566. +++ b/drivers/gpu/drm/radeon/radeon_asic.h
  567. @@ -441,7 +441,7 @@ void rs780_dpm_debugfs_print_current_performance_level(struct radeon_device *rde
  568.  /* uvd */
  569.  int r600_uvd_init(struct radeon_device *rdev);
  570.  int r600_uvd_rbc_start(struct radeon_device *rdev);
  571. -void r600_uvd_rbc_stop(struct radeon_device *rdev);
  572. +void r600_uvd_stop(struct radeon_device *rdev);
  573.  int r600_uvd_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
  574.  void r600_uvd_fence_emit(struct radeon_device *rdev,
  575.              struct radeon_fence *fence);
  576. diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
  577. index 82335e3..63398ae 100644
  578. --- a/drivers/gpu/drm/radeon/radeon_device.c
  579. +++ b/drivers/gpu/drm/radeon/radeon_device.c
  580. @@ -1163,6 +1163,7 @@ int radeon_device_init(struct radeon_device *rdev,
  581.     mutex_init(&rdev->gem.mutex);
  582.     mutex_init(&rdev->pm.mutex);
  583.     mutex_init(&rdev->gpu_clock_mutex);
  584. +   mutex_init(&rdev->srbm_mutex);
  585.     init_rwsem(&rdev->pm.mclk_lock);
  586.     init_rwsem(&rdev->exclusive_lock);
  587.     init_waitqueue_head(&rdev->irq.vblank_queue);
  588. @@ -1519,6 +1520,7 @@ int radeon_gpu_reset(struct radeon_device *rdev)
  589.     radeon_save_bios_scratch_regs(rdev);
  590.     /* block TTM */
  591.     resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
  592. +   radeon_pm_suspend(rdev);
  593.     radeon_suspend(rdev);
  594.  
  595.     for (i = 0; i < RADEON_NUM_RINGS; ++i) {
  596. @@ -1564,6 +1566,7 @@ retry:
  597.         }
  598.     }
  599.  
  600. +   radeon_pm_resume(rdev);
  601.     drm_helper_resume_force_mode(rdev->ddev);
  602.  
  603.     ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
  604. diff --git a/drivers/gpu/drm/radeon/radeon_fence.c b/drivers/gpu/drm/radeon/radeon_fence.c
  605. index 7ddb0ef..ddb8f8e 100644
  606. --- a/drivers/gpu/drm/radeon/radeon_fence.c
  607. +++ b/drivers/gpu/drm/radeon/radeon_fence.c
  608. @@ -782,7 +782,7 @@ int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring)
  609.  
  610.         } else {
  611.             /* put fence directly behind firmware */
  612. -           index = ALIGN(rdev->uvd.fw_size, 8);
  613. +           index = ALIGN(rdev->uvd_fw->size, 8);
  614.             rdev->fence_drv[ring].cpu_addr = rdev->uvd.cpu_addr + index;
  615.             rdev->fence_drv[ring].gpu_addr = rdev->uvd.gpu_addr + index;
  616.         }
  617. diff --git a/drivers/gpu/drm/radeon/radeon_gart.c b/drivers/gpu/drm/radeon/radeon_gart.c
  618. index 6a51d94..b990b1a 100644
  619. --- a/drivers/gpu/drm/radeon/radeon_gart.c
  620. +++ b/drivers/gpu/drm/radeon/radeon_gart.c
  621. @@ -207,7 +207,6 @@ void radeon_gart_table_vram_free(struct radeon_device *rdev)
  622.     if (rdev->gart.robj == NULL) {
  623.         return;
  624.     }
  625. -   radeon_gart_table_vram_unpin(rdev);
  626.     radeon_bo_unref(&rdev->gart.robj);
  627.  }
  628.  
  629. diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c
  630. index f374c46..6a7a80b 100644
  631. --- a/drivers/gpu/drm/radeon/radeon_pm.c
  632. +++ b/drivers/gpu/drm/radeon/radeon_pm.c
  633. @@ -1176,7 +1176,10 @@ int radeon_pm_init(struct radeon_device *rdev)
  634.     case CHIP_VERDE:
  635.     case CHIP_OLAND:
  636.     case CHIP_HAINAN:
  637. -       if (radeon_dpm == 1)
  638. +       /* DPM requires the RLC */
  639. +       if (!rdev->rlc_fw)
  640. +           rdev->pm.pm_method = PM_METHOD_PROFILE;
  641. +       else if (radeon_dpm == 1)
  642.             rdev->pm.pm_method = PM_METHOD_DPM;
  643.         else
  644.             rdev->pm.pm_method = PM_METHOD_PROFILE;
  645. diff --git a/drivers/gpu/drm/radeon/radeon_uvd.c b/drivers/gpu/drm/radeon/radeon_uvd.c
  646. index 414fd14..f1c1575 100644
  647. --- a/drivers/gpu/drm/radeon/radeon_uvd.c
  648. +++ b/drivers/gpu/drm/radeon/radeon_uvd.c
  649. @@ -56,7 +56,6 @@ static void radeon_uvd_idle_work_handler(struct work_struct *work);
  650.  
  651.  int radeon_uvd_init(struct radeon_device *rdev)
  652.  {
  653. -   const struct firmware *fw;
  654.     unsigned long bo_size;
  655.     const char *fw_name;
  656.     int i, r;
  657. @@ -105,14 +104,14 @@ int radeon_uvd_init(struct radeon_device *rdev)
  658.         return -EINVAL;
  659.     }
  660.  
  661. -   r = request_firmware(&fw, fw_name, rdev->dev);
  662. +   r = request_firmware(&rdev->uvd_fw, fw_name, rdev->dev);
  663.     if (r) {
  664.         dev_err(rdev->dev, "radeon_uvd: Can't load firmware \"%s\"\n",
  665.             fw_name);
  666.         return r;
  667.     }
  668.  
  669. -   bo_size = RADEON_GPU_PAGE_ALIGN(fw->size + 8) +
  670. +   bo_size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 8) +
  671.           RADEON_UVD_STACK_SIZE + RADEON_UVD_HEAP_SIZE;
  672.     r = radeon_bo_create(rdev, bo_size, PAGE_SIZE, true,
  673.                  RADEON_GEM_DOMAIN_VRAM, NULL, &rdev->uvd.vcpu_bo);
  674. @@ -145,12 +144,6 @@ int radeon_uvd_init(struct radeon_device *rdev)
  675.  
  676.     radeon_bo_unreserve(rdev->uvd.vcpu_bo);
  677.  
  678. -   rdev->uvd.fw_size = fw->size;
  679. -   memset(rdev->uvd.cpu_addr, 0, bo_size);
  680. -   memcpy(rdev->uvd.cpu_addr, fw->data, fw->size);
  681. -
  682. -   release_firmware(fw);
  683. -
  684.     for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
  685.         atomic_set(&rdev->uvd.handles[i], 0);
  686.         rdev->uvd.filp[i] = NULL;
  687. @@ -174,33 +167,60 @@ void radeon_uvd_fini(struct radeon_device *rdev)
  688.     }
  689.  
  690.     radeon_bo_unref(&rdev->uvd.vcpu_bo);
  691. +
  692. +   release_firmware(rdev->uvd_fw);
  693.  }
  694.  
  695.  int radeon_uvd_suspend(struct radeon_device *rdev)
  696.  {
  697.     unsigned size;
  698. +   void *ptr;
  699. +   int i;
  700.  
  701.     if (rdev->uvd.vcpu_bo == NULL)
  702.         return 0;
  703.  
  704. +   for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i)
  705. +       if (atomic_read(&rdev->uvd.handles[i]))
  706. +           break;
  707. +
  708. +   if (i == RADEON_MAX_UVD_HANDLES)
  709. +       return 0;
  710. +
  711.     size = radeon_bo_size(rdev->uvd.vcpu_bo);
  712. +   size -= rdev->uvd_fw->size;
  713. +
  714. +   ptr = rdev->uvd.cpu_addr;
  715. +   ptr += rdev->uvd_fw->size;
  716. +
  717.     rdev->uvd.saved_bo = kmalloc(size, GFP_KERNEL);
  718. -   memcpy(rdev->uvd.saved_bo, rdev->uvd.cpu_addr, size);
  719. +   memcpy(rdev->uvd.saved_bo, ptr, size);
  720.  
  721.     return 0;
  722.  }
  723.  
  724.  int radeon_uvd_resume(struct radeon_device *rdev)
  725.  {
  726. +   unsigned size;
  727. +   void *ptr;
  728. +
  729.     if (rdev->uvd.vcpu_bo == NULL)
  730.         return -EINVAL;
  731.  
  732. +   memcpy(rdev->uvd.cpu_addr, rdev->uvd_fw->data, rdev->uvd_fw->size);
  733. +
  734. +   size = radeon_bo_size(rdev->uvd.vcpu_bo);
  735. +   size -= rdev->uvd_fw->size;
  736. +
  737. +   ptr = rdev->uvd.cpu_addr;
  738. +   ptr += rdev->uvd_fw->size;
  739. +
  740.     if (rdev->uvd.saved_bo != NULL) {
  741. -       unsigned size = radeon_bo_size(rdev->uvd.vcpu_bo);
  742. -       memcpy(rdev->uvd.cpu_addr, rdev->uvd.saved_bo, size);
  743. +       memcpy(ptr, rdev->uvd.saved_bo, size);
  744.         kfree(rdev->uvd.saved_bo);
  745.         rdev->uvd.saved_bo = NULL;
  746. -   }
  747. +   } else
  748. +       memset(ptr, 0, size);
  749.  
  750.     return 0;
  751.  }
  752. @@ -215,8 +235,8 @@ void radeon_uvd_free_handles(struct radeon_device *rdev, struct drm_file *filp)
  753.  {
  754.     int i, r;
  755.     for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
  756. -       if (rdev->uvd.filp[i] == filp) {
  757. -           uint32_t handle = atomic_read(&rdev->uvd.handles[i]);
  758. +       uint32_t handle = atomic_read(&rdev->uvd.handles[i]);
  759. +       if (handle != 0 && rdev->uvd.filp[i] == filp) {
  760.             struct radeon_fence *fence;
  761.  
  762.             r = radeon_uvd_get_destroy_msg(rdev,
  763. @@ -337,8 +357,10 @@ static int radeon_uvd_cs_msg(struct radeon_cs_parser *p, struct radeon_bo *bo,
  764.     }
  765.  
  766.     r = radeon_bo_kmap(bo, &ptr);
  767. -   if (r)
  768. +   if (r) {
  769. +       DRM_ERROR("Failed mapping the UVD message (%d)!\n", r);
  770.         return r;
  771. +   }
  772.  
  773.     msg = ptr + offset;
  774.  
  775. @@ -364,8 +386,14 @@ static int radeon_uvd_cs_msg(struct radeon_cs_parser *p, struct radeon_bo *bo,
  776.         radeon_bo_kunmap(bo);
  777.         return 0;
  778.     } else {
  779. -       /* it's a create msg, no special handling needed */
  780.         radeon_bo_kunmap(bo);
  781. +
  782. +       if (msg_type != 0) {
  783. +           DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type);
  784. +           return -EINVAL;
  785. +       }
  786. +
  787. +       /* it's a create msg, no special handling needed */
  788.     }
  789.  
  790.     /* create or decode, validate the handle */
  791. @@ -388,7 +416,7 @@ static int radeon_uvd_cs_msg(struct radeon_cs_parser *p, struct radeon_bo *bo,
  792.  
  793.  static int radeon_uvd_cs_reloc(struct radeon_cs_parser *p,
  794.                    int data0, int data1,
  795. -                  unsigned buf_sizes[])
  796. +                  unsigned buf_sizes[], bool *has_msg_cmd)
  797.  {
  798.     struct radeon_cs_chunk *relocs_chunk;
  799.     struct radeon_cs_reloc *reloc;
  800. @@ -417,7 +445,7 @@ static int radeon_uvd_cs_reloc(struct radeon_cs_parser *p,
  801.  
  802.     if (cmd < 0x4) {
  803.         if ((end - start) < buf_sizes[cmd]) {
  804. -           DRM_ERROR("buffer to small (%d / %d)!\n",
  805. +           DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
  806.                   (unsigned)(end - start), buf_sizes[cmd]);
  807.             return -EINVAL;
  808.         }
  809. @@ -442,9 +470,17 @@ static int radeon_uvd_cs_reloc(struct radeon_cs_parser *p,
  810.     }
  811.  
  812.     if (cmd == 0) {
  813. +       if (*has_msg_cmd) {
  814. +           DRM_ERROR("More than one message in a UVD-IB!\n");
  815. +           return -EINVAL;
  816. +       }
  817. +       *has_msg_cmd = true;
  818.         r = radeon_uvd_cs_msg(p, reloc->robj, offset, buf_sizes);
  819.         if (r)
  820.             return r;
  821. +   } else if (!*has_msg_cmd) {
  822. +       DRM_ERROR("Message needed before other commands are send!\n");
  823. +       return -EINVAL;
  824.     }
  825.  
  826.     return 0;
  827. @@ -453,7 +489,8 @@ static int radeon_uvd_cs_reloc(struct radeon_cs_parser *p,
  828.  static int radeon_uvd_cs_reg(struct radeon_cs_parser *p,
  829.                  struct radeon_cs_packet *pkt,
  830.                  int *data0, int *data1,
  831. -                unsigned buf_sizes[])
  832. +                unsigned buf_sizes[],
  833. +                bool *has_msg_cmd)
  834.  {
  835.     int i, r;
  836.  
  837. @@ -467,7 +504,8 @@ static int radeon_uvd_cs_reg(struct radeon_cs_parser *p,
  838.             *data1 = p->idx;
  839.             break;
  840.         case UVD_GPCOM_VCPU_CMD:
  841. -           r = radeon_uvd_cs_reloc(p, *data0, *data1, buf_sizes);
  842. +           r = radeon_uvd_cs_reloc(p, *data0, *data1,
  843. +                       buf_sizes, has_msg_cmd);
  844.             if (r)
  845.                 return r;
  846.             break;
  847. @@ -488,6 +526,9 @@ int radeon_uvd_cs_parse(struct radeon_cs_parser *p)
  848.     struct radeon_cs_packet pkt;
  849.     int r, data0 = 0, data1 = 0;
  850.  
  851. +   /* does the IB has a msg command */
  852. +   bool has_msg_cmd = false;
  853. +
  854.     /* minimum buffer sizes */
  855.     unsigned buf_sizes[] = {
  856.         [0x00000000]    =   2048,
  857. @@ -514,8 +555,8 @@ int radeon_uvd_cs_parse(struct radeon_cs_parser *p)
  858.             return r;
  859.         switch (pkt.type) {
  860.         case RADEON_PACKET_TYPE0:
  861. -           r = radeon_uvd_cs_reg(p, &pkt, &data0,
  862. -                         &data1, buf_sizes);
  863. +           r = radeon_uvd_cs_reg(p, &pkt, &data0, &data1,
  864. +                         buf_sizes, &has_msg_cmd);
  865.             if (r)
  866.                 return r;
  867.             break;
  868. @@ -527,6 +568,12 @@ int radeon_uvd_cs_parse(struct radeon_cs_parser *p)
  869.             return -EINVAL;
  870.         }
  871.     } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
  872. +
  873. +   if (!has_msg_cmd) {
  874. +       DRM_ERROR("UVD-IBs need a msg command!\n");
  875. +       return -EINVAL;
  876. +   }
  877. +
  878.     return 0;
  879.  }
  880.  
  881. diff --git a/drivers/gpu/drm/radeon/rv6xx_dpm.c b/drivers/gpu/drm/radeon/rv6xx_dpm.c
  882. index 363018c..bdd888b 100644
  883. --- a/drivers/gpu/drm/radeon/rv6xx_dpm.c
  884. +++ b/drivers/gpu/drm/radeon/rv6xx_dpm.c
  885. @@ -1944,9 +1944,7 @@ static int rv6xx_parse_power_table(struct radeon_device *rdev)
  886.  
  887.  int rv6xx_dpm_init(struct radeon_device *rdev)
  888.  {
  889. -   int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
  890. -   uint16_t data_offset, size;
  891. -   uint8_t frev, crev;
  892. +   struct radeon_atom_ss ss;
  893.     struct atom_clock_dividers dividers;
  894.     struct rv6xx_power_info *pi;
  895.     int ret;
  896. @@ -1989,16 +1987,18 @@ int rv6xx_dpm_init(struct radeon_device *rdev)
  897.  
  898.     pi->gfx_clock_gating = true;
  899.  
  900. -   if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
  901. -                                   &frev, &crev, &data_offset)) {
  902. -       pi->sclk_ss = true;
  903. -       pi->mclk_ss = true;
  904. +   pi->sclk_ss = radeon_atombios_get_asic_ss_info(rdev, &ss,
  905. +                              ASIC_INTERNAL_ENGINE_SS, 0);
  906. +   pi->mclk_ss = radeon_atombios_get_asic_ss_info(rdev, &ss,
  907. +                              ASIC_INTERNAL_MEMORY_SS, 0);
  908. +
  909. +   /* Disable sclk ss, causes hangs on a lot of systems */
  910. +   pi->sclk_ss = false;
  911. +
  912. +   if (pi->sclk_ss || pi->mclk_ss)
  913.         pi->dynamic_ss = true;
  914. -   } else {
  915. -       pi->sclk_ss = false;
  916. -       pi->mclk_ss = false;
  917. +   else
  918.         pi->dynamic_ss = false;
  919. -   }
  920.  
  921.     pi->dynamic_pcie_gen2 = true;
  922.  
  923. diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
  924. index 30ea14e..bcc68ec 100644
  925. --- a/drivers/gpu/drm/radeon/rv770.c
  926. +++ b/drivers/gpu/drm/radeon/rv770.c
  927. @@ -813,7 +813,7 @@ int rv770_uvd_resume(struct radeon_device *rdev)
  928.  
  929.     /* programm the VCPU memory controller bits 0-27 */
  930.     addr = rdev->uvd.gpu_addr >> 3;
  931. -   size = RADEON_GPU_PAGE_ALIGN(rdev->uvd.fw_size + 4) >> 3;
  932. +   size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 4) >> 3;
  933.     WREG32(UVD_VCPU_CACHE_OFFSET0, addr);
  934.     WREG32(UVD_VCPU_CACHE_SIZE0, size);
  935.  
  936. @@ -1829,6 +1829,8 @@ static int rv770_startup(struct radeon_device *rdev)
  937.     /* enable pcie gen2 link */
  938.     rv770_pcie_gen2_enable(rdev);
  939.  
  940. +   rv770_mc_program(rdev);
  941. +
  942.     if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
  943.         r = r600_init_microcode(rdev);
  944.         if (r) {
  945. @@ -1841,7 +1843,6 @@ static int rv770_startup(struct radeon_device *rdev)
  946.     if (r)
  947.         return r;
  948.  
  949. -   rv770_mc_program(rdev);
  950.     if (rdev->flags & RADEON_IS_AGP) {
  951.         rv770_agp_enable(rdev);
  952.     } else {
  953. @@ -1983,6 +1984,7 @@ int rv770_resume(struct radeon_device *rdev)
  954.  int rv770_suspend(struct radeon_device *rdev)
  955.  {
  956.     r600_audio_fini(rdev);
  957. +   r600_uvd_stop(rdev);
  958.     radeon_uvd_suspend(rdev);
  959.     r700_cp_stop(rdev);
  960.     r600_dma_stop(rdev);
  961. @@ -2098,6 +2100,7 @@ void rv770_fini(struct radeon_device *rdev)
  962.     radeon_ib_pool_fini(rdev);
  963.     radeon_irq_kms_fini(rdev);
  964.     rv770_pcie_gart_fini(rdev);
  965. +   r600_uvd_stop(rdev);
  966.     radeon_uvd_fini(rdev);
  967.     r600_vram_scratch_fini(rdev);
  968.     radeon_gem_fini(rdev);
  969. diff --git a/drivers/gpu/drm/radeon/rv770_dpm.c b/drivers/gpu/drm/radeon/rv770_dpm.c
  970. index 2d34792..094c67a 100644
  971. --- a/drivers/gpu/drm/radeon/rv770_dpm.c
  972. +++ b/drivers/gpu/drm/radeon/rv770_dpm.c
  973. @@ -2319,12 +2319,25 @@ int rv7xx_parse_power_table(struct radeon_device *rdev)
  974.     return 0;
  975.  }
  976.  
  977. +void rv770_get_engine_memory_ss(struct radeon_device *rdev)
  978. +{
  979. +   struct rv7xx_power_info *pi = rv770_get_pi(rdev);
  980. +   struct radeon_atom_ss ss;
  981. +
  982. +   pi->sclk_ss = radeon_atombios_get_asic_ss_info(rdev, &ss,
  983. +                              ASIC_INTERNAL_ENGINE_SS, 0);
  984. +   pi->mclk_ss = radeon_atombios_get_asic_ss_info(rdev, &ss,
  985. +                              ASIC_INTERNAL_MEMORY_SS, 0);
  986. +
  987. +   if (pi->sclk_ss || pi->mclk_ss)
  988. +       pi->dynamic_ss = true;
  989. +   else
  990. +       pi->dynamic_ss = false;
  991. +}
  992. +
  993.  int rv770_dpm_init(struct radeon_device *rdev)
  994.  {
  995.     struct rv7xx_power_info *pi;
  996. -   int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
  997. -   uint16_t data_offset, size;
  998. -   uint8_t frev, crev;
  999.     struct atom_clock_dividers dividers;
  1000.     int ret;
  1001.  
  1002. @@ -2369,16 +2382,7 @@ int rv770_dpm_init(struct radeon_device *rdev)
  1003.     pi->mvdd_control =
  1004.         radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, 0);
  1005.  
  1006. -   if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
  1007. -                                   &frev, &crev, &data_offset)) {
  1008. -       pi->sclk_ss = true;
  1009. -       pi->mclk_ss = true;
  1010. -       pi->dynamic_ss = true;
  1011. -   } else {
  1012. -       pi->sclk_ss = false;
  1013. -       pi->mclk_ss = false;
  1014. -       pi->dynamic_ss = false;
  1015. -   }
  1016. +   rv770_get_engine_memory_ss(rdev);
  1017.  
  1018.     pi->asi = RV770_ASI_DFLT;
  1019.     pi->pasi = RV770_HASI_DFLT;
  1020. @@ -2393,8 +2397,7 @@ int rv770_dpm_init(struct radeon_device *rdev)
  1021.  
  1022.     pi->dynamic_pcie_gen2 = true;
  1023.  
  1024. -   if (pi->gfx_clock_gating &&
  1025. -       (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE))
  1026. +   if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
  1027.         pi->thermal_protection = true;
  1028.     else
  1029.         pi->thermal_protection = false;
  1030. diff --git a/drivers/gpu/drm/radeon/rv770_dpm.h b/drivers/gpu/drm/radeon/rv770_dpm.h
  1031. index 96b1b2a..9244eff 100644
  1032. --- a/drivers/gpu/drm/radeon/rv770_dpm.h
  1033. +++ b/drivers/gpu/drm/radeon/rv770_dpm.h
  1034. @@ -275,6 +275,7 @@ void rv770_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev,
  1035.  void rv770_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev,
  1036.                          struct radeon_ps *new_ps,
  1037.                          struct radeon_ps *old_ps);
  1038. +void rv770_get_engine_memory_ss(struct radeon_device *rdev);
  1039.  
  1040.  /* smc */
  1041.  int rv770_read_smc_soft_register(struct radeon_device *rdev,
  1042. diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
  1043. index 6ca9046..6a2dca4 100644
  1044. --- a/drivers/gpu/drm/radeon/si.c
  1045. +++ b/drivers/gpu/drm/radeon/si.c
  1046. @@ -6418,6 +6418,8 @@ static int si_startup(struct radeon_device *rdev)
  1047.     /* enable aspm */
  1048.     si_program_aspm(rdev);
  1049.  
  1050. +   si_mc_program(rdev);
  1051. +
  1052.     if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||
  1053.         !rdev->rlc_fw || !rdev->mc_fw) {
  1054.         r = si_init_microcode(rdev);
  1055. @@ -6437,7 +6439,6 @@ static int si_startup(struct radeon_device *rdev)
  1056.     if (r)
  1057.         return r;
  1058.  
  1059. -   si_mc_program(rdev);
  1060.     r = si_pcie_gart_enable(rdev);
  1061.     if (r)
  1062.         return r;
  1063. @@ -6621,7 +6622,7 @@ int si_suspend(struct radeon_device *rdev)
  1064.     si_cp_enable(rdev, false);
  1065.     cayman_dma_stop(rdev);
  1066.     if (rdev->has_uvd) {
  1067. -       r600_uvd_rbc_stop(rdev);
  1068. +       r600_uvd_stop(rdev);
  1069.         radeon_uvd_suspend(rdev);
  1070.     }
  1071.     si_irq_suspend(rdev);
  1072. @@ -6763,8 +6764,10 @@ void si_fini(struct radeon_device *rdev)
  1073.     radeon_vm_manager_fini(rdev);
  1074.     radeon_ib_pool_fini(rdev);
  1075.     radeon_irq_kms_fini(rdev);
  1076. -   if (rdev->has_uvd)
  1077. +   if (rdev->has_uvd) {
  1078. +       r600_uvd_stop(rdev);
  1079.         radeon_uvd_fini(rdev);
  1080. +   }
  1081.     si_pcie_gart_fini(rdev);
  1082.     r600_vram_scratch_fini(rdev);
  1083.     radeon_gem_fini(rdev);
  1084. diff --git a/drivers/gpu/drm/radeon/si_dpm.c b/drivers/gpu/drm/radeon/si_dpm.c
  1085. index 4182557..88699e3 100644
  1086. --- a/drivers/gpu/drm/radeon/si_dpm.c
  1087. +++ b/drivers/gpu/drm/radeon/si_dpm.c
  1088. @@ -2903,7 +2903,8 @@ static void si_apply_state_adjust_rules(struct radeon_device *rdev,
  1089.  {
  1090.     struct ni_ps *ps = ni_get_ps(rps);
  1091.     struct radeon_clock_and_voltage_limits *max_limits;
  1092. -   bool disable_mclk_switching;
  1093. +   bool disable_mclk_switching = false;
  1094. +   bool disable_sclk_switching = false;
  1095.     u32 mclk, sclk;
  1096.     u16 vddc, vddci;
  1097.     int i;
  1098. @@ -2911,8 +2912,11 @@ static void si_apply_state_adjust_rules(struct radeon_device *rdev,
  1099.     if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
  1100.         ni_dpm_vblank_too_short(rdev))
  1101.         disable_mclk_switching = true;
  1102. -   else
  1103. -       disable_mclk_switching = false;
  1104. +
  1105. +   if (rps->vclk || rps->dclk) {
  1106. +       disable_mclk_switching = true;
  1107. +       disable_sclk_switching = true;
  1108. +   }
  1109.  
  1110.     if (rdev->pm.dpm.ac_power)
  1111.         max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
  1112. @@ -2940,27 +2944,43 @@ static void si_apply_state_adjust_rules(struct radeon_device *rdev,
  1113.  
  1114.     if (disable_mclk_switching) {
  1115.         mclk  = ps->performance_levels[ps->performance_level_count - 1].mclk;
  1116. -       sclk = ps->performance_levels[0].sclk;
  1117. -       vddc = ps->performance_levels[0].vddc;
  1118.         vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
  1119.     } else {
  1120. -       sclk = ps->performance_levels[0].sclk;
  1121.         mclk = ps->performance_levels[0].mclk;
  1122. -       vddc = ps->performance_levels[0].vddc;
  1123.         vddci = ps->performance_levels[0].vddci;
  1124.     }
  1125.  
  1126. +   if (disable_sclk_switching) {
  1127. +       sclk = ps->performance_levels[ps->performance_level_count - 1].sclk;
  1128. +       vddc = ps->performance_levels[ps->performance_level_count - 1].vddc;
  1129. +   } else {
  1130. +       sclk = ps->performance_levels[0].sclk;
  1131. +       vddc = ps->performance_levels[0].vddc;
  1132. +   }
  1133. +
  1134.     /* adjusted low state */
  1135.     ps->performance_levels[0].sclk = sclk;
  1136.     ps->performance_levels[0].mclk = mclk;
  1137.     ps->performance_levels[0].vddc = vddc;
  1138.     ps->performance_levels[0].vddci = vddci;
  1139.  
  1140. -   for (i = 1; i < ps->performance_level_count; i++) {
  1141. -       if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
  1142. -           ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
  1143. -       if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
  1144. -           ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
  1145. +   if (disable_sclk_switching) {
  1146. +       sclk = ps->performance_levels[0].sclk;
  1147. +       for (i = 1; i < ps->performance_level_count; i++) {
  1148. +           if (sclk < ps->performance_levels[i].sclk)
  1149. +               sclk = ps->performance_levels[i].sclk;
  1150. +       }
  1151. +       for (i = 0; i < ps->performance_level_count; i++) {
  1152. +           ps->performance_levels[i].sclk = sclk;
  1153. +           ps->performance_levels[i].vddc = vddc;
  1154. +       }
  1155. +   } else {
  1156. +       for (i = 1; i < ps->performance_level_count; i++) {
  1157. +           if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
  1158. +               ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
  1159. +           if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
  1160. +               ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
  1161. +       }
  1162.     }
  1163.  
  1164.     if (disable_mclk_switching) {
  1165. @@ -6253,9 +6273,6 @@ int si_dpm_init(struct radeon_device *rdev)
  1166.     struct evergreen_power_info *eg_pi;
  1167.     struct ni_power_info *ni_pi;
  1168.     struct si_power_info *si_pi;
  1169. -   int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
  1170. -   u16 data_offset, size;
  1171. -   u8 frev, crev;
  1172.     struct atom_clock_dividers dividers;
  1173.     int ret;
  1174.     u32 mask;
  1175. @@ -6346,16 +6363,7 @@ int si_dpm_init(struct radeon_device *rdev)
  1176.     si_pi->vddc_phase_shed_control =
  1177.         radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, VOLTAGE_OBJ_PHASE_LUT);
  1178.  
  1179. -   if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
  1180. -                                   &frev, &crev, &data_offset)) {
  1181. -       pi->sclk_ss = true;
  1182. -       pi->mclk_ss = true;
  1183. -       pi->dynamic_ss = true;
  1184. -   } else {
  1185. -       pi->sclk_ss = false;
  1186. -       pi->mclk_ss = false;
  1187. -       pi->dynamic_ss = true;
  1188. -   }
  1189. +   rv770_get_engine_memory_ss(rdev);
  1190.  
  1191.     pi->asi = RV770_ASI_DFLT;
  1192.     pi->pasi = CYPRESS_HASI_DFLT;
  1193. @@ -6366,8 +6374,7 @@ int si_dpm_init(struct radeon_device *rdev)
  1194.     eg_pi->sclk_deep_sleep = true;
  1195.     si_pi->sclk_deep_sleep_above_low = false;
  1196.  
  1197. -   if (pi->gfx_clock_gating &&
  1198. -       (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE))
  1199. +   if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
  1200.         pi->thermal_protection = true;
  1201.     else
  1202.         pi->thermal_protection = false;
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement
Public Pastes
Advertisement
We use cookies for various purposes including analytics. By continuing to use Pastebin, you agree to our use of cookies as described in the Cookies Policy.  OK, I Understand
Not a member of Pastebin yet?
Sign Up, it unlocks many cool features!