LCD Sync Gen Attempt

// Width of counters
    parameter WIDTH = 11;

    // Horizontal timing parameters
    parameter H_VISIBLE = 800;
    parameter H_FRONT_PORCH = 210;
    parameter H_SYNC = 30;
    parameter H_BACK_PORCH = 16;

    // Vertical timing parameters
    parameter V_VISIBLE = 480;
    parameter V_FRONT_PORCH = 22;
    parameter V_SYNC = 13;
    parameter V_BACK_PORCH = 10;

     wire hblank;
     wire vblank;

    // Instantiate the synchronize generator
    sync_gen #(
        .WIDTH(WIDTH),
        .H_VISIBLE(H_VISIBLE),
        .H_FRONT_PORCH(H_FRONT_PORCH),
        .H_SYNC(H_SYNC),
        .H_BACK_PORCH(H_BACK_PORCH),
        .V_VISIBLE(V_VISIBLE),
        .V_FRONT_PORCH(V_FRONT_PORCH),
        .V_SYNC(V_SYNC),
        .V_BACK_PORCH(V_BACK_PORCH)
    ) sync_gen_0 (
        .clk(clock_to_lcd),
        .rst(~KEY[0]),
        .hsync(hsync),
        .vsync(vsync),
        .hblank(hblank),
        .vblank(vblank),
    );

And then separately

module sync_gen
#(
    // Width of counters
    parameter WIDTH,

    // Horizontal timing parameters
    parameter H_VISIBLE,
    parameter H_FRONT_PORCH,
    parameter H_SYNC,
    parameter H_BACK_PORCH,

    // Vertical timing parameters
    parameter V_VISIBLE,
    parameter V_FRONT_PORCH,
    parameter V_SYNC,
    parameter V_BACK_PORCH
)
(
    input logic clk, rst,
    output logic hsync, vsync,
    output logic hblank, vblank

);

    // The counters used to determine when to pulse the sync signals
    logic [WIDTH-1:0] pix_x, pix_y;


    // Parameters that determine the maximum line and frame sizes
    localparam [WIDTH-1:0] H_WHOLE_LINE = H_VISIBLE + H_FRONT_PORCH + H_SYNC + H_BACK_PORCH;
    localparam [WIDTH-1:0] V_WHOLE_FRAME = V_VISIBLE + V_FRONT_PORCH + V_SYNC + V_BACK_PORCH;

    // Determines when to turn on sync (active low) and blank signals
    assign hsync = !(pix_x >= (H_VISIBLE + H_FRONT_PORCH) && pix_x < (H_VISIBLE + H_FRONT_PORCH + H_SYNC));
    assign vsync = !(pix_y >= (V_VISIBLE + V_FRONT_PORCH) && pix_y < (V_VISIBLE + V_FRONT_PORCH + V_SYNC));

    assign hblank = (pix_x >= (H_VISIBLE) && pix_x < (H_WHOLE_LINE));
    assign vblank = (pix_y >= (V_VISIBLE) && pix_y < (V_WHOLE_FRAME));

    // Increment the counters
    always_ff @(posedge clk) begin
        begin
            if(rst) begin
                pix_x <= '0;
                pix_y <= '0;
            end else if (pix_x < H_WHOLE_LINE - 1) begin   // End of pixel, go to next pixel
                pix_x <= pix_x + 1'b1;
                pix_y <= pix_y;
            end else begin  // End of line, go to next line
                pix_x <= '0;
                if(pix_y < V_WHOLE_FRAME - 1)
                    pix_y <= pix_y + 1'b1;
                else    // End of frame, go back to top
                    pix_y <= '0;
            end
        end
    end

    endmodule