library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity rej is

generic (N:integer:=8);

port

(
  clk    : in  std_logic;
  reset  : in  std_logic;
  output : out std_logic_vector(11 downto 0);
  result : in std_logic_vector(N-1 downto 0);
  F : in std_logic_vector(3 downto 0)
  );
end rej;


architecture Rejestr of rej is

signal slowo : std_logic_vector(11 downto 0);
type reg is array(N-1 downto 0) of std_logic_vector(11 downto 0); -- reg jest tablica 8 slow
signal licznik : integer range 0 to 7;
signal tablica: reg;


begin

slowo <= result & F;

process(clk,reset)
begin
  if (reset='1') then

    licznik <= 0;


  elsif (clk'event and clk ='1') then

    if (licznik <7) then
    tablica(licznik) <= slowo;
    licznik <= licznik + 1;

    else
    licznik <= 0;
    tablica(licznik) <= slowo;

    end if;


  end if;

 output <= slowo;

 end process;


 end Rejestr;