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Atombios.h VRAM

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  1. /*************** ATOM Memory Related Data Structure ***********************/
  2. typedef struct _ATOM_MEMORY_VENDOR_BLOCK{
  3. UCHAR ucMemoryType;
  4. UCHAR ucMemoryVendor;
  5. UCHAR ucAdjMCId;
  6. UCHAR ucDynClkId;
  7. ULONG ulDllResetClkRange;
  8. }ATOM_MEMORY_VENDOR_BLOCK;
  9.  
  10.  
  11. typedef struct _ATOM_MEMORY_SETTING_ID_CONFIG{
  12. #if ATOM_BIG_ENDIAN
  13. ULONG ucMemBlkId:8;
  14. ULONG ulMemClockRange:24;
  15. #else
  16. ULONG ulMemClockRange:24;
  17. ULONG ucMemBlkId:8;
  18. #endif
  19. }ATOM_MEMORY_SETTING_ID_CONFIG;
  20.  
  21. typedef union _ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS
  22. {
  23. ATOM_MEMORY_SETTING_ID_CONFIG slAccess;
  24. ULONG ulAccess;
  25. }ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS;
  26.  
  27.  
  28. typedef struct _ATOM_MEMORY_SETTING_DATA_BLOCK{
  29. ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS ulMemoryID;
  30. ULONG aulMemData[1];
  31. }ATOM_MEMORY_SETTING_DATA_BLOCK;
  32.  
  33.  
  34. typedef struct _ATOM_INIT_REG_INDEX_FORMAT{
  35. USHORT usRegIndex; // MC register index
  36. UCHAR ucPreRegDataLength; // offset in ATOM_INIT_REG_DATA_BLOCK.saRegDataBuf
  37. }ATOM_INIT_REG_INDEX_FORMAT;
  38.  
  39.  
  40. typedef struct _ATOM_INIT_REG_BLOCK{
  41. USHORT usRegIndexTblSize; //size of asRegIndexBuf
  42. USHORT usRegDataBlkSize; //size of ATOM_MEMORY_SETTING_DATA_BLOCK
  43. ATOM_INIT_REG_INDEX_FORMAT asRegIndexBuf[1];
  44. ATOM_MEMORY_SETTING_DATA_BLOCK asRegDataBuf[1];
  45. }ATOM_INIT_REG_BLOCK;
  46.  
  47. #define END_OF_REG_INDEX_BLOCK 0x0ffff
  48. #define END_OF_REG_DATA_BLOCK 0x00000000
  49. #define ATOM_INIT_REG_MASK_FLAG 0x80 //Not used in BIOS
  50. #define CLOCK_RANGE_HIGHEST 0x00ffffff
  51.  
  52. #define VALUE_DWORD SIZEOF ULONG
  53. #define VALUE_SAME_AS_ABOVE 0
  54. #define VALUE_MASK_DWORD 0x84
  55.  
  56. #define INDEX_ACCESS_RANGE_BEGIN (VALUE_DWORD + 1)
  57. #define INDEX_ACCESS_RANGE_END (INDEX_ACCESS_RANGE_BEGIN + 1)
  58. #define VALUE_INDEX_ACCESS_SINGLE (INDEX_ACCESS_RANGE_END + 1)
  59. //#define ACCESS_MCIODEBUGIND 0x40 //defined in BIOS code
  60. #define ACCESS_PLACEHOLDER 0x80
  61.  
  62. typedef struct _ATOM_MC_INIT_PARAM_TABLE
  63. {
  64. ATOM_COMMON_TABLE_HEADER sHeader;
  65. USHORT usAdjustARB_SEQDataOffset;
  66. USHORT usMCInitMemTypeTblOffset;
  67. USHORT usMCInitCommonTblOffset;
  68. USHORT usMCInitPowerDownTblOffset;
  69. ULONG ulARB_SEQDataBuf[32];
  70. ATOM_INIT_REG_BLOCK asMCInitMemType;
  71. ATOM_INIT_REG_BLOCK asMCInitCommon;
  72. }ATOM_MC_INIT_PARAM_TABLE;
  73.  
  74.  
  75. #define _4Mx16 0x2
  76. #define _4Mx32 0x3
  77. #define _8Mx16 0x12
  78. #define _8Mx32 0x13
  79. #define _16Mx16 0x22
  80. #define _16Mx32 0x23
  81. #define _32Mx16 0x32
  82. #define _32Mx32 0x33
  83. #define _64Mx8 0x41
  84. #define _64Mx16 0x42
  85. #define _64Mx32 0x43
  86. #define _128Mx8 0x51
  87. #define _128Mx16 0x52
  88. #define _128Mx32 0x53
  89. #define _256Mx8 0x61
  90. #define _256Mx16 0x62
  91. #define _512Mx8 0x71
  92.  
  93. #define SAMSUNG 0x1
  94. #define INFINEON 0x2
  95. #define ELPIDA 0x3
  96. #define ETRON 0x4
  97. #define NANYA 0x5
  98. #define HYNIX 0x6
  99. #define MOSEL 0x7
  100. #define WINBOND 0x8
  101. #define ESMT 0x9
  102. #define MICRON 0xF
  103.  
  104. #define QIMONDA INFINEON
  105. #define PROMOS MOSEL
  106. #define KRETON INFINEON
  107. #define ELIXIR NANYA
  108. #define MEZZA ELPIDA
  109.  
  110.  
  111. /////////////Support for GDDR5 MC uCode to reside in upper 64K of ROM/////////////
  112.  
  113. #define UCODE_ROM_START_ADDRESS 0x1b800
  114. #define UCODE_SIGNATURE 0x4375434d // 'MCuC' - MC uCode
  115.  
  116. //uCode block header for reference
  117.  
  118. typedef struct _MCuCodeHeader
  119. {
  120. ULONG ulSignature;
  121. UCHAR ucRevision;
  122. UCHAR ucChecksum;
  123. UCHAR ucReserved1;
  124. UCHAR ucReserved2;
  125. USHORT usParametersLength;
  126. USHORT usUCodeLength;
  127. USHORT usReserved1;
  128. USHORT usReserved2;
  129. } MCuCodeHeader;
  130.  
  131. //////////////////////////////////////////////////////////////////////////////////
  132.  
  133. #define ATOM_MAX_NUMBER_OF_VRAM_MODULE 16
  134.  
  135. #define ATOM_VRAM_MODULE_MEMORY_VENDOR_ID_MASK 0xF
  136. typedef struct _ATOM_VRAM_MODULE_V1
  137. {
  138. ULONG ulReserved;
  139. USHORT usEMRSValue;
  140. USHORT usMRSValue;
  141. USHORT usReserved;
  142. UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
  143. UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] reserved;
  144. UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender
  145. UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32...
  146. UCHAR ucRow; // Number of Row,in power of 2;
  147. UCHAR ucColumn; // Number of Column,in power of 2;
  148. UCHAR ucBank; // Nunber of Bank;
  149. UCHAR ucRank; // Number of Rank, in power of 2
  150. UCHAR ucChannelNum; // Number of channel;
  151. UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2
  152. UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
  153. UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
  154. UCHAR ucReserved[2];
  155. }ATOM_VRAM_MODULE_V1;
  156.  
  157.  
  158. typedef struct _ATOM_VRAM_MODULE_V2
  159. {
  160. ULONG ulReserved;
  161. ULONG ulFlags; // To enable/disable functionalities based on memory type
  162. ULONG ulEngineClock; // Override of default engine clock for particular memory type
  163. ULONG ulMemoryClock; // Override of default memory clock for particular memory type
  164. USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type
  165. USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type
  166. USHORT usEMRSValue;
  167. USHORT usMRSValue;
  168. USHORT usReserved;
  169. UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
  170. UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now;
  171. UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed
  172. UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32...
  173. UCHAR ucRow; // Number of Row,in power of 2;
  174. UCHAR ucColumn; // Number of Column,in power of 2;
  175. UCHAR ucBank; // Nunber of Bank;
  176. UCHAR ucRank; // Number of Rank, in power of 2
  177. UCHAR ucChannelNum; // Number of channel;
  178. UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2
  179. UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
  180. UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
  181. UCHAR ucRefreshRateFactor;
  182. UCHAR ucReserved[3];
  183. }ATOM_VRAM_MODULE_V2;
  184.  
  185.  
  186. typedef struct _ATOM_MEMORY_TIMING_FORMAT
  187. {
  188. ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing
  189. union{
  190. USHORT usMRS; // mode register
  191. USHORT usDDR3_MR0;
  192. };
  193. union{
  194. USHORT usEMRS; // extended mode register
  195. USHORT usDDR3_MR1;
  196. };
  197. UCHAR ucCL; // CAS latency
  198. UCHAR ucWL; // WRITE Latency
  199. UCHAR uctRAS; // tRAS
  200. UCHAR uctRC; // tRC
  201. UCHAR uctRFC; // tRFC
  202. UCHAR uctRCDR; // tRCDR
  203. UCHAR uctRCDW; // tRCDW
  204. UCHAR uctRP; // tRP
  205. UCHAR uctRRD; // tRRD
  206. UCHAR uctWR; // tWR
  207. UCHAR uctWTR; // tWTR
  208. UCHAR uctPDIX; // tPDIX
  209. UCHAR uctFAW; // tFAW
  210. UCHAR uctAOND; // tAOND
  211. union
  212. {
  213. struct {
  214. UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon
  215. UCHAR ucReserved;
  216. };
  217. USHORT usDDR3_MR2;
  218. };
  219. }ATOM_MEMORY_TIMING_FORMAT;
  220.  
  221.  
  222. typedef struct _ATOM_MEMORY_TIMING_FORMAT_V1
  223. {
  224. ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing
  225. USHORT usMRS; // mode register
  226. USHORT usEMRS; // extended mode register
  227. UCHAR ucCL; // CAS latency
  228. UCHAR ucWL; // WRITE Latency
  229. UCHAR uctRAS; // tRAS
  230. UCHAR uctRC; // tRC
  231. UCHAR uctRFC; // tRFC
  232. UCHAR uctRCDR; // tRCDR
  233. UCHAR uctRCDW; // tRCDW
  234. UCHAR uctRP; // tRP
  235. UCHAR uctRRD; // tRRD
  236. UCHAR uctWR; // tWR
  237. UCHAR uctWTR; // tWTR
  238. UCHAR uctPDIX; // tPDIX
  239. UCHAR uctFAW; // tFAW
  240. UCHAR uctAOND; // tAOND
  241. UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon
  242. ////////////////////////////////////GDDR parameters///////////////////////////////////
  243. UCHAR uctCCDL; //
  244. UCHAR uctCRCRL; //
  245. UCHAR uctCRCWL; //
  246. UCHAR uctCKE; //
  247. UCHAR uctCKRSE; //
  248. UCHAR uctCKRSX; //
  249. UCHAR uctFAW32; //
  250. UCHAR ucMR5lo; //
  251. UCHAR ucMR5hi; //
  252. UCHAR ucTerminator;
  253. }ATOM_MEMORY_TIMING_FORMAT_V1;
  254.  
  255. typedef struct _ATOM_MEMORY_TIMING_FORMAT_V2
  256. {
  257. ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing
  258. USHORT usMRS; // mode register
  259. USHORT usEMRS; // extended mode register
  260. UCHAR ucCL; // CAS latency
  261. UCHAR ucWL; // WRITE Latency
  262. UCHAR uctRAS; // tRAS
  263. UCHAR uctRC; // tRC
  264. UCHAR uctRFC; // tRFC
  265. UCHAR uctRCDR; // tRCDR
  266. UCHAR uctRCDW; // tRCDW
  267. UCHAR uctRP; // tRP
  268. UCHAR uctRRD; // tRRD
  269. UCHAR uctWR; // tWR
  270. UCHAR uctWTR; // tWTR
  271. UCHAR uctPDIX; // tPDIX
  272. UCHAR uctFAW; // tFAW
  273. UCHAR uctAOND; // tAOND
  274. UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon
  275. ////////////////////////////////////GDDR parameters///////////////////////////////////
  276. UCHAR uctCCDL; //
  277. UCHAR uctCRCRL; //
  278. UCHAR uctCRCWL; //
  279. UCHAR uctCKE; //
  280. UCHAR uctCKRSE; //
  281. UCHAR uctCKRSX; //
  282. UCHAR uctFAW32; //
  283. UCHAR ucMR4lo; //
  284. UCHAR ucMR4hi; //
  285. UCHAR ucMR5lo; //
  286. UCHAR ucMR5hi; //
  287. UCHAR ucTerminator;
  288. UCHAR ucReserved;
  289. }ATOM_MEMORY_TIMING_FORMAT_V2;
  290.  
  291. typedef struct _ATOM_MEMORY_FORMAT
  292. {
  293. ULONG ulDllDisClock; // memory DLL will be disable when target memory clock is below this clock
  294. union{
  295. USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type
  296. USHORT usDDR3_Reserved; // Not used for DDR3 memory
  297. };
  298. union{
  299. USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type
  300. USHORT usDDR3_MR3; // Used for DDR3 memory
  301. };
  302. UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now;
  303. UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed
  304. UCHAR ucRow; // Number of Row,in power of 2;
  305. UCHAR ucColumn; // Number of Column,in power of 2;
  306. UCHAR ucBank; // Nunber of Bank;
  307. UCHAR ucRank; // Number of Rank, in power of 2
  308. UCHAR ucBurstSize; // burst size, 0= burst size=4 1= burst size=8
  309. UCHAR ucDllDisBit; // position of DLL Enable/Disable bit in EMRS ( Extended Mode Register )
  310. UCHAR ucRefreshRateFactor; // memory refresh rate in unit of ms
  311. UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
  312. UCHAR ucPreamble; //[7:4] Write Preamble, [3:0] Read Preamble
  313. UCHAR ucMemAttrib; // Memory Device Addribute, like RDBI/WDBI etc
  314. ATOM_MEMORY_TIMING_FORMAT asMemTiming[5]; //Memory Timing block sort from lower clock to higher clock
  315. }ATOM_MEMORY_FORMAT;
  316.  
  317.  
  318. typedef struct _ATOM_VRAM_MODULE_V3
  319. {
  320. ULONG ulChannelMapCfg; // board dependent paramenter:Channel combination
  321. USHORT usSize; // size of ATOM_VRAM_MODULE_V3
  322. USHORT usDefaultMVDDQ; // board dependent parameter:Default Memory Core Voltage
  323. USHORT usDefaultMVDDC; // board dependent parameter:Default Memory IO Voltage
  324. UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
  325. UCHAR ucChannelNum; // board dependent parameter:Number of channel;
  326. UCHAR ucChannelSize; // board dependent parameter:32bit or 64bit
  327. UCHAR ucVREFI; // board dependnt parameter: EXT or INT +160mv to -140mv
  328. UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
  329. UCHAR ucFlag; // To enable/disable functionalities based on memory type
  330. ATOM_MEMORY_FORMAT asMemory; // describ all of video memory parameters from memory spec
  331. }ATOM_VRAM_MODULE_V3;
  332.  
  333.  
  334. //ATOM_VRAM_MODULE_V3.ucNPL_RT
  335. #define NPL_RT_MASK 0x0f
  336. #define BATTERY_ODT_MASK 0xc0
  337.  
  338. #define ATOM_VRAM_MODULE ATOM_VRAM_MODULE_V3
  339.  
  340. typedef struct _ATOM_VRAM_MODULE_V4
  341. {
  342. ULONG ulChannelMapCfg; // board dependent parameter: Channel combination
  343. USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE
  344. USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
  345. // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
  346. USHORT usReserved;
  347. UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
  348. UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
  349. UCHAR ucChannelNum; // Number of channels present in this module config
  350. UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
  351. UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
  352. UCHAR ucFlag; // To enable/disable functionalities based on memory type
  353. UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8
  354. UCHAR ucVREFI; // board dependent parameter
  355. UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
  356. UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
  357. UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
  358. // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
  359. UCHAR ucReserved[3];
  360.  
  361. //compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level
  362. union{
  363. USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type
  364. USHORT usDDR3_Reserved;
  365. };
  366. union{
  367. USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type
  368. USHORT usDDR3_MR3; // Used for DDR3 memory
  369. };
  370. UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed
  371. UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
  372. UCHAR ucReserved2[2];
  373. ATOM_MEMORY_TIMING_FORMAT asMemTiming[5];//Memory Timing block sort from lower clock to higher clock
  374. }ATOM_VRAM_MODULE_V4;
  375.  
  376. #define VRAM_MODULE_V4_MISC_RANK_MASK 0x3
  377. #define VRAM_MODULE_V4_MISC_DUAL_RANK 0x1
  378. #define VRAM_MODULE_V4_MISC_BL_MASK 0x4
  379. #define VRAM_MODULE_V4_MISC_BL8 0x4
  380. #define VRAM_MODULE_V4_MISC_DUAL_CS 0x10
  381.  
  382. typedef struct _ATOM_VRAM_MODULE_V5
  383. {
  384. ULONG ulChannelMapCfg; // board dependent parameter: Channel combination
  385. USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE
  386. USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
  387. // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
  388. USHORT usReserved;
  389. UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
  390. UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
  391. UCHAR ucChannelNum; // Number of channels present in this module config
  392. UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
  393. UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
  394. UCHAR ucFlag; // To enable/disable functionalities based on memory type
  395. UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8
  396. UCHAR ucVREFI; // board dependent parameter
  397. UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
  398. UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
  399. UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
  400. // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
  401. UCHAR ucReserved[3];
  402.  
  403. //compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level
  404. USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type
  405. USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type
  406. UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed
  407. UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
  408. UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth
  409. UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
  410. ATOM_MEMORY_TIMING_FORMAT_V1 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock
  411. }ATOM_VRAM_MODULE_V5;
  412.  
  413. typedef struct _ATOM_VRAM_MODULE_V6
  414. {
  415. ULONG ulChannelMapCfg; // board dependent parameter: Channel combination
  416. USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE
  417. USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
  418. // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
  419. USHORT usReserved;
  420. UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
  421. UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
  422. UCHAR ucChannelNum; // Number of channels present in this module config
  423. UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
  424. UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
  425. UCHAR ucFlag; // To enable/disable functionalities based on memory type
  426. UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8
  427. UCHAR ucVREFI; // board dependent parameter
  428. UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
  429. UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
  430. UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
  431. // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
  432. UCHAR ucReserved[3];
  433.  
  434. //compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level
  435. USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type
  436. USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type
  437. UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed
  438. UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
  439. UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth
  440. UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
  441. ATOM_MEMORY_TIMING_FORMAT_V2 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock
  442. }ATOM_VRAM_MODULE_V6;
  443.  
  444. typedef struct _ATOM_VRAM_MODULE_V7
  445. {
  446. // Design Specific Values
  447. ULONG ulChannelMapCfg; // mmMC_SHARED_CHREMAP
  448. USHORT usModuleSize; // Size of ATOM_VRAM_MODULE_V7
  449. USHORT usPrivateReserved; // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
  450. USHORT usEnableChannels; // bit vector which indicate which channels are enabled
  451. UCHAR ucExtMemoryID; // Current memory module ID
  452. UCHAR ucMemoryType; // MEM_TYPE_DDR2/DDR3/GDDR3/GDDR5
  453. UCHAR ucChannelNum; // Number of mem. channels supported in this module
  454. UCHAR ucChannelWidth; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
  455. UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
  456. UCHAR ucReserve; // Former container for Mx_FLAGS like DBI_AC_MODE_ENABLE_ASIC for GDDR4. Not used now.
  457. UCHAR ucMisc; // RANK_OF_THISMEMORY etc.
  458. UCHAR ucVREFI; // Not used.
  459. UCHAR ucNPL_RT; // Round trip delay (MC_SEQ_CAS_TIMING [28:24]:TCL=CL+NPL_RT-2). Always 2.
  460. UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
  461. UCHAR ucMemorySize; // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
  462. USHORT usSEQSettingOffset;
  463. UCHAR ucReserved;
  464. // Memory Module specific values
  465. USHORT usEMRS2Value; // EMRS2/MR2 Value.
  466. USHORT usEMRS3Value; // EMRS3/MR3 Value.
  467. UCHAR ucMemoryVenderID; // [7:4] Revision, [3:0] Vendor code
  468. UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
  469. UCHAR ucFIFODepth; // FIFO depth can be detected during vendor detection, here is hardcoded per memory
  470. UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
  471. char strMemPNString[20]; // part number end with '0'.
  472. }ATOM_VRAM_MODULE_V7;
  473.  
  474. typedef struct _ATOM_VRAM_INFO_V2
  475. {
  476. ATOM_COMMON_TABLE_HEADER sHeader;
  477. UCHAR ucNumOfVRAMModule;
  478. ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
  479. }ATOM_VRAM_INFO_V2;
  480.  
  481. typedef struct _ATOM_VRAM_INFO_V3
  482. {
  483. ATOM_COMMON_TABLE_HEADER sHeader;
  484. USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting
  485. USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting
  486. USHORT usRerseved;
  487. UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+terminator
  488. UCHAR ucNumOfVRAMModule;
  489. ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
  490. ATOM_INIT_REG_BLOCK asMemPatch; // for allocation
  491. // ATOM_INIT_REG_BLOCK aMemAdjust;
  492. }ATOM_VRAM_INFO_V3;
  493.  
  494. #define ATOM_VRAM_INFO_LAST ATOM_VRAM_INFO_V3
  495.  
  496. typedef struct _ATOM_VRAM_INFO_V4
  497. {
  498. ATOM_COMMON_TABLE_HEADER sHeader;
  499. USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting
  500. USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting
  501. USHORT usRerseved;
  502. UCHAR ucMemDQ7_0ByteRemap; // DQ line byte remap, =0: Memory Data line BYTE0, =1: BYTE1, =2: BYTE2, =3: BYTE3
  503. ULONG ulMemDQ7_0BitRemap; // each DQ line ( 7~0) use 3bits, like: DQ0=Bit[2:0], DQ1:[5:3], ... DQ7:[23:21]
  504. UCHAR ucReservde[4];
  505. UCHAR ucNumOfVRAMModule;
  506. ATOM_VRAM_MODULE_V4 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
  507. ATOM_INIT_REG_BLOCK asMemPatch; // for allocation
  508. // ATOM_INIT_REG_BLOCK aMemAdjust;
  509. }ATOM_VRAM_INFO_V4;
  510.  
  511. typedef struct _ATOM_VRAM_INFO_HEADER_V2_1
  512. {
  513. ATOM_COMMON_TABLE_HEADER sHeader;
  514. USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting
  515. USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting
  516. USHORT usPerBytePresetOffset; // offset of ATOM_INIT_REG_BLOCK structure for Per Byte Offset Preset Settings
  517. USHORT usReserved[3];
  518. UCHAR ucNumOfVRAMModule; // indicate number of VRAM module
  519. UCHAR ucMemoryClkPatchTblVer; // version of memory AC timing register list
  520. UCHAR ucVramModuleVer; // indicate ATOM_VRAM_MODUE version
  521. UCHAR ucReserved;
  522. ATOM_VRAM_MODULE_V7 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
  523. }ATOM_VRAM_INFO_HEADER_V2_1;
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