-- ---------------------------------------------------------------------------
--                      8 - Bit General Purpose NVL Computer
-- ---------------------------------------------------------------------------
-- Title        : Arithmetical and Logical Unit
--              :
-- Purpose      : This is the ALU of the computer. It performs basic mathmematical
--              : operations, such as addition or multiplication.
--              :
-- Note         : Operation to be performed is selected by Function Select:
--              : FS = 0 --> Addition
--              : FS = 1 --> Bitwise AND
--              : FS = 2 --> Bitwise OR
--              : FS = 3 --> Left logical shift
--              : FS = 4 --> Right logical shift
--              : FS = 5 --> Multiplication
--              :
-- ---------------------------------------------------------------------------
-- Version      : 1.0
-- Date         : 21 October 2016
-- ---------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity alu is
    port
    (
        cs   : in  std_logic;                     -- Chip select
        fs   : in  std_logic_vector(2 downto 0);  -- Function select
        ms   : in  std_logic;                     -- Multiply select
        opr1 : in  std_logic_vector(7 downto 0);  -- First operand input
        opr2 : in  std_logic_vector(7 downto 0);  -- Second operand input
        y    : out std_logic_vector(7 downto 0);  -- Computation result
        flg  : out std_logic_vector(2 downto 0)   -- Carry and zero flag
    );
end entity;

architecture arch of alu is
 signal y_c : std_logic_vector(8 downto 0);   -- Temp output with MSB carry, only add and multiply affects the carry flag.
 --signal y_m : std_logic_vector(15 downto 0);  -- Result of multiplication, whenever result exceeds 8 bits, the carry flag is set.

    begin
        process(cs, fs, ms, opr1, opr2, y_c(8))
        variable x : integer range 0 to 7;
        variable y_m : std_logic_vector(15 downto 0);
        -- Result of multiplication, the lower 7 bits is stored in A and upper 7 bits in memory (MPH = 0x3F0).

            begin
            if(cs = '1') then
                case fs is
                    when "000" =>
                        y_c <= std_logic_vector(unsigned('0' & opr1) + unsigned('0' & opr2));
                    when "001" =>
                        y_c <= (y_c(8) & opr1) and (y_c(8) & opr2);
                    when "010" =>
                        y_c <= (y_c(8) & opr1) or (y_c(8) & opr2);
                    when "011" =>
                        -- new encoding scheme accepted : XXXX XXXD DDZ0 X100
                        x := to_integer(unsigned(opr2(7 downto 5)));
                        y_c(7 downto x) <= opr1(7 - x downto 0);            -- wont't detect carry
                        y_c(x - 1 downto 0) <= (others => '0');
                    when "100" =>
                        -- new encoding scheme accepted : XXXX XXXD DDZ1 X100
                        x := to_integer(unsigned(opr2(7 downto 5)));
                        y_c(7 - x downto 0) <= opr1(7 downto 0 + x);
                        y_c(7 downto 7 - x) <= (others => '0');
                    when "101" =>
                        if(ms = '0') then
                            y_m := std_logic_vector(unsigned(opr1) * unsigned(opr2));
                            y_c(7 downto 0) <= y_m(7 downto 0);
                            -- output lower 8 bits
                        else
                            y_c(7 downto 0) <= y_m(15 downto 8);
                            -- output higher 8 bits
                        end if;
                    when others =>
                    -- ADD otherwise
                    y_c <= std_logic_vector(unsigned('0' & opr1) + unsigned('0' & opr2));
                end case;
            else
                y_c <= (others => '0');
                y_m := (others => '0');
                x   := 0;
            end if;
            end process;
    -- Unregistered computatation output
    y <= y_c(7 downto 0);
    -- Unregistered Carry and Zero output
    flg(0) <= y_c(8);
    flg(1) <= (y_c(7) or y_c(6) or y_c(5) or y_c(4) or y_c(3) or y_c(2) or y_c(1) or y_c(0));
end architecture;