shifter

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity DIVISOR is
    Port (
        CLK : in std_logic;
        D : in   std_logic_vector (3 downto 0);
        A : in   std_logic_vector (7 downto 0);
        S : out  std_logic_vector (7 downto 0));
end DIVISOR;

architecture comportamento of DIVISOR is
begin
    process(CLK)
    begin
        if CLK'EVENT AND CLK = '1' THEN
            if (D="0010") then
                S <= "0" & A(7 downto 1);
            elsif (D="0100") then
                S <= "00" & A(7 downto 2);
            elsif (D="1000") then
                S <= "000" & A(7 downto 3);
            end if;
        end if;
    end process;
end comportamento;