from migen import *
from misoc.interconnect import stream

_SD_CMD_WAIT = [
        ("ticks" , 8)
    ]

class sd_cmd_wait(Module):
    def __init__(self, pads):
        self.sd_clk = Signal()
        started = Signal()
        cnt = Signal(8)

        self.sink = stream.Endpoint(_SD_CMD_WAIT)

        self.comb += [
            If(started,
               self.sd_clk.eq(~self.sd_clk #ClockSignal()
               )).Else(
                   self.sd_clk.eq(0)
               ),
        ]

        self.sync += [
            self.sink.ack.eq(0),

            If(self.sink.stb & ~started & ~self.sink.ack,
               started.eq(1),
               cnt.eq(self.sink.ticks),

            ),

            If(started,
               If(cnt==0,
                   self.sink.ack.eq(1),
                   cnt.eq(0),
                   started.eq(0)
               ).Else(
                   cnt.eq(cnt - 1)
               )
            )

        ]



class _TestPads:
    def __init__(self):
        self.sd_clk = Signal()
        self.cmd_oe = Signal()
        self.cmd_o = Signal()
        self.cmd_i = Signal()
        self.dat_oe = Signal()
        self.dat_o = Signal(4)
        self.dat_i = Signal(4)


class use_sd_cmd_wait(Module):
    def __init__(self):
        self.pads = pads = _TestPads()
        self.submodules.cmd_wait = sd_cmd_wait(pads)
        self.comb += pads.sd_clk.eq(self.cmd_wait.sd_clk)

        self.source = stream.Endpoint(_SD_CMD_WAIT)
        self.comb += self.source.connect(self.cmd_wait.sink)
        self.comb += self.source.ticks.eq(74)

        self.sync += self.source.stb.eq(1)
        self.sync += self.source.ack.eq(0)

def _test_gen(dut):
    for i in range(200):
        print( (yield dut.pads.sd_clk))
        yield




if __name__ == "__main__":

    dut = use_sd_cmd_wait()
    run_simulation(dut, _test_gen(dut), vcd_name="sd_cmd_wait.vcd")