library ieee;
use ieee.std_logic_1164.all;

entity cmp8 is
        port (clk : in std_logic;
          a: in std_logic_vector (7 downto 0); -- первое число
              b: in std_logic_vector (7 downto 0); -- второе число
              e: out std_logic;  -- equal
              g: out std_logic;  -- greater
              l: out std_logic); -- less
end cmp8;

architecture struct of cmp8 is

        component cmp2 is
                port (clk : in std_logic;
              a1, a0: in std_logic;
                      b1, b0: in std_logic;
                      ext_e, ext_g, ext_l: in std_logic;
                      e, g, l: out std_logic);
        end component;

        signal comp1_e, comp1_g, comp1_l: std_logic;
        signal comp2_e, comp2_g, comp2_l: std_logic;
        signal comp3_e, comp3_g, comp3_l: std_logic;
begin
        comp3: cmp2 port map (
    clk => clk,
        a(7), a(6), b(7), b(6),
        ext_e => '1',
        ext_g => '0',
        ext_l => '0',
        e => comp3_e,
        g => comp3_g,
        l => comp3_l);

        comp2: cmp2 port map (
        clk => clk,
    a(5), a(4), b(5), b(4),
        ext_e => comp3_e,
        ext_g => comp3_g,
        ext_l => comp3_l,
        e => comp2_e,
        g => comp2_g,
        l => comp2_l);

        comp1: cmp2 port map (
        clk => clk,
    a(3), a(2), b(3), b(2),
        ext_e => comp2_e,
        ext_g => comp2_g,
        ext_l => comp2_l,
        e => comp1_e,
        g => comp1_g,
        l => comp1_l);

        comp0: cmp2 port map (
        clk => clk,
    a(1), a(0), b(1), b(0),
        ext_e => comp1_e,
        ext_g => comp1_g,
        ext_l => comp1_l,
        e => e,
        g => g,
        l => l);

end struct;