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  1. static struct mt9p111_reg postInitTest[] = {
  2.    
  3.     /* for 16 MHz input, VCO=720 MHz */
  4.     {MT9P111_REG16, 0x0010, 0x012D},    /* PLL Dividers = 301 */
  5.     {MT9P111_REG16, 0x0012, 0x0070},    /* PLL P Dividers = 112 */
  6.     {MT9P111_REG16, 0x0014, 0x2025},    /* PLL Control: TEST_BYPASS off = 8229 */
  7.     {MT9P111_REG16, 0x0022, 0x0030},    /* VDD_DIS Counter Delay = 48 */
  8.     {MT9P111_REG16, 0x002A, 0x7FFF},    /* PLL P Dividers 4-5-6 = 32767 */
  9.     {MT9P111_REG16, 0x002C, 0x0000},    /* PLL P Dividers 7 = 0 */
  10.     {MT9P111_REG16, 0x002E, 0x0000},    /* Sensor Clock Divider = 0 */
  11.     {MT9P111_REG16, 0x001E, 0x0777},    /* Pad Slew Pad Config = 1092 */
  12.     {MT9P111_REG16, 0x0018, 0x400C},    /* Standby Control and Status: Out of standby */
  13.     {MT9P111_WAIT_MS, 0, 30},
  14.    
  15.     /* set I2C master clock to 400 KHz */
  16.     {MT9P111_REG16, 0x098E, 0x6004},    /* LOGICAL_ADDRESS_ACCESS [IO_I2C_CLK_DIVIDER] */
  17.     {MT9P111_REG16, 0xE004, 0x0708},    /* I2C Master Clock Divider = 1800 */
  18.     {MT9P111_REG16, 0xE002, 0x0108},    /* IO_ALGO */
  19.     {MT9P111_WAIT_MS, 0, 10},
  20.    
  21.     /* resync I2C master */
  22.     {MT9P111_REG16, 0x0016, 0x0057},    /* CLOCKS_CONTROL */
  23.     {MT9P111_REG16, 0x3B00, 0x80A0},    /* TXBUFFER_DATA_REGISTER_0 */
  24.     {MT9P111_REG16, 0x3B02, 0x0000},    /* TXBUFFER_DATA_REGISTER_1 */
  25.     {MT9P111_REG16, 0x3B86, 0x0002},    /* TXBUFFER_TOTAL_BYTE_COUNT */
  26.     {MT9P111_REG16, 0x3B82, 0x0007},    /* I2C_MASTER_CONTROL */
  27.     {MT9P111_WAIT_MS, 0, 10},
  28.     {MT9P111_REG16, 0x0016, 0x0047},    /* CLOCKS_CONTROL */
  29.    
  30.     /* Preview at 1280x960 YCbCr 27.5fps, capture at 2592x1944 YCbCr 5.85fps */
  31.     {MT9P111_REG16, 0x98E, 0x1000},
  32.     {MT9P111_REG16, 0xC86C, 0x0518},    /* Output Width (A) = 1304 */
  33.     {MT9P111_REG16, 0xC86E, 0x03D4},    /* Output Height (A) = 980 */
  34.     {MT9P111_REG16, 0xC83A, 0x000C},    /* Row Start (A) = 12 */
  35.     {MT9P111_REG16, 0xC83C, 0x0018},    /* Column Start (A) = 24 */
  36.     {MT9P111_REG16, 0xC83E, 0x07B1},    /* Row End (A) = 1969 */
  37.     {MT9P111_REG16, 0xC840, 0x0A45},    /* Column End (A) = 2629 */
  38.     {MT9P111_REG16, 0xC842, 0x0001},    /* Row Speed (A) = 1 */
  39.     {MT9P111_REG16, 0xC844, 0x0103},    /* Core Skip X (A) = 259 */
  40.     {MT9P111_REG16, 0xC846, 0x0103},    /* Core Skip Y (A) = 259 */
  41.     {MT9P111_REG16, 0xC848, 0x0103},    /* Pipe Skip X (A) = 259 */
  42.     {MT9P111_REG16, 0xC84A, 0x0103},    /* Pipe Skip Y (A) = 259 */
  43.     {MT9P111_REG16, 0xC84C, 0x00F6},    /* Power Mode (A) = 246 */
  44.     {MT9P111_REG16, 0xC84E, 0x0001},    /* Bin Mode (A) = 1 */
  45.     {MT9P111_REG8, 0xC850, 0x00},       /* Orientation (A) = 0 */
  46.     {MT9P111_REG8, 0xC851, 0x00},       /* Pixel Order (A) = 0 */
  47.     {MT9P111_REG16, 0xC852, 0x019C},    /* Fine Correction (A) = 412 */
  48.     {MT9P111_REG16, 0xC854, 0x0732},    /* Fine IT Min (A) = 1842 */
  49.     {MT9P111_REG16, 0xC856, 0x048E},    /* Fine IT Max Margin (A) = 1166 */
  50.     {MT9P111_REG16, 0xC858, 0x0002},    /* Coarse IT Min (A) = 2 */
  51.     {MT9P111_REG16, 0xC85A, 0x0001},    /* Coarse IT Max Margin (A) = 1 */
  52.     {MT9P111_REG16, 0xC85C, 0x0423},    /* Min Frame Lines (A) = 1059 */
  53.     {MT9P111_REG16, 0xC85E, 0xFFFF},    /* Max Frame Lines (A) = 65535 */
  54.     {MT9P111_REG16, 0xC860, 0x0423},    /* Base Frame Lines (A) = 1059 */
  55.     {MT9P111_REG16, 0xC862, 0x0EDB},    /* Min Line Length (A) = 3803 */
  56.     {MT9P111_REG16, 0xC864, 0xFFFE},    /* Max Line Length (A) = 65534 */
  57.     {MT9P111_REG16, 0xC866, 0x7F7C},    /* P456 Divider (A) = 32636 */
  58.     {MT9P111_REG16, 0xC868, 0x0423},    /* Frame Lines (A) = 1059 */
  59.     {MT9P111_REG16, 0xC86A, 0x0EDB},    /* Line Length (A) = 3803 */
  60.     {MT9P111_REG16, 0xC870, 0x0014},    /* RX FIFO Watermark (A) = 20 */
  61.     {MT9P111_REG16, 0xC8AA, 0x0500},    /* Output_0 Image Width = 1280 */
  62.     {MT9P111_REG16, 0xC8AC, 0x03C0},    /* Output_0 Image Height = 960 */
  63.     {MT9P111_REG16, 0xC8AE, 0x0001},    /* Output_0 Image Format = 1 */
  64.     {MT9P111_REG16, 0xC8B0, 0x0000},    /* Output_0 Format Order = 0 */
  65.     {MT9P111_REG16, 0xC8B8, 0x0000},    /* Output_0 JPEG control = 0 */
  66.     {MT9P111_REG16, 0xC8A4, 0x0A28},    /* Output Width (B) = 2600 */
  67.     {MT9P111_REG16, 0xC8A6, 0x07A0},    /* Output Height (B) = 1952 */
  68.     {MT9P111_REG16, 0xC872, 0x0010},    /* Row Start (B) = 16 */
  69.     {MT9P111_REG16, 0xC874, 0x001C},    /* Column Start (B) = 28 */
  70.     {MT9P111_REG16, 0xC876, 0x07AF},    /* Row End (B) = 1967 */
  71.     {MT9P111_REG16, 0xC878, 0x0A43},    /* Column End (B) = 2627 */
  72.     {MT9P111_REG16, 0xC87A, 0x0001},    /* Row Speed (B) = 1 */
  73.     {MT9P111_REG16, 0xC87C, 0x0101},    /* Core Skip X (B) = 257 */
  74.     {MT9P111_REG16, 0xC87E, 0x0101},    /* Core Skip Y (B) = 257 */
  75.     {MT9P111_REG16, 0xC880, 0x0101},    /* Pipe Skip X (B) = 257 */
  76.     {MT9P111_REG16, 0xC882, 0x0101},    /* Pipe Skip Y (B) = 257 */
  77.     {MT9P111_REG16, 0xC884, 0x00F2},    /* Power Mode (B) = 242 */
  78.     {MT9P111_REG16, 0xC886, 0x0000},    /* Bin Mode (B) = 0 */
  79.     {MT9P111_REG8, 0xC888, 0x00},       /* Orientation (B) = 0 */
  80.     {MT9P111_REG8, 0xC889, 0x00},       /* Pixel Order (B) = 0 */
  81.     {MT9P111_REG16, 0xC88A, 0x009C},    /* Fine Correction (B) = 156 */
  82.     {MT9P111_REG16, 0xC88C, 0x034A},    /* Fine IT Min (B) = 842 */
  83.     {MT9P111_REG16, 0xC88E, 0x02A6},    /* Fine IT Max Margin (B) = 678 */
  84.     {MT9P111_REG16, 0xC890, 0x0002},    /* Coarse IT Min (B) = 2 */
  85.     {MT9P111_REG16, 0xC892, 0x0001},    /* Coarse IT Max Margin (B) = 1 */
  86.     {MT9P111_REG16, 0xC894, 0x07EF},    /* Min Frame Lines (B) = 2031 */
  87.     {MT9P111_REG16, 0xC896, 0xFFFF},    /* Max Frame Lines (B) = 65535 */
  88.     {MT9P111_REG16, 0xC898, 0x07EF},    /* Base Frame Lines (B) = 2031 */
  89.     {MT9P111_REG16, 0xC89A, 0x246A},    /* Min Line Length (B) = 9322 */
  90.     {MT9P111_REG16, 0xC89C, 0xFFFE},    /* Max Line Length (B) = 65534   */
  91.     {MT9P111_REG16, 0xC89E, 0x7F9C},    /* P456 Divider (B) = 32668 */
  92.     {MT9P111_REG16, 0xC8A0, 0x07EF},    /* Frame Lines (B) = 2031 */
  93.     {MT9P111_REG16, 0xC8A2, 0x246A},    /* Line Length (B) = 9322 */
  94.     {MT9P111_REG16, 0xC8A8, 0x0014},    /* RX FIFO Watermark (B) = 20 */
  95.     {MT9P111_REG16, 0xC8C0, 0x0A20},    /* Output_1 Image Width = 2592 */
  96.     {MT9P111_REG16, 0xC8C2, 0x0798},    /* Output_1 Image Height = 1944 */
  97.     {MT9P111_REG16, 0xC8C4, 0x0001},    /* Output_1 Image Format = 1 */
  98.     {MT9P111_REG16, 0xC8C6, 0x0000},    /* Output_1 Format Order = 0 */
  99.     {MT9P111_REG16, 0xC8CE, 0x0000},    /* Output_1 JPEG control = 0 */
  100.     {MT9P111_REG16, 0xA010, 0x010F},    /* fd_min_expected50hz_flicker_period = 271 */
  101.     {MT9P111_REG16, 0xA012, 0x0137},    /* fd_max_expected50hz_flicker_period = 311 */
  102.     {MT9P111_REG16, 0xA014, 0x00DF},    /* fd_min_expected60hz_flicker_period = 223 */
  103.     {MT9P111_REG16, 0xA016, 0x0107},    /* fd_max_expected60hz_flicker_period = 263 */
  104.     {MT9P111_REG16, 0xA018, 0x0123},    /* fd_expected50hz_flicker_period (A) = 291 */
  105.     {MT9P111_REG16, 0xA01A, 0x0077},    /* fd_expected50hz_flicker_period (B) = 119 */
  106.     {MT9P111_REG16, 0xA01C, 0x00F3},    /* fd_expected60hz_flicker_period (A) = 243 */
  107.     {MT9P111_REG16, 0xA01E, 0x0063},    /* fd_expected60hz_flicker_period (B) = 99 */
  108.     {MT9P111_REG8, 0xDC0A, 0x06},       /* Scaler Allow Zoom Ratio = 6 */
  109.     {MT9P111_REG16, 0xDC1C, 0x2710},    /* System Zoom Ratio = 10000 */
  110.     {MT9P111_REG8, 0x8404, 0x06},       /* Refresh Sequencer Mode = 6 */
  111.    
  112.     /* k28a_rev03_patch01_basic_REV5 */
  113.     {MT9P111_REG16, 0x0982, 0x0000},    /* ACCESS_CTL_STAT */
  114.     {MT9P111_REG16, 0x098A, 0x0000},    /* PHYSICAL_ADDRESS_ACCESS */
  115.  
  116.  
  117.     /* try enable parallel */
  118.     {MT9P111_REG16, 0x001A, 0x0018},    /* RESET_AND_MISC_CONTROL */
  119.     {MT9P111_REG16, 0x001A, 0x0300},    /* parallel_enable, oe_gp_enable */
  120.     {MT9P111_REG16, 0x3CA0, 0x0000},    /* TXSS_PARAMETERS */ // ~~~
  121.     {MT9P111_REG16, 0x0018, 0x2008},    /* STANDBY_CONTROL_AND_STATUS, Run MCU */
  122.  
  123.     {MT9P111_TABLE_END, 0, 0}
  124. };
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