Gato en Verilog

module paso1(A_0, B_0, C_0, D_0, E_0, F_0, G_0, H_0, I_0,A_1_W, B_1_W, C_1_W, D_1_W, E_1_W , F_1_W, G_1_W, H_1_W);
input [1:0] A_0, B_0, C_0, D_0, E_0, F_0, G_0, H_0, I_0;
output [5:0] A_1_W, B_1_W, C_1_W, D_1_W, E_1_W , F_1_W, G_1_W, H_1_W;

assign A_1_W[0] = C_0[0];
assign A_1_W[1] = C_0[1];
assign A_1_W[2] = B_0[0];
assign A_1_W[3] = B_0[1];
assign A_1_W[4] = A_0[0];
assign A_1_W[5] = A_0[1];
assign B_1_W[0] = F_0[0];
assign B_1_W[1] = F_0[1];
assign B_1_W[2] = E_0[0];
assign B_1_W[3] = E_0[1];
assign B_1_W[4] = D_0[0];
assign B_1_W[5] = D_0[1];
assign C_1_W[0] = I_0[0];
assign C_1_W[1] = I_0[1];
assign C_1_W[2] = H_0[0];
assign C_1_W[3] = H_0[1];
assign C_1_W[4] = G_0[0];
assign C_1_W[5] = G_0[1];
assign D_1_W[0] = G_0[0];
assign D_1_W[1] = G_0[1];
assign D_1_W[2] = D_0[0];
assign D_1_W[3] = D_0[1];
assign D_1_W[4] = A_0[0];
assign D_1_W[5] = A_0[1];
assign E_1_W[0] = H_0[0];
assign E_1_W[1] = H_0[1];
assign E_1_W[2] = E_0[0];
assign E_1_W[3] = E_0[1];
assign E_1_W[4] = B_0[0];
assign E_1_W[5] = B_0[1];
assign F_1_W[0] = I_0[0];
assign F_1_W[1] = I_0[1];
assign F_1_W[2] = F_0[0];
assign F_1_W[3] = F_0[1];
assign F_1_W[4] = C_0[0];
assign F_1_W[5] = C_0[1];
assign G_1_W[0] = I_0[0];
assign G_1_W[1] = I_0[1];
assign G_1_W[2] = E_0[0];
assign G_1_W[3] = E_0[1];
assign G_1_W[4] = A_0[0];
assign G_1_W[5] = A_0[1];
assign H_1_W[0] = C_0[0];
assign H_1_W[1] = C_0[1];
assign H_1_W[2] = E_0[0];
assign H_1_W[3] = E_0[1];
assign H_1_W[4] = G_0[0];
assign H_1_W[5] = G_0[1];

endmodule

///////////////////////////////////////////////////////////////////////////////////////////////////

module paso2(A_1, B_1, C_1, D_1, E_1 , F_1, G_1, H_1,A_2_W, B_2_W, C_2_W, D_2_W, E_2_W , F_2_W, G_2_W, H_2_W);
input [5:0] A_1, B_1, C_1, D_1, E_1, F_1, G_1, H_1;
output [1:0] A_2_W, B_2_W, C_2_W, D_2_W, E_2_W , F_2_W, G_2_W, H_2_W;

assign A_2_W[0] = A_1[5] &  ~A_1[4] &  A_1[3] &  ~A_1[2] &  A_1[1] &  ~A_1[0];
assign A_2_W[1] = ~A_1[5] &  A_1[4] &  ~A_1[3] &  A_1[2] &  ~A_1[1] &  A_1[0];

assign B_2_W[0] = B_1[5] &  ~B_1[4] &  B_1[3] &  ~B_1[2] &  B_1[1] &  ~B_1[0];
assign B_2_W[1] = ~B_1[5] &  B_1[4] &  ~B_1[3] &  B_1[2] &  ~B_1[1] &  B_1[0];

assign C_2_W[0] = C_1[5] &  ~C_1[4] &  C_1[3] &  ~C_1[2] &  C_1[1] &  ~C_1[0];
assign C_2_W[1] = ~C_1[5] &  C_1[4] &  ~C_1[3] &  C_1[2] &  ~C_1[1] &  C_1[0];

assign D_2_W[0] = D_1[5] &  ~D_1[4] &  D_1[3] &  ~D_1[2] &  D_1[1] &  ~D_1[0];
assign D_2_W[1] = ~D_1[5] &  D_1[4] &  ~D_1[3] &  D_1[2] &  ~D_1[1] &  D_1[0];

assign E_2_W[0] = E_1[5] &  ~E_1[4] &  E_1[3] &  ~E_1[2] &  E_1[1] &  ~E_1[0];
assign E_2_W[1] = ~E_1[5] &  E_1[4] &  ~E_1[3] &  E_1[2] &  ~E_1[1] &  E_1[0];

assign F_2_W[0] = F_1[5] &  ~F_1[4] &  F_1[3] &  ~F_1[2] &  F_1[1] &  ~F_1[0];
assign F_2_W[1] = ~F_1[5] &  F_1[4] &  ~F_1[3] &  F_1[2] &  ~F_1[1] &  F_1[0];

assign G_2_W[0] = G_1[5] &  ~G_1[4] &  G_1[3] &  ~G_1[2] &  G_1[1] &  ~G_1[0];
assign G_2_W[1] = ~G_1[5] &  G_1[4] &  ~G_1[3] &  G_1[2] &  ~G_1[1] &  G_1[0];

assign H_2_W[0] = H_1[5] &  ~H_1[4] &  H_1[3] &  ~H_1[2] &  H_1[1] &  ~H_1[0];
assign H_2_W[1] = ~H_1[5] &  H_1[4] &  ~H_1[3] &  H_1[2] &  ~H_1[1] &  H_1[0];

endmodule

///////////////////////////////////////////////////////////////////////////////////////////////////

module test(); //En un archivo test-and. Fïjese que no tiene entradas ni salidas. Es una caja negra que envuelve el módulo
reg [1:0] A_0, B_0, C_0, D_0, E_0, F_0, G_0, H_0, I_0;
wire [1:0]  A_0_W, B_0_W, C_0_W, D_0_W, E_0_W, F_0_W, G_0_W, H_0_W, I_0_W;
wire [5:0] A_1_W, B_1_W, C_1_W, D_1_W, E_1_W , F_1_W, G_1_W, H_1_W; // Salida

reg [5:0] A_1, B_1, C_1, D_1, E_1, F_1, G_1, H_1;
wire [1:0] A_2_W, B_2_W, C_2_W, D_2_W, E_2_W , F_2_W, G_2_W, H_2_W; // Salida

paso1 test1 (.A_0(A_0_W), .B_0(B_0_W), .C_0(C_0_W), .D_0(D_0_W), .E_0(E_0_W), .F_0(F_0_W), .G_0(G_0_W), .H_0(H_0_W), .I_0(I_0_W),.A_1_W(A_1_W), .B_1_W(B_1_W), .C_1_W(C_1_W), .D_1_W(D_1_W), .E_1_W(E_1_W) , .F_1_W(F_1_W), .G_1_W(G_1_W), .H_1_W(H_1_W));

paso2 test2 (.A_1(A_1_W), .B_1(B_1_W), .C_1(C_1_W), .D_1(D_1_W), .E_1(E_1_W), .F_1(F_1_W), .G_1(G_1_W), .H_1(H_1_W),.A_2_W(A_2_W), .B_2_W(B_2_W), .C_2_W(C_2_W), .D_2_W(D_2_W), .E_2_W(E_2_W) , .F_2_W(F_2_W), .G_2_W(G_2_W), .H_2_W(H_2_W));


assign A_0_W = A_0;
assign B_0_W = B_0;
assign C_0_W = C_0;
assign D_0_W = D_0;
assign E_0_W = E_0;
assign F_0_W = F_0;
assign G_0_W = G_0;
assign H_0_W = H_0;
assign I_0_W = I_0;

initial
begin


                                  // AQUÍ SE PUEDE JUGAR  EL GATO
                                 ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

                            A_0=2'b00;                          D_0=2'b00;                   G_0=2'b00;


                            B_0=2'b00;                          E_0=2'b00;                   H_0=2'b00;


                            C_0=2'b00;                          F_0=2'b00;                   I_0=2'b00;


                                 ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////


#10

$display();
$display("TIC TAC TOE");
$display();
if (A_0 == 2'b10) $write("[X]"); else if (A_0 == 2'b01) $write("[O]"); else $write("[ ]");
if (D_0 == 2'b10) $write("[X]"); else if (D_0 == 2'b01) $write("[O]"); else $write("[ ]");
if (G_0 == 2'b10) $write("[X]"); else if (G_0 == 2'b01) $write("[O]"); else $write("[ ]");
$display();
if (B_0 == 2'b10) $write("[X]"); else if (B_0 == 2'b01) $write("[O]"); else $write("[ ]");
if (E_0 == 2'b10) $write("[X]"); else if (E_0 == 2'b01) $write("[O]"); else $write("[ ]");
if (H_0 == 2'b10) $write("[X]"); else if (H_0 == 2'b01) $write("[O]"); else $write("[ ]");
$display();
if (C_0 == 2'b10) $write("[X]"); else if (C_0 == 2'b01) $write("[O]"); else $write("[ ]");
if (F_0 == 2'b10) $write("[X]"); else if (F_0 == 2'b01) $write("[O]"); else $write("[ ]");
if (I_0 == 2'b10) $write("[X]"); else if (I_0 == 2'b01) $write("[O]"); else $write("[ ]");
$display();
$display();

$display("{Cadena Inicial, 18 bits}");
$display(A_0[0],A_0[1],B_0[0],B_0[1],C_0[0],C_0[1],D_0[0],D_0[1],E_0[0],E_0[1],F_0[0],F_0[1],G_0[0],G_0[1],H_0[0],H_0[1],I_0[0],I_0[1]);
$display();
$display("{Cadena Fragmentadora de gato, 48 bits}");
$display(A_1_W[5],A_1_W[4],A_1_W[3],A_1_W[2],A_1_W[1],A_1_W[0],B_1_W[5],B_1_W[4],B_1_W[3],B_1_W[2],B_1_W[1],B_1_W[0],C_1_W[5],C_1_W[4],C_1_W[3],C_1_W[2],C_1_W[1],C_1_W[0],D_1_W[5],D_1_W[4],D_1_W[3],D_1_W[2],D_1_W[1],D_1_W[0],E_1_W[5],E_1_W[4],E_1_W[3],E_1_W[2],E_1_W[1],E_1_W[0],F_1_W[5],F_1_W[4],F_1_W[3],F_1_W[2],F_1_W[1],F_1_W[0],G_1_W[5],G_1_W[4],G_1_W[3],G_1_W[2],G_1_W[1],G_1_W[0],H_1_W[5],H_1_W[4],H_1_W[3],H_1_W[2],H_1_W[1],H_1_W[0]);
$display();
$display("{Cadena detectora de ganes, 16 bits}");
$display(A_2_W[0],A_2_W[1],B_2_W[0],B_2_W[1],C_2_W[0],C_2_W[1],D_2_W[0],D_2_W[1],E_2_W[0],E_2_W[1],F_2_W[0],F_2_W[1],G_2_W[0],G_2_W[1],H_2_W[0],H_2_W[1]);
$display();
$display("{Ganador, 2 bits}");
$write(A_2_W[0] | B_2_W[0] | C_2_W[0] | D_2_W[0] | E_2_W[0] | F_2_W[0] | G_2_W[0] | H_2_W[0],A_2_W[1] | B_2_W[1] | C_2_W[1] | D_2_W[1] | E_2_W[1] | F_2_W[1] | G_2_W[1] | H_2_W[1]);
if (A_2_W[0] | B_2_W[0] | C_2_W[0] | D_2_W[0] | E_2_W[0] | F_2_W[0] | G_2_W[0] | H_2_W[0]==1) $write(", Jugador 1");
else if (A_2_W[1] | B_2_W[1] | C_2_W[1] | D_2_W[1] | E_2_W[1] | F_2_W[1] | G_2_W[1] | H_2_W[1]) $write(", Jugador 2");
else  $write(", sin ganador aun");

$display();$display();$display();$display();$display();$display();$display();


end //initial

endmodule