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  1. /*
  2.  * Xilinx Zynq Device Config driver
  3.  *
  4.  * Copyright (c) 2011 - 2013 Xilinx Inc.
  5.  *
  6.  * This program is free software; you can redistribute it and/or
  7.  * modify it under the terms of the GNU General Public License
  8.  * as published by the Free Software Foundation; either version
  9.  * 2 of the License, or (at your option) any later version.
  10.  */
  11.  
  12. #include <linux/cdev.h>
  13. #include <linux/clk.h>
  14. #include <linux/dma-mapping.h>
  15. #include <linux/fs.h>
  16. #include <linux/init.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/io.h>
  19. #include <linux/ioport.h>
  20. #include <linux/kernel.h>
  21. #include <linux/module.h>
  22. #include <linux/mutex.h>
  23. #include <linux/of.h>
  24. #include <linux/platform_device.h>
  25. #include <linux/slab.h>
  26. #include <linux/string.h>
  27. #include <linux/sysctl.h>
  28. #include <linux/types.h>
  29. #include <linux/uaccess.h>
  30. #include <linux/delay.h>
  31.  
  32. extern void zynq_slcr_init_preload_fpga(void);
  33. extern void zynq_slcr_init_postload_fpga(void);
  34.  
  35. #define DRIVER_NAME "xdevcfg"
  36. #define XDEVCFG_DEVICES 1
  37.  
  38. /* An array, which is set to true when the device is registered. */
  39. static DEFINE_MUTEX(xdevcfg_mutex);
  40.  
  41. /* Constant Definitions */
  42. #define XDCFG_CTRL_OFFSET       0x00 /* Control Register */
  43. #define XDCFG_LOCK_OFFSET       0x04 /* Lock Register */
  44. #define XDCFG_INT_STS_OFFSET        0x0C /* Interrupt Status Register */
  45. #define XDCFG_INT_MASK_OFFSET       0x10 /* Interrupt Mask Register */
  46. #define XDCFG_STATUS_OFFSET     0x14 /* Status Register */
  47. #define XDCFG_DMA_SRC_ADDR_OFFSET   0x18 /* DMA Source Address Register */
  48. #define XDCFG_DMA_DEST_ADDR_OFFSET  0x1C /* DMA Destination Address Reg */
  49. #define XDCFG_DMA_SRC_LEN_OFFSET    0x20 /* DMA Source Transfer Length */
  50. #define XDCFG_DMA_DEST_LEN_OFFSET   0x24 /* DMA Destination Transfer */
  51. #define XDCFG_UNLOCK_OFFSET     0x34 /* Unlock Register */
  52. #define XDCFG_MCTRL_OFFSET      0x80 /* Misc. Control Register */
  53.  
  54. /* Control Register Bit definitions */
  55. #define XDCFG_CTRL_PCFG_PROG_B_MASK 0x40000000 /* Program signal to
  56.                             *  Reset FPGA */
  57. #define XDCFG_CTRL_PCAP_PR_MASK     0x08000000 /* Enable PCAP for PR */
  58. #define XDCFG_CTRL_PCAP_MODE_MASK   0x04000000 /* Enable PCAP */
  59. #define XDCFG_CTRL_PCAP_RATE_EN_MASK  0x02000000 /* Enable PCAP Quad Rate */
  60. #define XDCFG_CTRL_PCFG_AES_EN_MASK 0x00000E00 /* AES Enable Mask */
  61. #define XDCFG_CTRL_SEU_EN_MASK      0x00000100 /* SEU Enable Mask */
  62. #define XDCFG_CTRL_SPNIDEN_MASK     0x00000040 /* Secure Non Invasive
  63.                             *  Debug Enable */
  64. #define XDCFG_CTRL_SPIDEN_MASK      0x00000020 /* Secure Invasive
  65.                             *  Debug Enable */
  66. #define XDCFG_CTRL_NIDEN_MASK       0x00000010 /* Non-Invasive Debug
  67.                             *  Enable */
  68. #define XDCFG_CTRL_DBGEN_MASK       0x00000008 /* Invasive Debug
  69.                             *  Enable */
  70. #define XDCFG_CTRL_DAP_EN_MASK      0x00000007 /* DAP Enable Mask */
  71.  
  72. /* Lock register bit definitions */
  73.  
  74. #define XDCFG_LOCK_AES_EN_MASK      0x00000008 /* Lock AES_EN update */
  75. #define XDCFG_LOCK_SEU_MASK     0x00000004 /* Lock SEU_En update */
  76. #define XDCFG_LOCK_DBG_MASK     0x00000001 /* This bit locks
  77.                             *  security config
  78.                             *  including: DAP_En,
  79.                             *  DBGEN,NIDEN, SPNIEN */
  80.  
  81. /* Miscellaneous Control Register bit definitions */
  82. #define XDCFG_MCTRL_PCAP_LPBK_MASK  0x00000010 /* Internal PCAP loopback */
  83.  
  84. /* Status register bit definitions */
  85. #define XDCFG_STATUS_PCFG_INIT_MASK 0x00000010 /* FPGA init status */
  86.  
  87. /* Interrupt Status/Mask Register Bit definitions */
  88. #define XDCFG_IXR_DMA_DONE_MASK     0x00002000 /* DMA Command Done */
  89. #define XDCFG_IXR_D_P_DONE_MASK     0x00001000 /* DMA and PCAP Cmd Done */
  90. #define XDCFG_IXR_PCFG_DONE_MASK    0x00000004 /* FPGA programmed */
  91. #define XDCFG_IXR_ERROR_FLAGS_MASK  0x00F0F860
  92. #define XDCFG_IXR_ALL_MASK      0xF8F7F87F
  93. /* Miscellaneous constant values */
  94. #define XDCFG_DMA_INVALID_ADDRESS   0xFFFFFFFF  /* Invalid DMA address */
  95.  
  96. static const char * const fclk_name[] = {
  97.     "fclk0",
  98.     "fclk1",
  99.     "fclk2",
  100.     "fclk3"
  101. };
  102. #define NUMFCLKS ARRAY_SIZE(fclk_name)
  103.  
  104. /**
  105.  * struct xdevcfg_drvdata - Device Configuration driver structure
  106.  *
  107.  * @dev: Pointer to the device structure
  108.  * @cdev: Instance of the cdev structure
  109.  * @devt: Pointer to the dev_t structure
  110.  * @class: Pointer to device class
  111.  * @fclk_class: Pointer to fclk device class
  112.  * @dma_done: The dma_done status bit for the DMA command completion
  113.  * @error_status: The error status captured during the DMA transfer
  114.  * @irq: Interrupt number
  115.  * @clk: Peripheral clock for devcfg
  116.  * @fclk: Array holding references to the FPGA clocks
  117.  * @fclk_exported: Flag inidcating whether an FPGA clock is exported
  118.  * @is_open: The status bit to indicate whether the device is opened
  119.  * @sem: Instance for the mutex
  120.  * @lock: Instance of spinlock
  121.  * @base_address: The virtual device base address of the device registers
  122.  * @is_partial_bitstream: Status bit to indicate partial/full bitstream
  123.  */
  124. struct xdevcfg_drvdata {
  125.     struct device *dev;
  126.     struct cdev cdev;
  127.     dev_t devt;
  128.     struct class *class;
  129.     struct class *fclk_class;
  130.     int irq;
  131.     struct clk *clk;
  132.     struct clk *fclk[NUMFCLKS];
  133.     u8 fclk_exported[NUMFCLKS];
  134.     volatile bool dma_done;
  135.     volatile int error_status;
  136.     bool is_open;
  137.     struct mutex sem;
  138.     spinlock_t lock;
  139.     void __iomem *base_address;
  140.     int ep107;
  141.     bool is_partial_bitstream;
  142.     bool endian_swap;
  143.     char residue_buf[3];
  144.     int residue_len;
  145. };
  146.  
  147. /**
  148.  * struct fclk_data - FPGA clock data
  149.  * @clk: Pointer to clock
  150.  * @enable: Flag indicating enable status of the clock
  151.  * @rate_rnd: Rate to be rounded for round rate operation
  152.  */
  153. struct fclk_data {
  154.     struct clk *clk;
  155.     int enabled;
  156.     unsigned long rate_rnd;
  157. };
  158.  
  159. /* Register read/write access routines */
  160. #define xdevcfg_writereg(offset, val)   __raw_writel(val, offset)
  161. #define xdevcfg_readreg(offset)     __raw_readl(offset)
  162.  
  163. /**
  164.  * xdevcfg_reset_pl() - Reset the programmable logic.
  165.  * @base_address:   The base address of the device.
  166.  *
  167.  * Must be called with PCAP clock enabled
  168.  */
  169. static void xdevcfg_reset_pl(void __iomem *base_address)
  170. {
  171.     /*
  172.      * Create a rising edge on PCFG_INIT. PCFG_INIT follows PCFG_PROG_B,
  173.      * so we need to * poll it after setting PCFG_PROG_B to make sure that
  174.      * the rising edge happens.
  175.      */
  176.     xdevcfg_writereg(base_address + XDCFG_CTRL_OFFSET,
  177.             (xdevcfg_readreg(base_address + XDCFG_CTRL_OFFSET) |
  178.              XDCFG_CTRL_PCFG_PROG_B_MASK));
  179.     while (!(xdevcfg_readreg(base_address + XDCFG_STATUS_OFFSET) &
  180.                 XDCFG_STATUS_PCFG_INIT_MASK))
  181.         ;
  182.  
  183.     xdevcfg_writereg(base_address + XDCFG_CTRL_OFFSET,
  184.             (xdevcfg_readreg(base_address + XDCFG_CTRL_OFFSET) &
  185.              ~XDCFG_CTRL_PCFG_PROG_B_MASK));
  186.     while (xdevcfg_readreg(base_address + XDCFG_STATUS_OFFSET) &
  187.             XDCFG_STATUS_PCFG_INIT_MASK)
  188.         ;
  189.  
  190.     xdevcfg_writereg(base_address + XDCFG_CTRL_OFFSET,
  191.             (xdevcfg_readreg(base_address + XDCFG_CTRL_OFFSET) |
  192.              XDCFG_CTRL_PCFG_PROG_B_MASK));
  193.     while (!(xdevcfg_readreg(base_address + XDCFG_STATUS_OFFSET) &
  194.                 XDCFG_STATUS_PCFG_INIT_MASK))
  195.         ;
  196. }
  197.  
  198. /**
  199.  * xdevcfg_irq() - The main interrupt handler.
  200.  * @irq:    The interrupt number.
  201.  * @data:   Pointer to the driver data structure.
  202.  * returns: IRQ_HANDLED after the interrupt is handled.
  203.  **/
  204. static irqreturn_t xdevcfg_irq(int irq, void *data)
  205. {
  206.     u32 intr_status;
  207.     struct xdevcfg_drvdata *drvdata = data;
  208.  
  209.     spin_lock(&drvdata->lock);
  210.  
  211.     intr_status = xdevcfg_readreg(drvdata->base_address +
  212.                     XDCFG_INT_STS_OFFSET);
  213.  
  214.     /* Clear the interrupts */
  215.     xdevcfg_writereg(drvdata->base_address + XDCFG_INT_STS_OFFSET,
  216.                 intr_status);
  217.  
  218.     if ((intr_status & XDCFG_IXR_D_P_DONE_MASK) ==
  219.                 XDCFG_IXR_D_P_DONE_MASK)
  220.         drvdata->dma_done = 1;
  221.  
  222.     if ((intr_status & XDCFG_IXR_ERROR_FLAGS_MASK) ==
  223.             XDCFG_IXR_ERROR_FLAGS_MASK)
  224.         drvdata->error_status = 1;
  225.  
  226.     spin_unlock(&drvdata->lock);
  227.  
  228.     return IRQ_HANDLED;
  229. }
  230.  
  231. /**
  232.  * xdevcfg_write() - The is the driver write function.
  233.  *
  234.  * @file:   Pointer to the file structure.
  235.  * @buf:    Pointer to the bitstream location.
  236.  * @count:  The number of bytes to be written.
  237.  * @ppos:   Pointer to the offset value
  238.  * returns: Success or error status.
  239.  **/
  240. static ssize_t
  241. xdevcfg_write(struct file *file, const char __user *buf, size_t count,
  242.         loff_t *ppos)
  243. {
  244.     char *kbuf;
  245.     int status;
  246.     unsigned long timeout;
  247.     u32 intr_reg, dma_len;
  248.     dma_addr_t dma_addr;
  249.     u32 transfer_length = 0;
  250.     struct xdevcfg_drvdata *drvdata = file->private_data;
  251.     size_t user_count = count;
  252.     int i;
  253.     int error;
  254.     u8 data;
  255.     u8 offset;
  256.     struct resource *region;
  257.     void __iomem *rom;
  258.  
  259.     status = clk_enable(drvdata->clk);
  260.     if (status)
  261.         return status;
  262.  
  263.     status = mutex_lock_interruptible(&drvdata->sem);
  264.  
  265.     if (status)
  266.         goto err_clk;
  267.  
  268.     dma_len = count + drvdata->residue_len;
  269.     kbuf = dma_alloc_coherent(drvdata->dev, dma_len, &dma_addr, GFP_KERNEL);
  270.     if (!kbuf) {
  271.         status = -ENOMEM;
  272.         goto err_unlock;
  273.     }
  274.  
  275.     /* Collect stragglers from last time (0 to 3 bytes) */
  276.     memcpy(kbuf, drvdata->residue_buf, drvdata->residue_len);
  277.  
  278.     /* Fetch user data, appending to stragglers */
  279.     if (copy_from_user(kbuf + drvdata->residue_len, buf, count)) {
  280.         status = -EFAULT;
  281.         goto error;
  282.     }
  283.  
  284.     /* Include stragglers in total bytes to be handled */
  285.     count += drvdata->residue_len;
  286.  
  287.     /* First block contains a header */
  288.     if (*ppos == 0 && count > 4) {
  289.         /* Look for sync word */
  290.         for (i = 0; i < count - 4; i++) {
  291.             if (memcmp(kbuf + i, "\x66\x55\x99\xAA", 4) == 0) {
  292.                 pr_debug("Found normal sync word\n");
  293.                 drvdata->endian_swap = 0;
  294.                 break;
  295.             }
  296.             if (memcmp(kbuf + i, "\xAA\x99\x55\x66", 4) == 0) {
  297.                 pr_debug("Found swapped sync word\n");
  298.                 drvdata->endian_swap = 1;
  299.                 break;
  300.             }
  301.         }
  302.         /* Remove the header, aligning the data on word boundary */
  303.         if (i != count - 4) {
  304.             count -= i;
  305.             memmove(kbuf, kbuf + i, count);
  306.         }
  307.     }
  308.  
  309.     /* Save stragglers for next time */
  310.     drvdata->residue_len = count % 4;
  311.     count -= drvdata->residue_len;
  312.     memcpy(drvdata->residue_buf, kbuf + count, drvdata->residue_len);
  313.  
  314.     /* Fixup endianess of the data */
  315.     if (drvdata->endian_swap) {
  316.         for (i = 0; i < count; i += 4) {
  317.             u32 *p = (u32 *)&kbuf[i];
  318.             *p = swab32(*p);
  319.         }
  320.     }
  321.  
  322.     /* Enable DMA and error interrupts */
  323.     xdevcfg_writereg(drvdata->base_address + XDCFG_INT_STS_OFFSET,
  324.                 XDCFG_IXR_ALL_MASK);
  325.  
  326.  
  327.     xdevcfg_writereg(drvdata->base_address + XDCFG_INT_MASK_OFFSET,
  328.                 (u32) (~(XDCFG_IXR_D_P_DONE_MASK |
  329.                 XDCFG_IXR_ERROR_FLAGS_MASK)));
  330.  
  331.     drvdata->dma_done = 0;
  332.     drvdata->error_status = 0;
  333.  
  334.     /* Initiate DMA write command */
  335.     if (count < 0x1000)
  336.         xdevcfg_writereg(drvdata->base_address +
  337.             XDCFG_DMA_SRC_ADDR_OFFSET, (u32)(dma_addr + 1));
  338.     else
  339.         xdevcfg_writereg(drvdata->base_address +
  340.             XDCFG_DMA_SRC_ADDR_OFFSET, (u32) dma_addr);
  341.  
  342.     xdevcfg_writereg(drvdata->base_address + XDCFG_DMA_DEST_ADDR_OFFSET,
  343.                 (u32)XDCFG_DMA_INVALID_ADDRESS);
  344.     /* Convert number of bytes to number of words.  */
  345.     if (count % 4)
  346.         transfer_length = (count / 4 + 1);
  347.     else
  348.         transfer_length = count / 4;
  349.     xdevcfg_writereg(drvdata->base_address + XDCFG_DMA_SRC_LEN_OFFSET,
  350.                 transfer_length);
  351.     xdevcfg_writereg(drvdata->base_address + XDCFG_DMA_DEST_LEN_OFFSET, 0);
  352.  
  353.     timeout = jiffies + msecs_to_jiffies(1000);
  354.  
  355.     while (!drvdata->dma_done) {
  356.         if (time_after(jiffies, timeout)) {
  357.                 status = -ETIMEDOUT;
  358.                 goto error;
  359.         }
  360.     }
  361.  
  362.     if (drvdata->error_status)
  363.         status = drvdata->error_status;
  364.  
  365.     /* Disable the DMA and error interrupts */
  366.     intr_reg = xdevcfg_readreg(drvdata->base_address +
  367.                     XDCFG_INT_MASK_OFFSET);
  368.     xdevcfg_writereg(drvdata->base_address + XDCFG_INT_MASK_OFFSET,
  369.                 intr_reg | (XDCFG_IXR_D_P_DONE_MASK |
  370.                 XDCFG_IXR_ERROR_FLAGS_MASK));
  371.  
  372.     /* If we didn't write correctly, then bail out. */
  373.     if (status) {
  374.         status = -EFAULT;
  375.         goto error;
  376.     }
  377.  
  378.     /* Binfiles for the Zynq are always the same size, so this works in
  379.      * prototyping */
  380.     if (*ppos + user_count == 4045564) {
  381.         // Wait for FPGA programming to be done
  382.         while (!(xdevcfg_readreg(drvdata->base_address +
  383.                 XDCFG_INT_STS_OFFSET) &
  384.                 XDCFG_IXR_PCFG_DONE_MASK)) {
  385.             msleep(50);
  386.             printk(".");
  387.         }
  388.  
  389.         region = request_mem_region(0x7fff0000, 0x10000,
  390.             "xilinx_xdevcfg");
  391.         if (region == NULL) {
  392.             printk("xdevcfg: !! Region request failed\n");
  393.             return -EBUSY;
  394.         }
  395.         printk("xdevcfg: Region received\n");
  396.  
  397.         rom = ioremap(0x7fff0000, 0x10000);
  398.         if (rom == NULL) {
  399.             printk("xdevcfg: !! Remap failed\n");
  400.             return -EIO;
  401.         }
  402.         printk("xdevcfg: Memory remapped\n");
  403.  
  404.         // Overlay-specific stuff
  405.         error = of_overlay_destroy_all();
  406.         if (error) {
  407.             printk("!! Destroy failed\n");
  408.             status = -ENODEV;
  409.             goto error;
  410.         }
  411.         printk("Overlays destroyed\n");
  412.  
  413.         printk("ROM address: %p\n", rom);
  414.         offset = ioread8((u8 *)rom);
  415.         printk("Data: %d\n", offset);
  416.  
  417.         /*data = ioread8((u8 *)rom + offset);
  418.         printk("DATA: %d\n", data);*/
  419.  
  420.         if (data == 0xd00dfeed) {
  421.             // Do the actual work with overlays here
  422.             // of_overlay_create((struct device_node *)io);
  423.         } else {
  424.             // Device trees always start with 0xd00dfeed
  425.             printk("BAD MAGIC\n");
  426.         }
  427.         printk("READ DONE\n");
  428.  
  429.         /*iounmap(rom);
  430.         printk("UNMAPPED\n");
  431.         release_mem_region(0x7fff0000, 0x10000);
  432.         printk("REGION RELEASED\n");*/
  433.     }
  434.  
  435.     *ppos += user_count;
  436.     status = user_count;
  437.  
  438. error:
  439.     dma_free_coherent(drvdata->dev, dma_len, kbuf, dma_addr);
  440. err_unlock:
  441.     mutex_unlock(&drvdata->sem);
  442. err_clk:
  443.     clk_disable(drvdata->clk);
  444.     return status;
  445. }
  446.  
  447.  
  448. /**
  449.  * xdevcfg_read() - The is the driver read function.
  450.  * @file:   Pointer to the file structure.
  451.  * @buf:    Pointer to the bitstream location.
  452.  * @count:  The number of bytes read.
  453.  * @ppos:   Pointer to the offsetvalue
  454.  * returns: Success or error status.
  455.  */
  456. static ssize_t
  457. xdevcfg_read(struct file *file, char __user *buf, size_t count, loff_t *ppos)
  458. {
  459.     u32 *kbuf;
  460.     int status;
  461.     unsigned long timeout;
  462.     dma_addr_t dma_addr;
  463.     struct xdevcfg_drvdata *drvdata = file->private_data;
  464.     u32 intr_reg;
  465.  
  466.     status = clk_enable(drvdata->clk);
  467.     if (status)
  468.         return status;
  469.  
  470.     status = mutex_lock_interruptible(&drvdata->sem);
  471.     if (status)
  472.         goto err_clk;
  473.  
  474.     /* Get new data from the ICAP, and return was requested. */
  475.     kbuf = dma_alloc_coherent(drvdata->dev, count, &dma_addr, GFP_KERNEL);
  476.     if (!kbuf) {
  477.         status = -ENOMEM;
  478.         goto err_unlock;
  479.     }
  480.  
  481.     drvdata->dma_done = 0;
  482.     drvdata->error_status = 0;
  483.  
  484.     /* Enable DMA and error interrupts */
  485.     xdevcfg_writereg(drvdata->base_address + XDCFG_INT_STS_OFFSET,
  486.                 XDCFG_IXR_ALL_MASK);
  487.  
  488.     xdevcfg_writereg(drvdata->base_address + XDCFG_INT_MASK_OFFSET,
  489.                 (u32) (~(XDCFG_IXR_D_P_DONE_MASK |
  490.                 XDCFG_IXR_ERROR_FLAGS_MASK)));
  491.     /* Initiate DMA read command */
  492.     xdevcfg_writereg(drvdata->base_address + XDCFG_DMA_SRC_ADDR_OFFSET,
  493.                 (u32)XDCFG_DMA_INVALID_ADDRESS);
  494.     xdevcfg_writereg(drvdata->base_address + XDCFG_DMA_DEST_ADDR_OFFSET,
  495.                 (u32)dma_addr);
  496.     xdevcfg_writereg(drvdata->base_address + XDCFG_DMA_SRC_LEN_OFFSET, 0);
  497.     xdevcfg_writereg(drvdata->base_address + XDCFG_DMA_DEST_LEN_OFFSET,
  498.                 count / 4);
  499.  
  500.     timeout = jiffies + msecs_to_jiffies(1000);
  501.  
  502.     while (!drvdata->dma_done) {
  503.         if (time_after(jiffies, timeout)) {
  504.             status = -ETIMEDOUT;
  505.             goto error;
  506.         }
  507.     }
  508.  
  509.     if (drvdata->error_status)
  510.         status = drvdata->error_status;
  511.  
  512.     /* Disable and clear DMA and error interrupts */
  513.     intr_reg = xdevcfg_readreg(drvdata->base_address +
  514.                     XDCFG_INT_MASK_OFFSET);
  515.     xdevcfg_writereg(drvdata->base_address + XDCFG_INT_MASK_OFFSET,
  516.                 intr_reg | (XDCFG_IXR_D_P_DONE_MASK |
  517.                 XDCFG_IXR_ERROR_FLAGS_MASK));
  518.  
  519.  
  520.     /* If we didn't read correctly, then bail out. */
  521.     if (status) {
  522.         status = -EFAULT;
  523.         goto error;
  524.     }
  525.  
  526.     /* If we fail to return the data to the user, then bail out. */
  527.     if (copy_to_user(buf, kbuf, count)) {
  528.         status = -EFAULT;
  529.         goto error;
  530.     }
  531.  
  532.     status = count;
  533. error:
  534.     dma_free_coherent(drvdata->dev, count, kbuf, dma_addr);
  535. err_unlock:
  536.     mutex_unlock(&drvdata->sem);
  537. err_clk:
  538.     clk_disable(drvdata->clk);
  539.  
  540.     return status;
  541. }
  542.  
  543. /**
  544.  * xdevcfg_open() - The is the driver open function.
  545.  * @inode:  Pointer to the inode structure of this device.
  546.  * @file:   Pointer to the file structure.
  547.  * returns: Success or error status.
  548.  */
  549. static int xdevcfg_open(struct inode *inode, struct file *file)
  550. {
  551.     struct xdevcfg_drvdata *drvdata;
  552.     int status;
  553.  
  554.     drvdata = container_of(inode->i_cdev, struct xdevcfg_drvdata, cdev);
  555.  
  556.     status = clk_enable(drvdata->clk);
  557.     if (status)
  558.         return status;
  559.  
  560.     status = mutex_lock_interruptible(&drvdata->sem);
  561.     if (status)
  562.         goto err_clk;
  563.  
  564.     if (drvdata->is_open) {
  565.         status = -EBUSY;
  566.         goto error;
  567.     }
  568.  
  569.     file->private_data = drvdata;
  570.     drvdata->is_open = 1;
  571.     drvdata->endian_swap = 0;
  572.     drvdata->residue_len= 0;
  573.  
  574.     /*
  575.      * If is_partial_bitstream is set, then PROG_B is not asserted
  576.      * (xdevcfg_reset_pl function) and also zynq_slcr_init_preload_fpga and
  577.      * zynq_slcr_init_postload_fpga functions are not invoked.
  578.      */
  579.     if (!drvdata->is_partial_bitstream)
  580.         zynq_slcr_init_preload_fpga();
  581.  
  582.     /*
  583.      * Only do the reset of the PL for Zynq as it causes problems on the
  584.      * EP107 and the issue is not understood, but not worth investigating
  585.      * as the emulation platform is very different than silicon and not a
  586.      * complete implementation. Also, do not reset if it is a partial
  587.      * bitstream.
  588.      */
  589.     if ((!drvdata->ep107) && (!drvdata->is_partial_bitstream))
  590.         xdevcfg_reset_pl(drvdata->base_address);
  591.  
  592.     xdevcfg_writereg(drvdata->base_address + XDCFG_INT_STS_OFFSET,
  593.             XDCFG_IXR_PCFG_DONE_MASK);
  594.  
  595. error:
  596.     mutex_unlock(&drvdata->sem);
  597. err_clk:
  598.     clk_disable(drvdata->clk);
  599.     return status;
  600. }
  601.  
  602. /**
  603.  * xdevcfg_release() - The is the driver release function.
  604.  * @inode:  Pointer to the inode structure of this device.
  605.  * @file:   Pointer to the file structure.
  606.  * returns: Success.
  607.  */
  608. static int xdevcfg_release(struct inode *inode, struct file *file)
  609. {
  610.     struct xdevcfg_drvdata *drvdata = file->private_data;
  611.  
  612.     if (!drvdata->is_partial_bitstream)
  613.         zynq_slcr_init_postload_fpga();
  614.  
  615.     if (drvdata->residue_len)
  616.         printk("Did not transfer last %d bytes\n",
  617.             drvdata->residue_len);
  618.  
  619.     drvdata->is_open = 0;
  620.  
  621.     return 0;
  622. }
  623.  
  624. static const struct file_operations xdevcfg_fops = {
  625.     .owner = THIS_MODULE,
  626.     .write = xdevcfg_write,
  627.     .read = xdevcfg_read,
  628.     .open = xdevcfg_open,
  629.     .release = xdevcfg_release,
  630. };
  631.  
  632. /*
  633.  * The following functions are the routines provided to the user to
  634.  * set/get the status bit value in the control/lock registers.
  635.  */
  636.  
  637. /**
  638.  * xdevcfg_set_dap_en() - This function sets the DAP bits in the
  639.  * control register with the given value.
  640.  * @dev:    Pointer to the device structure.
  641.  * @attr:   Pointer to the device attribute structure.
  642.  * @buf:    Pointer to the buffer location for the configuration
  643.  *      data.
  644.  * @size:   The number of bytes used from the buffer
  645.  * returns: negative error if the string could not be converted
  646.  *      or the size of the buffer.
  647.  */
  648. static ssize_t xdevcfg_set_dap_en(struct device *dev,
  649.         struct device_attribute *attr, const char *buf, size_t size)
  650. {
  651.     u32 ctrl_reg_status;
  652.     unsigned long flags;
  653.     unsigned long mask_bit;
  654.     int status;
  655.     struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev);
  656.  
  657.     status = clk_enable(drvdata->clk);
  658.     if (status)
  659.         return status;
  660.  
  661.     ctrl_reg_status = xdevcfg_readreg(drvdata->base_address +
  662.                 XDCFG_CTRL_OFFSET);
  663.     spin_lock_irqsave(&drvdata->lock, flags);
  664.  
  665.     status = strict_strtoul(buf, 10, &mask_bit);
  666.  
  667.     if (status)
  668.         goto err_unlock;
  669.  
  670.     if (mask_bit > 7) {
  671.         status = -EINVAL;
  672.         goto err_unlock;
  673.     }
  674.  
  675.     xdevcfg_writereg(drvdata->base_address + XDCFG_CTRL_OFFSET,
  676.             (ctrl_reg_status |
  677.              (((u32)mask_bit) & XDCFG_CTRL_DAP_EN_MASK)));
  678.  
  679.     spin_unlock_irqrestore(&drvdata->lock, flags);
  680.  
  681.     clk_disable(drvdata->clk);
  682.  
  683.     return size;
  684.  
  685. err_unlock:
  686.     spin_unlock_irqrestore(&drvdata->lock, flags);
  687.     clk_disable(drvdata->clk);
  688.  
  689.     return status;
  690. }
  691.  
  692. /**
  693.  * xdevcfg_show_dap_en_status() - The function returns the DAP_EN bits status in
  694.  * the control register.
  695.  * @dev:    Pointer to the device structure.
  696.  * @attr:   Pointer to the device attribute structure.
  697.  * @buf:    Pointer to the buffer location for the configuration
  698.  *      data.
  699.  * returns: Size of the buffer.
  700.  */
  701. static ssize_t xdevcfg_show_dap_en_status(struct device *dev,
  702.         struct device_attribute *attr, char *buf)
  703. {
  704.     u32 dap_en_status;
  705.     int status;
  706.     struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev);
  707.  
  708.     status = clk_enable(drvdata->clk);
  709.     if (status)
  710.         return status;
  711.  
  712.     dap_en_status = xdevcfg_readreg(drvdata->base_address +
  713.                 XDCFG_CTRL_OFFSET) & XDCFG_CTRL_DAP_EN_MASK;
  714.  
  715.     clk_disable(drvdata->clk);
  716.  
  717.     status = sprintf(buf, "%d\n", dap_en_status);
  718.  
  719.     return status;
  720. }
  721.  
  722. static DEVICE_ATTR(enable_dap, 0644, xdevcfg_show_dap_en_status,
  723.                 xdevcfg_set_dap_en);
  724.  
  725. /**
  726.  * xdevcfg_set_dbgen() - This function sets the DBGEN bit in the
  727.  * control register with the given value.
  728.  * @dev:    Pointer to the device structure.
  729.  * @attr:   Pointer to the device attribute structure.
  730.  * @buf:    Pointer to the buffer location for the configuration
  731.  *      data.
  732.  * @size:   The number of bytes used from the buffer
  733.  * returns: -EINVAL if invalid parameter is sent or size
  734.  */
  735. static ssize_t xdevcfg_set_dbgen(struct device *dev,
  736.         struct device_attribute *attr, const char *buf, size_t size)
  737. {
  738.     u32 ctrl_reg_status;
  739.     unsigned long flags;
  740.     unsigned long mask_bit;
  741.     int status;
  742.     struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev);
  743.  
  744.     status = clk_enable(drvdata->clk);
  745.     if (status)
  746.         return status;
  747.  
  748.     ctrl_reg_status = xdevcfg_readreg(drvdata->base_address +
  749.                 XDCFG_CTRL_OFFSET);
  750.  
  751.     status = strict_strtoul(buf, 10, &mask_bit);
  752.  
  753.     if (status)
  754.         goto err_clk;
  755.  
  756.     if (mask_bit > 1) {
  757.         status = -EINVAL;
  758.         goto err_clk;
  759.     }
  760.  
  761.     spin_lock_irqsave(&drvdata->lock, flags);
  762.  
  763.     if (mask_bit)
  764.         xdevcfg_writereg(drvdata->base_address + XDCFG_CTRL_OFFSET,
  765.                 (ctrl_reg_status | XDCFG_CTRL_DBGEN_MASK));
  766.     else
  767.         xdevcfg_writereg(drvdata->base_address + XDCFG_CTRL_OFFSET,
  768.                 (ctrl_reg_status & (~XDCFG_CTRL_DBGEN_MASK)));
  769.  
  770.     spin_unlock_irqrestore(&drvdata->lock, flags);
  771.  
  772.     clk_disable(drvdata->clk);
  773.  
  774.     return size;
  775.  
  776. err_clk:
  777.     clk_disable(drvdata->clk);
  778.  
  779.     return status;
  780. }
  781.  
  782. /**
  783.  * xdevcfg_show_dbgen_status() - The function returns the DBGEN bit status in
  784.  * the control register.
  785.  * @dev:    Pointer to the device structure.
  786.  * @attr:   Pointer to the device attribute structure.
  787.  * @buf:    Pointer to the buffer location for the configuration
  788.  *      data.
  789.  * returns: Size of the buffer.
  790.  */
  791. static ssize_t xdevcfg_show_dbgen_status(struct device *dev,
  792.         struct device_attribute *attr, char *buf)
  793. {
  794.     u32 dbgen_status;
  795.     ssize_t status;
  796.     struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev);
  797.  
  798.     status = clk_enable(drvdata->clk);
  799.     if (status)
  800.         return status;
  801.  
  802.     dbgen_status = xdevcfg_readreg(drvdata->base_address +
  803.                 XDCFG_CTRL_OFFSET) & XDCFG_CTRL_DBGEN_MASK;
  804.  
  805.     clk_disable(drvdata->clk);
  806.  
  807.     status = sprintf(buf, "%d\n", (dbgen_status >> 3));
  808.  
  809.     return status;
  810. }
  811.  
  812. static DEVICE_ATTR(enable_dbg_in, 0644, xdevcfg_show_dbgen_status,
  813.                 xdevcfg_set_dbgen);
  814.  
  815. /**
  816.  * xdevcfg_set_niden() - This function sets the NIDEN bit in the
  817.  * control register with the given value.
  818.  * @dev:    Pointer to the device structure.
  819.  * @attr:   Pointer to the device attribute structure.
  820.  * @buf:    Pointer to the buffer location for the configuration
  821.  *      data.
  822.  * @size:   The number of bytes used from the buffer
  823.  * returns: -EINVAL if invalid parameter is sent or size
  824.  */
  825. static ssize_t xdevcfg_set_niden(struct device *dev,
  826.         struct device_attribute *attr, const char *buf, size_t size)
  827. {
  828.     u32 ctrl_reg_status;
  829.     unsigned long flags;
  830.     unsigned long mask_bit;
  831.     int status;
  832.     struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev);
  833.  
  834.     status = clk_enable(drvdata->clk);
  835.     if (status)
  836.         return status;
  837.  
  838.     ctrl_reg_status = xdevcfg_readreg(drvdata->base_address +
  839.                 XDCFG_CTRL_OFFSET);
  840.  
  841.     status = strict_strtoul(buf, 10, &mask_bit);
  842.  
  843.     if (status)
  844.         goto err_clk;
  845.  
  846.     if (mask_bit > 1) {
  847.         status = -EINVAL;
  848.         goto err_clk;
  849.     }
  850.  
  851.     spin_lock_irqsave(&drvdata->lock, flags);
  852.  
  853.     if (mask_bit)
  854.         xdevcfg_writereg(drvdata->base_address + XDCFG_CTRL_OFFSET,
  855.                 (ctrl_reg_status | XDCFG_CTRL_NIDEN_MASK));
  856.     else
  857.         xdevcfg_writereg(drvdata->base_address + XDCFG_CTRL_OFFSET,
  858.                 (ctrl_reg_status & (~XDCFG_CTRL_NIDEN_MASK)));
  859.  
  860.     spin_unlock_irqrestore(&drvdata->lock, flags);
  861.  
  862.     clk_disable(drvdata->clk);
  863.  
  864.     return size;
  865.  
  866. err_clk:
  867.     clk_disable(drvdata->clk);
  868.  
  869.     return status;
  870. }
  871.  
  872. /**
  873.  * xdevcfg_show_niden_status() - The function returns the NIDEN bit status in
  874.  * the control register.
  875.  * @dev:    Pointer to the device structure.
  876.  * @attr:   Pointer to the device attribute structure.
  877.  * @buf:    Pointer to the buffer location for the configuration
  878.  *      data.
  879.  * returns: Size of the buffer.
  880.  */
  881. static ssize_t xdevcfg_show_niden_status(struct device *dev,
  882.         struct device_attribute *attr, char *buf)
  883. {
  884.     u32 niden_status;
  885.     ssize_t status;
  886.     struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev);
  887.  
  888.     status = clk_enable(drvdata->clk);
  889.     if (status)
  890.         return status;
  891.  
  892.     niden_status = xdevcfg_readreg(drvdata->base_address +
  893.                 XDCFG_CTRL_OFFSET) & XDCFG_CTRL_NIDEN_MASK;
  894.  
  895.     clk_disable(drvdata->clk);
  896.  
  897.     status = sprintf(buf, "%d\n", (niden_status >> 4));
  898.  
  899.     return status;
  900. }
  901.  
  902. static DEVICE_ATTR(enable_dbg_nonin, 0644, xdevcfg_show_niden_status,
  903.             xdevcfg_set_niden);
  904.  
  905. /**
  906.  * xdevcfg_set_spiden() - This function sets the SPIDEN bit in the
  907.  * control register with the given value.
  908.  * @dev:    Pointer to the device structure.
  909.  * @attr:   Pointer to the device attribute structure.
  910.  * @buf:    Pointer to the buffer location for the configuration
  911.  *      data.
  912.  * @size:   The number of bytes used from the buffer
  913.  * returns: -EINVAL if invalid parameter is sent or size
  914.  */
  915. static ssize_t xdevcfg_set_spiden(struct device *dev,
  916.         struct device_attribute *attr, const char *buf, size_t size)
  917. {
  918.     u32 ctrl_reg_status;
  919.     unsigned long flags;
  920.     unsigned long mask_bit;
  921.     int status;
  922.     struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev);
  923.  
  924.     status = clk_enable(drvdata->clk);
  925.     if (status)
  926.         return status;
  927.  
  928.     ctrl_reg_status = xdevcfg_readreg(drvdata->base_address +
  929.                 XDCFG_CTRL_OFFSET);
  930.  
  931.     status = strict_strtoul(buf, 10, &mask_bit);
  932.  
  933.     if (status)
  934.         goto err_clk;
  935.  
  936.     if (mask_bit > 1) {
  937.         status = -EINVAL;
  938.         goto err_clk;
  939.     }
  940.  
  941.     spin_lock_irqsave(&drvdata->lock, flags);
  942.  
  943.     if (mask_bit)
  944.         xdevcfg_writereg(drvdata->base_address + XDCFG_CTRL_OFFSET,
  945.                 (ctrl_reg_status | XDCFG_CTRL_SPIDEN_MASK));
  946.     else
  947.  
  948.         xdevcfg_writereg(drvdata->base_address + XDCFG_CTRL_OFFSET,
  949.                 (ctrl_reg_status & (~XDCFG_CTRL_SPIDEN_MASK)));
  950.  
  951.     spin_unlock_irqrestore(&drvdata->lock, flags);
  952.  
  953.     clk_disable(drvdata->clk);
  954.  
  955.     return size;
  956.  
  957. err_clk:
  958.     clk_disable(drvdata->clk);
  959.  
  960.     return status;
  961. }
  962.  
  963. /**
  964.  * xdevcfg_show_spiden_status() - The function returns the SPIDEN bit status in
  965.  * the control register.
  966.  * @dev:    Pointer to the device structure.
  967.  * @attr:   Pointer to the device attribute structure.
  968.  * @buf:    Pointer to the buffer location for the configuration
  969.  *      data.
  970.  * returns: Size of the buffer.
  971.  */
  972. static ssize_t xdevcfg_show_spiden_status(struct device *dev,
  973.         struct device_attribute *attr, char *buf)
  974. {
  975.     u32 spiden_status;
  976.     ssize_t status;
  977.     struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev);
  978.  
  979.     status = clk_enable(drvdata->clk);
  980.     if (status)
  981.         return status;
  982.  
  983.     spiden_status = xdevcfg_readreg(drvdata->base_address +
  984.             XDCFG_CTRL_OFFSET) & XDCFG_CTRL_SPIDEN_MASK;
  985.  
  986.     clk_disable(drvdata->clk);
  987.  
  988.     status = sprintf(buf, "%d\n", (spiden_status >> 5));
  989.  
  990.     return status;
  991. }
  992.  
  993. static DEVICE_ATTR(enable_sec_dbg_in, 0644, xdevcfg_show_spiden_status,
  994.                 xdevcfg_set_spiden);
  995.  
  996. /**
  997.  * xdevcfg_set_spniden() - This function sets the SPNIDEN bit in the
  998.  * control register with the given value.
  999.  * @dev:    Pointer to the device structure.
  1000.  * @attr:   Pointer to the device attribute structure.
  1001.  * @buf:    Pointer to the buffer location for the configuration
  1002.  *      data.
  1003.  * @size:   The number of bytes used from the buffer
  1004.  * returns: -EINVAL if invalid parameter is sent or the size of buffer
  1005.  */
  1006. static ssize_t xdevcfg_set_spniden(struct device *dev,
  1007.         struct device_attribute *attr, const char *buf, size_t size)
  1008. {
  1009.     u32 ctrl_reg_status;
  1010.     unsigned long flags;
  1011.     unsigned long mask_bit;
  1012.     ssize_t status;
  1013.     struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev);
  1014.  
  1015.     status = clk_enable(drvdata->clk);
  1016.     if (status)
  1017.         return status;
  1018.  
  1019.     ctrl_reg_status = xdevcfg_readreg(drvdata->base_address +
  1020.                 XDCFG_CTRL_OFFSET);
  1021.     status = strict_strtoul(buf, 10, &mask_bit);
  1022.  
  1023.     if (status)
  1024.         goto err_clk;
  1025.  
  1026.     if (mask_bit > 1) {
  1027.         status = -EINVAL;
  1028.         goto err_clk;
  1029.     }
  1030.  
  1031.     spin_lock_irqsave(&drvdata->lock, flags);
  1032.  
  1033.     if (mask_bit)
  1034.         xdevcfg_writereg(drvdata->base_address + XDCFG_CTRL_OFFSET,
  1035.                 (ctrl_reg_status | XDCFG_CTRL_SPNIDEN_MASK));
  1036.     else
  1037.         xdevcfg_writereg(drvdata->base_address + XDCFG_CTRL_OFFSET,
  1038.                 (ctrl_reg_status & (~XDCFG_CTRL_SPNIDEN_MASK)));
  1039.  
  1040.     spin_unlock_irqrestore(&drvdata->lock, flags);
  1041.  
  1042.     clk_disable(drvdata->clk);
  1043.  
  1044.     return size;
  1045.  
  1046. err_clk:
  1047.     clk_disable(drvdata->clk);
  1048.  
  1049.     return status;
  1050. }
  1051.  
  1052. /**
  1053.  * xdevcfg_show_spniden_status() - The function returns the SPNIDEN bit status
  1054.  * in the control register.
  1055.  * @dev:    Pointer to the device structure.
  1056.  * @attr:   Pointer to the device attribute structure.
  1057.  * @buf:    Pointer to the buffer location for the configuration
  1058.  *      data.
  1059.  * returns: Size of the buffer.
  1060.  */
  1061. static ssize_t xdevcfg_show_spniden_status(struct device *dev,
  1062.         struct device_attribute *attr, char *buf)
  1063. {
  1064.     u32 spniden_status;
  1065.     ssize_t status;
  1066.     struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev);
  1067.  
  1068.     status = clk_enable(drvdata->clk);
  1069.     if (status)
  1070.         return status;
  1071.  
  1072.     spniden_status = xdevcfg_readreg(drvdata->base_address +
  1073.             XDCFG_CTRL_OFFSET) & XDCFG_CTRL_SPNIDEN_MASK;
  1074.  
  1075.     clk_disable(drvdata->clk);
  1076.  
  1077.     status = sprintf(buf, "%d\n", (spniden_status >> 6));
  1078.  
  1079.     return status;
  1080. }
  1081.  
  1082. static DEVICE_ATTR(enable_sec_dbg_nonin, 0644, xdevcfg_show_spniden_status,
  1083.                     xdevcfg_set_spniden);
  1084.  
  1085. /**
  1086.  * xdevcfg_set_seu() - This function sets the SEU_EN bit in the
  1087.  * control register with the given value
  1088.  * @dev:    Pointer to the device structure.
  1089.  * @attr:   Pointer to the device attribute structure.
  1090.  * @buf:    Pointer to the buffer location for the configuration
  1091.  *      data.
  1092.  * @size:   The number of bytes used from the buffer
  1093.  * returns: -EINVAL if invalid parameter is sent or size
  1094.  */
  1095. static ssize_t xdevcfg_set_seu(struct device *dev,
  1096.         struct device_attribute *attr, const char *buf, size_t size)
  1097. {
  1098.     u32 ctrl_reg_status;
  1099.     unsigned long flags;
  1100.     unsigned long mask_bit;
  1101.     ssize_t status;
  1102.     struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev);
  1103.  
  1104.     status = clk_enable(drvdata->clk);
  1105.     if (status)
  1106.         return status;
  1107.  
  1108.     ctrl_reg_status = xdevcfg_readreg(drvdata->base_address +
  1109.                 XDCFG_CTRL_OFFSET);
  1110.  
  1111.     status = strict_strtoul(buf, 10, &mask_bit);
  1112.  
  1113.     if (status)
  1114.         goto err_clk;
  1115.  
  1116.     if (mask_bit > 1) {
  1117.         status = -EINVAL;
  1118.         goto err_clk;
  1119.     }
  1120.  
  1121.     spin_lock_irqsave(&drvdata->lock, flags);
  1122.  
  1123.     if (mask_bit)
  1124.         xdevcfg_writereg(drvdata->base_address + XDCFG_CTRL_OFFSET,
  1125.                 (ctrl_reg_status | XDCFG_CTRL_SEU_EN_MASK));
  1126.     else
  1127.         xdevcfg_writereg(drvdata->base_address + XDCFG_CTRL_OFFSET,
  1128.                 (ctrl_reg_status & (~XDCFG_CTRL_SEU_EN_MASK)));
  1129.  
  1130.     spin_unlock_irqrestore(&drvdata->lock, flags);
  1131.  
  1132.     clk_disable(drvdata->clk);
  1133.  
  1134.     return size;
  1135.  
  1136. err_clk:
  1137.     clk_disable(drvdata->clk);
  1138.  
  1139.     return status;
  1140. }
  1141.  
  1142. /**
  1143.  * xdevcfg_show_seu_status() - The function returns the SEU_EN bit status
  1144.  * in the control register.
  1145.  * @dev:    Pointer to the device structure.
  1146.  * @attr:   Pointer to the device attribute structure.
  1147.  * @buf:    Pointer to the buffer location for the configuration
  1148.  *      data.
  1149.  * returns: size of the buffer.
  1150.  */
  1151. static ssize_t xdevcfg_show_seu_status(struct device *dev,
  1152.         struct device_attribute *attr, char *buf)
  1153. {
  1154.     u32 seu_status;
  1155.     ssize_t status;
  1156.     struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev);
  1157.  
  1158.     status = clk_enable(drvdata->clk);
  1159.     if (status)
  1160.         return status;
  1161.  
  1162.     seu_status = xdevcfg_readreg(drvdata->base_address +
  1163.             XDCFG_CTRL_OFFSET) & XDCFG_CTRL_SEU_EN_MASK;
  1164.  
  1165.     clk_disable(drvdata->clk);
  1166.  
  1167.     status = sprintf(buf, "%d\n", (seu_status > 8));
  1168.  
  1169.     return status;
  1170. }
  1171.  
  1172. static DEVICE_ATTR(enable_seu, 0644, xdevcfg_show_seu_status, xdevcfg_set_seu);
  1173.  
  1174. /**
  1175.  * xdevcfg_set_aes() - This function sets the AES_EN bits in the
  1176.  * control register with either all 1s or all 0s.
  1177.  * @dev:    Pointer to the device structure.
  1178.  * @attr:   Pointer to the device attribute structure.
  1179.  * @buf:    Pointer to the buffer location for the configuration
  1180.  *      data.
  1181.  * @size:   The number of bytes used from the buffer
  1182.  * returns: -EINVAL if invalid parameter is sent or size
  1183.  *
  1184.  * The user must send only one bit in the buffer to notify whether he wants to
  1185.  * either set or reset these bits.
  1186.  */
  1187. static ssize_t xdevcfg_set_aes(struct device *dev,
  1188.         struct device_attribute *attr, const char *buf, size_t size)
  1189. {
  1190.     u32 ctrl_reg_status;
  1191.     unsigned long flags;
  1192.     unsigned long mask_bit;
  1193.     int status;
  1194.     struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev);
  1195.  
  1196.     status = clk_enable(drvdata->clk);
  1197.     if (status)
  1198.         return status;
  1199.  
  1200.     ctrl_reg_status = xdevcfg_readreg(drvdata->base_address +
  1201.                 XDCFG_CTRL_OFFSET);
  1202.  
  1203.     status = strict_strtoul(buf, 10, &mask_bit);
  1204.  
  1205.     if (status < 0)
  1206.         goto err_clk;
  1207.  
  1208.     if (mask_bit > 1) {
  1209.         status = -EINVAL;
  1210.         goto err_clk;
  1211.     }
  1212.  
  1213.  
  1214.     spin_lock_irqsave(&drvdata->lock, flags);
  1215.  
  1216.     if (mask_bit)
  1217.         xdevcfg_writereg(drvdata->base_address + XDCFG_CTRL_OFFSET,
  1218.                 (ctrl_reg_status |
  1219.                  XDCFG_CTRL_PCFG_AES_EN_MASK |
  1220.                  XDCFG_CTRL_PCAP_RATE_EN_MASK));
  1221.     else
  1222.         xdevcfg_writereg(drvdata->base_address + XDCFG_CTRL_OFFSET,
  1223.                 (ctrl_reg_status &
  1224.                  ~(XDCFG_CTRL_PCFG_AES_EN_MASK |
  1225.                  XDCFG_CTRL_PCAP_RATE_EN_MASK)));
  1226.  
  1227.     spin_unlock_irqrestore(&drvdata->lock, flags);
  1228.  
  1229.     clk_disable(drvdata->clk);
  1230.  
  1231.     return size;
  1232.  
  1233. err_clk:
  1234.     clk_disable(drvdata->clk);
  1235.  
  1236.     return status;
  1237. }
  1238.  
  1239. /**
  1240.  * xdevcfg_show_aes_status() - The function returns the AES_EN bit status
  1241.  * in the control register.
  1242.  * @dev:    Pointer to the device structure.
  1243.  * @attr:   Pointer to the device attribute structure.
  1244.  * @buf:    Pointer to the buffer location for the configuration
  1245.  *      data.
  1246.  * returns: size of the buffer.
  1247.  */
  1248. static ssize_t xdevcfg_show_aes_status(struct device *dev,
  1249.         struct device_attribute *attr, char *buf)
  1250. {
  1251.     u32 aes_status;
  1252.     ssize_t status;
  1253.     struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev);
  1254.  
  1255.     status = clk_enable(drvdata->clk);
  1256.     if (status)
  1257.         return status;
  1258.  
  1259.     aes_status = xdevcfg_readreg(drvdata->base_address +
  1260.             XDCFG_CTRL_OFFSET) & XDCFG_CTRL_PCFG_AES_EN_MASK;
  1261.  
  1262.     clk_disable(drvdata->clk);
  1263.  
  1264.     status = sprintf(buf, "%d\n", (aes_status >> 9));
  1265.  
  1266.     return status;
  1267. }
  1268.  
  1269. static DEVICE_ATTR(enable_aes, 0644, xdevcfg_show_aes_status, xdevcfg_set_aes);
  1270.  
  1271. /**
  1272.  * xdevcfg_set_aes_en_lock() - This function sets the LOCK_AES_EN bit in the
  1273.  * lock register.
  1274.  * @dev:    Pointer to the device structure.
  1275.  * @attr:   Pointer to the device attribute structure.
  1276.  * @buf:    Pointer to the buffer location for the configuration
  1277.  *      data.
  1278.  * @size:   The number of bytes used from the buffer
  1279.  * returns: -EINVAL if invalid parameter is sent or size
  1280.  */
  1281. static ssize_t xdevcfg_set_aes_en_lock(struct device *dev,
  1282.         struct device_attribute *attr, const char *buf, size_t size)
  1283. {
  1284.     u32 aes_en_lock_status;
  1285.     unsigned long flags;
  1286.     unsigned long mask_bit;
  1287.     ssize_t status;
  1288.     struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev);
  1289.  
  1290.     status = clk_enable(drvdata->clk);
  1291.     if (status)
  1292.         return status;
  1293.  
  1294.     aes_en_lock_status = xdevcfg_readreg(drvdata->base_address +
  1295.                 XDCFG_LOCK_OFFSET);
  1296.  
  1297.     status = strict_strtoul(buf, 10, &mask_bit);
  1298.  
  1299.     if (status)
  1300.         goto err_clk;
  1301.  
  1302.     if (mask_bit > 1) {
  1303.         status = -EINVAL;
  1304.         goto err_clk;
  1305.     }
  1306.  
  1307.     spin_lock_irqsave(&drvdata->lock, flags);
  1308.  
  1309.     if (mask_bit)
  1310.         xdevcfg_writereg(drvdata->base_address + XDCFG_LOCK_OFFSET,
  1311.                 (aes_en_lock_status | XDCFG_LOCK_AES_EN_MASK));
  1312.     else
  1313.         xdevcfg_writereg(drvdata->base_address + XDCFG_LOCK_OFFSET,
  1314.                 (aes_en_lock_status &
  1315.                  (~XDCFG_LOCK_AES_EN_MASK)));
  1316.  
  1317.     spin_unlock_irqrestore(&drvdata->lock, flags);
  1318.  
  1319.     clk_disable(drvdata->clk);
  1320.  
  1321.     return size;
  1322.  
  1323. err_clk:
  1324.     clk_disable(drvdata->clk);
  1325.  
  1326.     return status;
  1327. }
  1328.  
  1329. /**
  1330.  * xdevcfg_show_aes_en_lock_status() - The function returns the LOCK_AES_EN bit
  1331.  * status in the lock register.
  1332.  * @dev:    Pointer to the device structure.
  1333.  * @attr:   Pointer to the device attribute structure.
  1334.  * @buf:    Pointer to the buffer location for the configuration
  1335.  *      data.
  1336.  * returns: size of the buffer.
  1337.  */
  1338. static ssize_t xdevcfg_show_aes_en_lock_status(struct device *dev,
  1339.         struct device_attribute *attr, char *buf)
  1340. {
  1341.     u32 aes_en_lock_status;
  1342.     ssize_t status;
  1343.     struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev);
  1344.  
  1345.     status = clk_enable(drvdata->clk);
  1346.     if (status)
  1347.         return status;
  1348.  
  1349.     aes_en_lock_status = xdevcfg_readreg(drvdata->base_address +
  1350.             XDCFG_LOCK_OFFSET) & XDCFG_LOCK_AES_EN_MASK;
  1351.  
  1352.     clk_disable(drvdata->clk);
  1353.  
  1354.     status = sprintf(buf, "%d\n", (aes_en_lock_status >> 3));
  1355.  
  1356.     return status;
  1357. }
  1358.  
  1359. static DEVICE_ATTR(aes_en_lock, 0644, xdevcfg_show_aes_en_lock_status,
  1360.                 xdevcfg_set_aes_en_lock);
  1361.  
  1362. /**
  1363.  * xdevcfg_set_seu_lock() - This function sets the LOCK_SEU bit in the
  1364.  * lock register.
  1365.  * @dev:    Pointer to the device structure.
  1366.  * @attr:   Pointer to the device attribute structure.
  1367.  * @buf:    Pointer to the buffer location for the configuration
  1368.  *      data.
  1369.  * @size:   The number of bytes used from the buffer
  1370.  * returns: -EINVAL if invalid parameter is sent or size
  1371.  */
  1372. static ssize_t xdevcfg_set_seu_lock(struct device *dev,
  1373.         struct device_attribute *attr, const char *buf, size_t size)
  1374. {
  1375.     u32 seu_lock_status;
  1376.     unsigned long flags;
  1377.     unsigned long mask_bit;
  1378.     ssize_t status;
  1379.     struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev);
  1380.  
  1381.     status = clk_enable(drvdata->clk);
  1382.     if (status)
  1383.         return status;
  1384.  
  1385.     seu_lock_status = xdevcfg_readreg(drvdata->base_address +
  1386.                 XDCFG_LOCK_OFFSET);
  1387.  
  1388.     status = strict_strtoul(buf, 10, &mask_bit);
  1389.  
  1390.     if (status)
  1391.         goto err_clk;
  1392.  
  1393.     if (mask_bit > 1) {
  1394.         status = -EINVAL;
  1395.         goto err_clk;
  1396.     }
  1397.  
  1398.     spin_lock_irqsave(&drvdata->lock, flags);
  1399.  
  1400.     if (mask_bit)
  1401.         xdevcfg_writereg(drvdata->base_address + XDCFG_LOCK_OFFSET,
  1402.                 (seu_lock_status | XDCFG_LOCK_SEU_MASK));
  1403.     else
  1404.         xdevcfg_writereg(drvdata->base_address + XDCFG_LOCK_OFFSET,
  1405.                 (seu_lock_status  & (~XDCFG_LOCK_SEU_MASK)));
  1406.  
  1407.     spin_unlock_irqrestore(&drvdata->lock, flags);
  1408.  
  1409.     clk_disable(drvdata->clk);
  1410.  
  1411.     return size;
  1412.  
  1413. err_clk:
  1414.     clk_disable(drvdata->clk);
  1415.  
  1416.     return status;
  1417. }
  1418.  
  1419. /**
  1420.  * xdevcfg_show_seu_lock_status() - The function returns the LOCK_SEU bit
  1421.  * status in the lock register.
  1422.  * @dev:    Pointer to the device structure.
  1423.  * @attr:   Pointer to the device attribute structure.
  1424.  * @buf:    Pointer to the buffer location for the configuration
  1425.  *      data.
  1426.  * returns: size of the buffer.
  1427.  */
  1428. static ssize_t xdevcfg_show_seu_lock_status(struct device *dev,
  1429.         struct device_attribute *attr, char *buf)
  1430. {
  1431.     u32 seu_lock_status;
  1432.     ssize_t status;
  1433.     struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev);
  1434.  
  1435.     status = clk_enable(drvdata->clk);
  1436.     if (status)
  1437.         return status;
  1438.  
  1439.     seu_lock_status = xdevcfg_readreg(drvdata->base_address +
  1440.             XDCFG_LOCK_OFFSET) & XDCFG_LOCK_SEU_MASK;
  1441.  
  1442.     clk_disable(drvdata->clk);
  1443.  
  1444.     status = sprintf(buf, "%d\n", (seu_lock_status >> 2));
  1445.  
  1446.     return status;
  1447. }
  1448.  
  1449. static DEVICE_ATTR(seu_lock, 0644, xdevcfg_show_seu_lock_status,
  1450.                     xdevcfg_set_seu_lock);
  1451.  
  1452. /**
  1453.  * xdevcfg_set_dbg_lock() - This function sets the LOCK_DBG bit in the
  1454.  * lock register.
  1455.  * @dev:    Pointer to the device structure.
  1456.  * @attr:   Pointer to the device attribute structure.
  1457.  * @buf:    Pointer to the buffer location for the configuration
  1458.  *      data.
  1459.  * @size:   The number of bytes used from the buffer
  1460.  * returns: -EINVAL if invalid parameter is sent or size
  1461.  */
  1462. static ssize_t xdevcfg_set_dbg_lock(struct device *dev,
  1463.         struct device_attribute *attr, const char *buf, size_t size)
  1464. {
  1465.     u32 lock_reg_status;
  1466.     unsigned long flags;
  1467.     unsigned long mask_bit;
  1468.     ssize_t status;
  1469.     struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev);
  1470.  
  1471.     status = clk_enable(drvdata->clk);
  1472.     if (status)
  1473.         return status;
  1474.  
  1475.     lock_reg_status = xdevcfg_readreg(drvdata->base_address +
  1476.                 XDCFG_LOCK_OFFSET);
  1477.     status = strict_strtoul(buf, 10, &mask_bit);
  1478.  
  1479.     if (status)
  1480.         goto err_clk;
  1481.  
  1482.     if (mask_bit > 1) {
  1483.         status = -EINVAL;
  1484.         goto err_clk;
  1485.     }
  1486.  
  1487.     spin_lock_irqsave(&drvdata->lock, flags);
  1488.  
  1489.     if (mask_bit)
  1490.         xdevcfg_writereg(drvdata->base_address + XDCFG_LOCK_OFFSET,
  1491.                 (lock_reg_status | XDCFG_LOCK_DBG_MASK));
  1492.     else
  1493.         xdevcfg_writereg(drvdata->base_address + XDCFG_LOCK_OFFSET,
  1494.                 (lock_reg_status & (~XDCFG_LOCK_DBG_MASK)));
  1495.  
  1496.     spin_unlock_irqrestore(&drvdata->lock, flags);
  1497.  
  1498.     clk_disable(drvdata->clk);
  1499.  
  1500.     return size;
  1501.  
  1502. err_clk:
  1503.     clk_disable(drvdata->clk);
  1504.  
  1505.     return status;
  1506. }
  1507.  
  1508. /**
  1509.  * xdevcfg_show_dbg_lock_status() - The function returns the LOCK_DBG bit
  1510.  * status in the lock register.
  1511.  * @dev:    Pointer to the device structure.
  1512.  * @attr:   Pointer to the device attribute structure.
  1513.  * @buf:    Pointer to the buffer location for the configuration
  1514.  *      data.
  1515.  * returns: size of the buffer.
  1516.  */
  1517. static ssize_t xdevcfg_show_dbg_lock_status(struct device *dev,
  1518.         struct device_attribute *attr, char *buf)
  1519. {
  1520.     u32 dbg_lock_status;
  1521.     ssize_t status;
  1522.     struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev);
  1523.  
  1524.     status = clk_enable(drvdata->clk);
  1525.     if (status)
  1526.         return status;
  1527.  
  1528.     dbg_lock_status = xdevcfg_readreg(drvdata->base_address +
  1529.             XDCFG_LOCK_OFFSET) & XDCFG_LOCK_DBG_MASK;
  1530.  
  1531.     clk_disable(drvdata->clk);
  1532.  
  1533.     status = sprintf(buf, "%d\n", dbg_lock_status);
  1534.  
  1535.     return status;
  1536. }
  1537.  
  1538. static DEVICE_ATTR(dbg_lock, 0644, xdevcfg_show_dbg_lock_status,
  1539.                 xdevcfg_set_dbg_lock);
  1540.  
  1541. /**
  1542.  * xdevcfg_show_prog_done_status() - The function returns the PROG_DONE bit
  1543.  * status in the interrupt status register.
  1544.  * @dev:    Pointer to the device structure.
  1545.  * @attr:   Pointer to the device attribute structure.
  1546.  * @buf:    Pointer to the buffer location for the configuration
  1547.  *      data.
  1548.  * returns: size of the buffer.
  1549.  */
  1550. static ssize_t xdevcfg_show_prog_done_status(struct device *dev,
  1551.         struct device_attribute *attr, char *buf)
  1552. {
  1553.     u32 prog_done_status;
  1554.     ssize_t status;
  1555.     struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev);
  1556.  
  1557.     status = clk_enable(drvdata->clk);
  1558.     if (status)
  1559.         return status;
  1560.  
  1561.     prog_done_status = xdevcfg_readreg(drvdata->base_address +
  1562.             XDCFG_INT_STS_OFFSET) & XDCFG_IXR_PCFG_DONE_MASK;
  1563.  
  1564.     clk_disable(drvdata->clk);
  1565.  
  1566.     status = sprintf(buf, "%d\n", (prog_done_status >> 2));
  1567.  
  1568.     return status;
  1569. }
  1570.  
  1571. static DEVICE_ATTR(prog_done, 0644, xdevcfg_show_prog_done_status,
  1572.                 NULL);
  1573.  
  1574. /**
  1575.  * xdevcfg_set_is_partial_bitstream() - This function sets the
  1576.  * is_partial_bitstream variable. If is_partial_bitstream is set,
  1577.  * then PROG_B is not asserted (xdevcfg_reset_pl) and also
  1578.  * zynq_slcr_init_preload_fpga and zynq_slcr_init_postload_fpga functions
  1579.  * are not invoked.
  1580.  * @dev:    Pointer to the device structure.
  1581.  * @attr:   Pointer to the device attribute structure.
  1582.  * @buf:    Pointer to the buffer location for the configuration
  1583.  *      data.
  1584.  * @size:   The number of bytes used from the buffer
  1585.  * returns: -EINVAL if invalid parameter is sent or size
  1586.  */
  1587. static ssize_t xdevcfg_set_is_partial_bitstream(struct device *dev,
  1588.         struct device_attribute *attr, const char *buf, size_t size)
  1589. {
  1590.     unsigned long mask_bit;
  1591.     ssize_t status;
  1592.     struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev);
  1593.  
  1594.     status = strict_strtoul(buf, 10, &mask_bit);
  1595.  
  1596.     if (status)
  1597.         return status;
  1598.  
  1599.     if (mask_bit > 1)
  1600.         return -EINVAL;
  1601.  
  1602.     if (mask_bit)
  1603.         drvdata->is_partial_bitstream = 1;
  1604.     else
  1605.         drvdata->is_partial_bitstream = 0;
  1606.  
  1607.     return size;
  1608. }
  1609.  
  1610. /**
  1611.  * xdevcfg_show_is_partial_bitstream_status() - The function returns the
  1612.  * value of is_partial_bitstream variable.
  1613.  * @dev:    Pointer to the device structure.
  1614.  * @attr:   Pointer to the device attribute structure.
  1615.  * @buf:    Pointer to the buffer location for the configuration
  1616.  *      data.
  1617.  * returns: size of the buffer.
  1618.  */
  1619. static ssize_t xdevcfg_show_is_partial_bitstream_status(struct device *dev,
  1620.         struct device_attribute *attr, char *buf)
  1621. {
  1622.     ssize_t status;
  1623.     struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev);
  1624.  
  1625.     status = sprintf(buf, "%d\n", drvdata->is_partial_bitstream);
  1626.  
  1627.     return status;
  1628. }
  1629.  
  1630. static DEVICE_ATTR(is_partial_bitstream, 0644,
  1631.                 xdevcfg_show_is_partial_bitstream_status,
  1632.                 xdevcfg_set_is_partial_bitstream);
  1633.  
  1634. static const struct attribute *xdevcfg_attrs[] = {
  1635.     &dev_attr_prog_done.attr, /* PCFG_DONE bit in Intr Status register */
  1636.     &dev_attr_dbg_lock.attr, /* Debug lock bit in Lock register */
  1637.     &dev_attr_seu_lock.attr, /* SEU lock bit in Lock register */
  1638.     &dev_attr_aes_en_lock.attr, /* AES EN lock bit in Lock register */
  1639.     &dev_attr_enable_aes.attr, /* AES EN bit in Control register */
  1640.     &dev_attr_enable_seu.attr, /* SEU EN bit in Control register */
  1641.     &dev_attr_enable_sec_dbg_nonin.attr, /*SPNIDEN bit in Control register*/
  1642.     &dev_attr_enable_sec_dbg_in.attr, /*SPIDEN bit in Control register */
  1643.     &dev_attr_enable_dbg_nonin.attr, /* NIDEN bit in Control register */
  1644.     &dev_attr_enable_dbg_in.attr, /* DBGEN bit in Control register */
  1645.     &dev_attr_enable_dap.attr, /* DAP_EN bits in Control register */
  1646.     &dev_attr_is_partial_bitstream.attr, /* Flag for partial bitstream */
  1647.     NULL,
  1648. };
  1649.  
  1650.  
  1651. static const struct attribute_group xdevcfg_attr_group = {
  1652.     .attrs = (struct attribute **) xdevcfg_attrs,
  1653. };
  1654.  
  1655. static ssize_t fclk_enable_show(struct device *dev,
  1656.         struct device_attribute *attr, char *buf)
  1657. {
  1658.     struct fclk_data *pdata = dev_get_drvdata(dev);
  1659.  
  1660.     return scnprintf(buf, PAGE_SIZE, "%u\n", pdata->enabled);
  1661. }
  1662.  
  1663. static ssize_t fclk_enable_store(struct device *dev,
  1664.         struct device_attribute *attr, const char *buf, size_t count)
  1665. {
  1666.     unsigned long enable;
  1667.     int ret;
  1668.     struct fclk_data *pdata = dev_get_drvdata(dev);
  1669.  
  1670.     ret = kstrtoul(buf, 0, &enable);
  1671.     if (ret)
  1672.         return -EINVAL;
  1673.  
  1674.     enable = !!enable;
  1675.     if (enable == pdata->enabled)
  1676.         return count;
  1677.  
  1678.     if (enable)
  1679.         ret = clk_enable(pdata->clk);
  1680.     else
  1681.         clk_disable(pdata->clk);
  1682.  
  1683.     if (ret)
  1684.         return ret;
  1685.  
  1686.     pdata->enabled = enable;
  1687.     return count;
  1688. }
  1689.  
  1690. static DEVICE_ATTR(enable, 0644, fclk_enable_show, fclk_enable_store);
  1691.  
  1692. static ssize_t fclk_set_rate_show(struct device *dev,
  1693.         struct device_attribute *attr, char *buf)
  1694. {
  1695.     struct fclk_data *pdata = dev_get_drvdata(dev);
  1696.  
  1697.     return scnprintf(buf, PAGE_SIZE, "%lu\n", clk_get_rate(pdata->clk));
  1698. }
  1699.  
  1700. static ssize_t fclk_set_rate_store(struct device *dev,
  1701.         struct device_attribute *attr, const char *buf, size_t count)
  1702. {
  1703.     int ret = 0;
  1704.     unsigned long rate;
  1705.     struct fclk_data *pdata = dev_get_drvdata(dev);
  1706.  
  1707.     ret = kstrtoul(buf, 0, &rate);
  1708.     if (ret)
  1709.         return -EINVAL;
  1710.  
  1711.     rate = clk_round_rate(pdata->clk, rate);
  1712.     ret = clk_set_rate(pdata->clk, rate);
  1713.  
  1714.     return ret ? ret : count;
  1715. }
  1716.  
  1717. static DEVICE_ATTR(set_rate, 0644, fclk_set_rate_show, fclk_set_rate_store);
  1718.  
  1719. static ssize_t fclk_round_rate_show(struct device *dev,
  1720.         struct device_attribute *attr, char *buf)
  1721. {
  1722.     struct fclk_data *pdata = dev_get_drvdata(dev);
  1723.  
  1724.     return scnprintf(buf, PAGE_SIZE, "%lu => %lu\n", pdata->rate_rnd,
  1725.             clk_round_rate(pdata->clk, pdata->rate_rnd));
  1726. }
  1727.  
  1728. static ssize_t fclk_round_rate_store(struct device *dev,
  1729.         struct device_attribute *attr, const char *buf, size_t count)
  1730. {
  1731.     int ret = 0;
  1732.     unsigned long rate;
  1733.     struct fclk_data *pdata = dev_get_drvdata(dev);
  1734.  
  1735.     ret = kstrtoul(buf, 0, &rate);
  1736.     if (ret)
  1737.         return -EINVAL;
  1738.  
  1739.     pdata->rate_rnd = rate;
  1740.  
  1741.     return count;
  1742. }
  1743.  
  1744. static DEVICE_ATTR(round_rate, 0644, fclk_round_rate_show,
  1745.         fclk_round_rate_store);
  1746.  
  1747. static const struct attribute *fclk_ctrl_attrs[] = {
  1748.     &dev_attr_enable.attr,
  1749.     &dev_attr_set_rate.attr,
  1750.     &dev_attr_round_rate.attr,
  1751.     NULL,
  1752. };
  1753.  
  1754. static const struct attribute_group fclk_ctrl_attr_grp = {
  1755.     .attrs = (struct attribute **)fclk_ctrl_attrs,
  1756. };
  1757.  
  1758. static ssize_t xdevcfg_fclk_export_store(struct device *dev,
  1759.         struct device_attribute *attr, const char *buf, size_t size)
  1760. {
  1761.     int i, ret;
  1762.     struct device *subdev;
  1763.     struct fclk_data *fdata;
  1764.     struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev);
  1765.  
  1766.     for (i = 0; i < NUMFCLKS; i++) {
  1767.         if (!strncmp(buf, fclk_name[i], strlen(fclk_name[i])))
  1768.             break;
  1769.     }
  1770.  
  1771.     if (i < NUMFCLKS && !drvdata->fclk_exported[i]) {
  1772.         drvdata->fclk_exported[i] = 1;
  1773.         subdev = device_create(drvdata->fclk_class, dev, MKDEV(0, 0),
  1774.                 NULL, fclk_name[i]);
  1775.         if (IS_ERR(subdev))
  1776.             return PTR_ERR(subdev);
  1777.         ret = clk_prepare(drvdata->fclk[i]);
  1778.         if (ret)
  1779.             return ret;
  1780.         fdata = kzalloc(sizeof(*fdata), GFP_KERNEL);
  1781.         if (!fdata) {
  1782.             ret = -ENOMEM;
  1783.             goto err_unprepare;
  1784.         }
  1785.         fdata->clk = drvdata->fclk[i];
  1786.         dev_set_drvdata(subdev, fdata);
  1787.         ret = sysfs_create_group(&subdev->kobj, &fclk_ctrl_attr_grp);
  1788.         if (ret)
  1789.             goto err_free;
  1790.     } else {
  1791.         return -EINVAL;
  1792.     }
  1793.  
  1794.     return size;
  1795.  
  1796. err_free:
  1797.     kfree(fdata);
  1798. err_unprepare:
  1799.     clk_unprepare(drvdata->fclk[i]);
  1800.  
  1801.     return ret;
  1802. }
  1803.  
  1804. static ssize_t xdevcfg_fclk_export_show(struct device *dev,
  1805.         struct device_attribute *attr, char *buf)
  1806. {
  1807.     int i;
  1808.     ssize_t count = 0;
  1809.     struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev);
  1810.  
  1811.     for (i = 0; i < NUMFCLKS; i++) {
  1812.         if (!drvdata->fclk_exported[i])
  1813.             count += scnprintf(buf + count, PAGE_SIZE - count,
  1814.                     "%s\n", fclk_name[i]);
  1815.     }
  1816.     return count;
  1817. }
  1818.  
  1819. static DEVICE_ATTR(fclk_export, 0644, xdevcfg_fclk_export_show,
  1820.         xdevcfg_fclk_export_store);
  1821.  
  1822. static int match_fclk(struct device *dev, const void *data)
  1823. {
  1824.     struct fclk_data *fdata = dev_get_drvdata(dev);
  1825.  
  1826.     return fdata->clk == data;
  1827. }
  1828.  
  1829. static ssize_t xdevcfg_fclk_unexport_store(struct device *dev,
  1830.         struct device_attribute *attr, const char *buf, size_t size)
  1831. {
  1832.     int i;
  1833.     struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev);
  1834.  
  1835.     for (i = 0; i < NUMFCLKS; i++) {
  1836.         if (!strncmp(buf, fclk_name[i], strlen(fclk_name[i])))
  1837.             break;
  1838.     }
  1839.  
  1840.     if (i < NUMFCLKS && drvdata->fclk_exported[i]) {
  1841.         struct fclk_data *fdata;
  1842.         struct device *subdev;
  1843.  
  1844.         drvdata->fclk_exported[i] = 0;
  1845.         subdev = class_find_device(drvdata->fclk_class, NULL,
  1846.                 drvdata->fclk[i], match_fclk);
  1847.         fdata = dev_get_drvdata(subdev);
  1848.         if (fdata->enabled)
  1849.             clk_disable(fdata->clk);
  1850.         clk_unprepare(fdata->clk);
  1851.         kfree(fdata);
  1852.         device_unregister(subdev);
  1853.         put_device(subdev);
  1854.     } else {
  1855.         return -EINVAL;
  1856.     }
  1857.  
  1858.     return size;
  1859. }
  1860.  
  1861. static ssize_t xdevcfg_fclk_unexport_show(struct device *dev,
  1862.         struct device_attribute *attr, char *buf)
  1863. {
  1864.     int i;
  1865.     ssize_t count = 0;
  1866.     struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev);
  1867.  
  1868.     for (i = 0; i < NUMFCLKS; i++) {
  1869.         if (drvdata->fclk_exported[i])
  1870.             count += scnprintf(buf + count, PAGE_SIZE - count,
  1871.                     "%s\n", fclk_name[i]);
  1872.     }
  1873.     return count;
  1874. }
  1875.  
  1876. static DEVICE_ATTR(fclk_unexport, 0644, xdevcfg_fclk_unexport_show,
  1877.         xdevcfg_fclk_unexport_store);
  1878.  
  1879. static const struct attribute *fclk_exp_attrs[] = {
  1880.     &dev_attr_fclk_export.attr,
  1881.     &dev_attr_fclk_unexport.attr,
  1882.     NULL,
  1883. };
  1884.  
  1885. static const struct attribute_group fclk_exp_attr_grp = {
  1886.     .attrs = (struct attribute **)fclk_exp_attrs,
  1887. };
  1888.  
  1889. static void xdevcfg_fclk_init(struct device *dev)
  1890. {
  1891.     int i;
  1892.     struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev);
  1893.  
  1894.     for (i = 0; i < NUMFCLKS; i++) {
  1895.         drvdata->fclk[i] = clk_get(dev, fclk_name[i]);
  1896.         if (IS_ERR(drvdata->fclk[i])) {
  1897.             dev_warn(dev, "fclk not found\n");
  1898.             return;
  1899.         }
  1900.     }
  1901.  
  1902.     drvdata->fclk_class = class_create(THIS_MODULE, "fclk");
  1903.     if (IS_ERR(drvdata->fclk_class)) {
  1904.         dev_warn(dev, "failed to create fclk class\n");
  1905.         return;
  1906.     }
  1907.  
  1908.     if (sysfs_create_group(&dev->kobj, &fclk_exp_attr_grp))
  1909.         dev_warn(dev, "failed to create sysfs entries\n");
  1910. }
  1911.  
  1912. static void xdevcfg_fclk_remove(struct device *dev)
  1913. {
  1914.     int i;
  1915.     struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev);
  1916.  
  1917.     for (i = 0; i < NUMFCLKS; i++) {
  1918.         if (drvdata->fclk_exported[i]) {
  1919.             struct fclk_data *fdata;
  1920.             struct device *subdev;
  1921.  
  1922.             drvdata->fclk_exported[i] = 0;
  1923.             subdev = class_find_device(drvdata->fclk_class, NULL,
  1924.                     drvdata->fclk[i], match_fclk);
  1925.             fdata = dev_get_drvdata(subdev);
  1926.             if (fdata->enabled)
  1927.                 clk_disable(fdata->clk);
  1928.             clk_unprepare(fdata->clk);
  1929.             kfree(fdata);
  1930.             device_unregister(subdev);
  1931.             put_device(subdev);
  1932.  
  1933.         }
  1934.     }
  1935.  
  1936.     class_destroy(drvdata->fclk_class);
  1937.     sysfs_remove_group(&dev->kobj, &fclk_exp_attr_grp);
  1938.  
  1939.     return;
  1940. }
  1941.  
  1942. /**
  1943.  * xdevcfg_drv_probe -  Probe call for the device.
  1944.  *
  1945.  * @pdev:   handle to the platform device structure.
  1946.  * Returns 0 on success, negative error otherwise.
  1947.  *
  1948.  * It does all the memory allocation and registration for the device.
  1949.  */
  1950. static int xdevcfg_drv_probe(struct platform_device *pdev)
  1951. {
  1952.     struct resource *res;
  1953.     struct xdevcfg_drvdata *drvdata;
  1954.     dev_t devt;
  1955.     int retval;
  1956.     u32 ctrlreg;
  1957.     struct device_node *np;
  1958.     const void *prop;
  1959.     int size;
  1960.     struct device *dev;
  1961.  
  1962.     drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata), GFP_KERNEL);
  1963.     if (!drvdata)
  1964.         return -ENOMEM;
  1965.  
  1966.     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1967.     drvdata->base_address = devm_ioremap_resource(&pdev->dev, res);
  1968.     if (IS_ERR(drvdata->base_address))
  1969.         return PTR_ERR(drvdata->base_address);
  1970.  
  1971.     drvdata->irq = platform_get_irq(pdev, 0);
  1972.     retval = devm_request_irq(&pdev->dev, drvdata->irq, &xdevcfg_irq,
  1973.                 0, dev_name(&pdev->dev), drvdata);
  1974.     if (retval) {
  1975.         dev_err(&pdev->dev, "No IRQ available");
  1976.         return retval;
  1977.     }
  1978.  
  1979.     platform_set_drvdata(pdev, drvdata);
  1980.     spin_lock_init(&drvdata->lock);
  1981.     mutex_init(&drvdata->sem);
  1982.     drvdata->is_open = 0;
  1983.     drvdata->is_partial_bitstream = 0;
  1984.     drvdata->dma_done = 0;
  1985.     drvdata->error_status = 0;
  1986.     dev_info(&pdev->dev, "ioremap %pa to %p\n",
  1987.          &res->start, drvdata->base_address);
  1988.  
  1989.     drvdata->clk = devm_clk_get(&pdev->dev, "ref_clk");
  1990.     if (IS_ERR(drvdata->clk)) {
  1991.         dev_err(&pdev->dev, "input clock not found\n");
  1992.         return PTR_ERR(drvdata->clk);
  1993.     }
  1994.  
  1995.     retval = clk_prepare_enable(drvdata->clk);
  1996.     if (retval) {
  1997.         dev_err(&pdev->dev, "unable to enable clock\n");
  1998.         return retval;
  1999.     }
  2000.  
  2001.     /*
  2002.      * Figure out from the device tree if this is running on the EP107
  2003.      * emulation platform as it doesn't match the silicon exactly and the
  2004.      * driver needs to work accordingly.
  2005.      */
  2006.     np = of_get_next_parent(pdev->dev.of_node);
  2007.     np = of_get_next_parent(np);
  2008.     prop = of_get_property(np, "compatible", &size);
  2009.  
  2010.     if (prop != NULL) {
  2011.         if ((strcmp((const char *)prop, "xlnx,zynq-ep107")) == 0)
  2012.             drvdata->ep107 = 1;
  2013.         else
  2014.             drvdata->ep107 = 0;
  2015.     }
  2016.  
  2017.     /* Unlock the device */
  2018.     xdevcfg_writereg(drvdata->base_address + XDCFG_UNLOCK_OFFSET,
  2019.                 0x757BDF0D);
  2020.  
  2021.     /*
  2022.      * Set the configuration register with the following options
  2023.      *  - Reset FPGA
  2024.      *  - Enable PCAP interface for Partial reconfiguration
  2025.      *  - Enable the PCAP interface
  2026.      *  - Set the throughput rate for maximum speed
  2027.      *  - Se the CPU in user mode
  2028.      */
  2029.     ctrlreg = xdevcfg_readreg(drvdata->base_address + XDCFG_CTRL_OFFSET);
  2030.     xdevcfg_writereg(drvdata->base_address + XDCFG_CTRL_OFFSET,
  2031.                 (XDCFG_CTRL_PCFG_PROG_B_MASK |
  2032.                 XDCFG_CTRL_PCAP_PR_MASK |
  2033.                 XDCFG_CTRL_PCAP_MODE_MASK |
  2034.                 ctrlreg));
  2035.  
  2036.     /* Ensure internal PCAP loopback is disabled */
  2037.     ctrlreg = xdevcfg_readreg(drvdata->base_address + XDCFG_MCTRL_OFFSET);
  2038.     xdevcfg_writereg(drvdata->base_address + XDCFG_MCTRL_OFFSET,
  2039.                 (~XDCFG_MCTRL_PCAP_LPBK_MASK &
  2040.                 ctrlreg));
  2041.  
  2042.  
  2043.     retval = alloc_chrdev_region(&devt, 0, XDEVCFG_DEVICES, DRIVER_NAME);
  2044.     if (retval < 0)
  2045.         goto failed5;
  2046.  
  2047.     drvdata->devt = devt;
  2048.  
  2049.     cdev_init(&drvdata->cdev, &xdevcfg_fops);
  2050.     drvdata->cdev.owner = THIS_MODULE;
  2051.     retval = cdev_add(&drvdata->cdev, devt, 1);
  2052.     if (retval) {
  2053.         dev_err(&pdev->dev, "cdev_add() failed\n");
  2054.         goto failed6;
  2055.     }
  2056.  
  2057.     drvdata->class = class_create(THIS_MODULE, DRIVER_NAME);
  2058.     if (IS_ERR(drvdata->class)) {
  2059.         dev_err(&pdev->dev, "failed to create class\n");
  2060.         goto failed6;
  2061.     }
  2062.  
  2063.     dev = device_create(drvdata->class, &pdev->dev, devt, drvdata,
  2064.             DRIVER_NAME);
  2065.     if (IS_ERR(dev)) {
  2066.             dev_err(&pdev->dev, "unable to create device\n");
  2067.             goto failed7;
  2068.     }
  2069.  
  2070.     /* create sysfs files for the device */
  2071.     retval = sysfs_create_group(&(pdev->dev.kobj), &xdevcfg_attr_group);
  2072.     if (retval) {
  2073.         dev_err(&pdev->dev, "Failed to create sysfs attr group\n");
  2074.         cdev_del(&drvdata->cdev);
  2075.         goto failed8;
  2076.     }
  2077.  
  2078.     xdevcfg_fclk_init(&pdev->dev);
  2079.  
  2080.     clk_disable(drvdata->clk);
  2081.  
  2082.     return 0;       /* Success */
  2083.  
  2084. failed8:
  2085.     device_destroy(drvdata->class, drvdata->devt);
  2086. failed7:
  2087.     class_destroy(drvdata->class);
  2088. failed6:
  2089.     /* Unregister char driver */
  2090.     unregister_chrdev_region(devt, XDEVCFG_DEVICES);
  2091. failed5:
  2092.     clk_disable_unprepare(drvdata->clk);
  2093.  
  2094.     return retval;
  2095. }
  2096.  
  2097. /**
  2098.  * xdevcfg_drv_remove -  Remove call for the device.
  2099.  *
  2100.  * @pdev:   handle to the platform device structure.
  2101.  * Returns 0 or error status.
  2102.  *
  2103.  * Unregister the device after releasing the resources.
  2104.  */
  2105. static int xdevcfg_drv_remove(struct platform_device *pdev)
  2106. {
  2107.     struct xdevcfg_drvdata *drvdata;
  2108.  
  2109.     drvdata = platform_get_drvdata(pdev);
  2110.  
  2111.     if (!drvdata)
  2112.         return -ENODEV;
  2113.  
  2114.     unregister_chrdev_region(drvdata->devt, XDEVCFG_DEVICES);
  2115.  
  2116.     sysfs_remove_group(&pdev->dev.kobj, &xdevcfg_attr_group);
  2117.  
  2118.     xdevcfg_fclk_remove(&pdev->dev);
  2119.     device_destroy(drvdata->class, drvdata->devt);
  2120.     class_destroy(drvdata->class);
  2121.     cdev_del(&drvdata->cdev);
  2122.     clk_unprepare(drvdata->clk);
  2123.  
  2124.     return 0;       /* Success */
  2125. }
  2126.  
  2127. static struct of_device_id xdevcfg_of_match[] = {
  2128.     { .compatible = "xlnx,zynq-devcfg-1.0", },
  2129.     { /* end of table */}
  2130. };
  2131. MODULE_DEVICE_TABLE(of, xdevcfg_of_match);
  2132.  
  2133. /* Driver Structure */
  2134. static struct platform_driver xdevcfg_platform_driver = {
  2135.     .probe = xdevcfg_drv_probe,
  2136.     .remove = xdevcfg_drv_remove,
  2137.     .driver = {
  2138.         .owner = THIS_MODULE,
  2139.         .name = DRIVER_NAME,
  2140.         .of_match_table = xdevcfg_of_match,
  2141.     },
  2142. };
  2143.  
  2144. module_platform_driver(xdevcfg_platform_driver);
  2145.  
  2146. MODULE_AUTHOR("Xilinx, Inc");
  2147. MODULE_DESCRIPTION("Xilinx Device Config Driver");
  2148. MODULE_LICENSE("GPL");
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