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Release 14.7 Trace  (lin64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.

/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/trce -intstyle ise -v 3 -s 2 -n
3 -fastpaths -xml orpsoc_top.twx orpsoc_top.ncd -o orpsoc_top.twr
orpsoc_top.pcf

Design file:              orpsoc_top.ncd
Physical constraint file: orpsoc_top.pcf
Device,package,speed:     xc7a100t,csg324,C,-2 (PRODUCTION 1.10 2013-10-13)
Report level:             verbose report

Environment Variable      Effect
--------------------      ------
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
   a 50 Ohm transmission line loading model.  For the details of this model,
   and for more information on accounting for different loading conditions,
   please see the device datasheet.



Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock sys_clk_pad_i
---------------+------------+------------+------------+------------+------------------+--------+
               |Max Setup to|  Process   |Max Hold to |  Process   |                  | Clock  |
Source         | clk (edge) |   Corner   | clk (edge) |   Corner   |Internal Clock(s) | Phase  |
---------------+------------+------------+------------+------------+------------------+--------+
gpio0_io<0>    |    4.052(R)|      SLOW  |   -1.767(R)|      FAST  |wb_clk            |   0.000|
gpio0_io<1>    |    4.474(R)|      SLOW  |   -2.036(R)|      FAST  |wb_clk            |   0.000|
gpio0_io<2>    |    4.027(R)|      SLOW  |   -1.758(R)|      FAST  |wb_clk            |   0.000|
gpio0_io<3>    |    3.898(R)|      SLOW  |   -1.661(R)|      FAST  |wb_clk            |   0.000|
gpio0_io<4>    |    3.389(R)|      SLOW  |   -1.469(R)|      FAST  |wb_clk            |   0.000|
gpio0_io<5>    |    3.670(R)|      SLOW  |   -1.652(R)|      FAST  |wb_clk            |   0.000|
gpio0_io<6>    |    3.818(R)|      SLOW  |   -1.672(R)|      FAST  |wb_clk            |   0.000|
gpio0_io<7>    |    4.033(R)|      SLOW  |   -1.728(R)|      FAST  |wb_clk            |   0.000|
rst_n_pad_i    |    7.246(R)|      SLOW  |   -2.819(R)|      FAST  |wb_clk            |   0.000|
uart0_srx_pad_i|    3.976(R)|      SLOW  |   -1.749(R)|      FAST  |wb_clk            |   0.000|
---------------+------------+------------+------------+------------+------------------+--------+

Clock sys_clk_pad_i to Pad
---------------+-----------------+------------+-----------------+------------+------------------+--------+
               |Max (slowest) clk|  Process   |Min (fastest) clk|  Process   |                  | Clock  |
Destination    |  (edge) to PAD  |   Corner   |  (edge) to PAD  |   Corner   |Internal Clock(s) | Phase  |
---------------+-----------------+------------+-----------------+------------+------------------+--------+
gpio0_io<0>    |         7.695(R)|      SLOW  |         1.798(R)|      FAST  |wb_clk            |   0.000|
gpio0_io<1>    |         6.194(R)|      SLOW  |         1.827(R)|      FAST  |wb_clk            |   0.000|
gpio0_io<2>    |         7.654(R)|      SLOW  |         1.770(R)|      FAST  |wb_clk            |   0.000|
gpio0_io<3>    |         6.942(R)|      SLOW  |         1.731(R)|      FAST  |wb_clk            |   0.000|
gpio0_io<4>    |         6.063(R)|      SLOW  |         1.825(R)|      FAST  |wb_clk            |   0.000|
gpio0_io<5>    |         6.552(R)|      SLOW  |         1.671(R)|      FAST  |wb_clk            |   0.000|
gpio0_io<6>    |         7.554(R)|      SLOW  |         2.697(R)|      FAST  |wb_clk            |   0.000|
gpio0_io<7>    |         6.522(R)|      SLOW  |         1.869(R)|      FAST  |wb_clk            |   0.000|
uart0_stx_pad_o|         8.262(R)|      SLOW  |         2.773(R)|      FAST  |wb_clk            |   0.000|
---------------+-----------------+------------+-----------------+------------+------------------+--------+

Clock to Setup on destination clock sys_clk_pad_i
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
sys_clk_pad_i  |   14.421|         |         |         |
---------------+---------+---------+---------+---------+


Analysis completed Mon Apr 14 22:36:26 2014
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Trace Settings:
-------------------------
Trace Settings

Peak Memory Usage: 1747 MB