void MyEMCConfig()
{
    uint32_t WaitN=10000;
    uint32_t *pConfig; //Register pointer
    /**Enable EMC clocking*/
    Chip_SCU_ClockPinMuxSet(0,SCU_MODE_FUNC0); //CLK0 pad N5 set to EMC_CLOCK 0

    //Set CREG6 control register for EMC_CLK_SEL (bit # 16) = 1 => EMC_CLK_DIV divided by 2.
    LPC_CREG->CREG6 |= 1 << 16;

    //Set CCU1 branch clock configuration register. Clock divider value (bit 5:7) 0x1 (divided by 2)
    pConfig=(volatile uint32_t *)0x40051478;
    *pConfig|=0x23; //bit 0,1 and 5 is 1



    //Configure EMCCLKDELAY for frequencies above 95 Mhz
    pConfig=(volatile uint32_t *)0x40086D00;    //EMC clock delay register
    *pConfig |= 0x7FFF; //~ 3.5 ns delay. Page 429


    /**Enable the EMC interface and set EMC endian-ness*/
    pConfig=(volatile uint32_t *)0x40005000; //EMC Control register
    *pConfig |= 0x1;                         //Enable EMC
    pConfig=(volatile uint32_t *)0x40005008; //EMC Configuration register
    *pConfig |= 0x0;                         //Bit 0: Endianess. 0 for little-endian (POR value)


    /**Set a long period for the dynamic refresh rate*/
    pConfig=(volatile uint32_t *)0x40005024; //Dynamic Memory Refresh Timer Register
    *pConfig |= 0x7FF;                       //Long refresh period

    /**Setup address mapping*/
    pConfig=(volatile uint32_t *)0x40005100;    //Dynamic Memory Configuration Register
    *pConfig |= 0x6 << 7;                       //AM0 Address mapping bit 7:12
    *pConfig |= 0x1 << 14;                      //AM1 Address mapping bit 14
    WaitState(WaitN);                           //Empty for-loop for WaitN iterations

    //Ends up 0x4300 => RBC mapping as expected

    /**Setup RAS and CAS latencies*/
    pConfig=(volatile uint32_t *)0x40005104;   //Dynamic Memory RAS & CAS Delay registers
    *pConfig |= 0x3;                           //RAS 3 bit 0:1
    *pConfig |= 0x3 << 8;                      //CAS 3 bit 8:9
    WaitState(WaitN);                          //Empty for-loop for WaitN iterations

    /**Setup the SDRAM command and read strategy*/
    pConfig=(volatile uint32_t *)0x40005028; //Dynamic Memory Read Configuration register
    *pConfig |= 0x1;                         //0x1 for SDRAM operation

    /**Setup interface timing*/
    LPC_EMC->DYNAMICRP      = 4;

    LPC_EMC->DYNAMICRAS     = 7;

    LPC_EMC->DYNAMICSREX    = 9;

    LPC_EMC->DYNAMICAPR     = 1;

    LPC_EMC->DYNAMICDAL     = 7;

    LPC_EMC->DYNAMICWR      = 4;

    LPC_EMC->DYNAMICRC      = 9;

    LPC_EMC->DYNAMICRFC     = 9;

    LPC_EMC->DYNAMICXSR     = 9;

    LPC_EMC->DYNAMICRRD     = 4;

    LPC_EMC->DYNAMICMRD     = 2;


    /**Enable SDRAM clocks and clock enables and issues NOPs for 200 us*/
    pConfig=(volatile uint32_t *)0x40005020; //Dynamic Control Register
    *pConfig |= 0x1;                         //Clock enable
    *pConfig |= 0x1 << 1;                    //Clock Control enable

    pConfig=(volatile uint32_t *)0x40005000; //EMC Control register
    *pConfig |= 0x3 <<7;                     //NOP
    WaitState(WaitN);

    /**Step 13: Issue precharge-all command*/
    pConfig=(volatile uint32_t *)0x40005020; //Dynamic Control Register
    *pConfig |= 0x1;                         //Clock enable
    *pConfig |= 0x1 << 1;                    //Clock Control enable


    pConfig=(volatile uint32_t *)0x40005024;   //Dynamic Memory Refresh Timer Register
    *pConfig = 0x001;                          //Short refresh period

    pConfig=(volatile uint32_t *)0x40005020;  //EMC Control register
    *pConfig |= 0x2 <<7;                      //PALL

    WaitState(WaitN);


    /**Set normal dynamic refresh timing*/
    pConfig=(volatile uint32_t *)0x40005024; //Dynamic Memory Refresh Timer Register
    *pConfig |= 0x64;                        //0x64 EMC_CLK cycles => ~ 15.6 us

    /**Issue mode word*/
    uint32_t ConfigRead;
    //ConfigRead=*((volatile uint32_t *)(0x28000000|0x32<<12)); //DYSC0 Base Address + MODE << OFFSET
    ConfigRead=*((volatile uint32_t *)(0x28032000)); //DYSC0 Base Address + MODE << OFFSET

    pConfig=(volatile uint32_t *)0x40005000; //EMC Control register
    *pConfig |= 0x3 <<7;                     //NOP
    WaitState(WaitN);
    *pConfig |= 0x3 <<7;                     //NOP
    WaitState(WaitN);

    /**Enter normal operational mode*/
    pConfig=(volatile uint32_t *)0x40005020; //Dynamic Control Register
    //*pConfig |= 0x00 << 7;                    //Normal mode (bit 7:8)
    //*pConfig |= 0x0  << 2;                    //Self-refresh normal
    *pConfig = 0x00;                            //Clear
    *pConfig = 0x7;                             //CE, CS, SR

    /** Enable buffer*/
    pConfig=(volatile uint32_t *)0x40005100;    //Dynamic Memory Configuration Register
    *pConfig |= 0x1 << 19;
}