MMU.c

void MMU_reset() {
    int i;
    for(i=0; i<8192; i++) {
      MMU_wram[i] = 0;
      MMU_eram[i] = 0;
    }
    for(i=0; i<127; i++) {
      MMU_zram[i] = 0;
    }
    MMU_inbios=1;
    MMU_ie=0;
    MMU_if=0;
 };

int MMU_rw(int addr) { return MMU_rb(addr)+(MMU_rb(addr+1)<<8); };

void MMU_wb(int addr, int val) {
    switch(addr&0xF000)
    {
      // ROM bank 0
      case 0x0000:
        if(MMU_inbios && addr<0x0100) return;
    // fall through
      case 0x1000:
      case 0x2000:
      case 0x3000:
        break;

      // ROM bank 1
      case 0x4000: case 0x5000: case 0x6000: case 0x7000:
        break;

      // VRAM
      case 0x8000: case 0x9000:
        GPU_vram[addr&0x1FFF] = val;
    GPU_updatetile(addr&0x1FFF, val);
    break;

      // External RAM
      case 0xA000: case 0xB000:
        MMU_eram[addr&0x1FFF] = val;
    break;

      // Work RAM and echo
      case 0xC000: case 0xD000: case 0xE000:
        MMU_wram[addr&0x1FFF] = val;
    break;

      // Everything else
      case 0xF000:
        switch(addr&0x0F00)
    {
      // Echo RAM
      case 0x000: case 0x100: case 0x200: case 0x300:
      case 0x400: case 0x500: case 0x600: case 0x700:
      case 0x800: case 0x900: case 0xA00: case 0xB00:
      case 0xC00: case 0xD00:
        MMU_wram[addr&0x1FFF] = val;
        break;

          // OAM
      case 0xE00:
        if((addr&0xFF)<0xA0) GPU_oam[addr&0xFF] = val;
        GPU_updateoam(addr,val);
        break;

          // Zeropage RAM, I/O
      case 0xF00:
        if(addr > 0xFF7F) { MMU_zram[addr&0x7F]=val; }
        else switch(addr&0xF0)
        {
        }
    }
    break;
    }
};

void MMU_ww(int addr, int val) { MMU_wb(addr,val&255); MMU_wb(addr+1,val>>8); };