library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity CAMReg is
	port ( data: in std_logic_vector(3 downto 0);
			ld: in std_logic;
			rd: in std_logic;
			rdy: out std_logic;
			mbit: out boolean);
end CAMReg;

architecture behav of CAMReg is
	type states is (STO, WT, RET);

	signal newstates;
begin

	-- State transition process

	process is
		variable currentstate: states := RET;
	begin
		if clk = '1'
			case currentstate is
				when STO =>
					currentstate := WT;
				when WT =>
					if not((ld = '1') and (rd = '1')) then
						currentstate := WT;
					end if

					if ((ld = '1') and (rd = '1')) then
						currentstate := RET;
					end if;

				when RET =>
					currentstate := WT
			end case;
		end if;
		newstates <= currentstate;
	wait on clk;
	begin
	end process;

-- Asserted outputs process
	process is
		variable REG: std_logic_vector(3 downto 0);
		case newstates is
			when STO =>
				REG := data;
			when WT =>
				rdy <= '1';
				mbit <= true;
			when RET =>
				mbit <= (REG = data);
		end case;
	wait on newstates;
	end process;

end behav;