module cam(
    input [7:0] DIVISOR,
    input DIR,
    input SPINDLE,
    output reg STEPPER
    );

     parameter FORWARD = 1'b1;
     parameter REVERSE = !FORWARD;

     reg[7:0] counter = 0;

    always @(posedge SPINDLE) begin
    //  STEPPER = 0;
        if (DIR == FORWARD) begin
            counter = counter + 1;
            if (counter == DIVISOR) counter = 0;
            end
        else begin
        //  counter <= counter - 1;
        //  if (counter == (-1)) counter <= DIVISOR;
            end
    end

    always @(negedge SPINDLE) begin
        STEPPER = (counter == 0) ? 1 : 0;
    end

endmodule

Counter  MyCount (.clk(clk),
                  .rst(rst_count),
                  .inc(inc_count),
                  .data_out(count_out));