ModemRS 3.0.0 (Beta)

--Configs
local MODEM_SIDES = {"all"}
local INPUT_SIDES = {"all"}
local OUTPUT_SIDES = {"all"}
local FREQUENCIES = {"1"}
local MODEM_RS_CHANNEL = 127
local INVERT_INPUT = false
local INVERT_OUTPUT = false
local OUTPUT_ANALOG = false
local OUTPUT_LOGIC = {"r",1,0}
local INPUT_LOGIC = "or"

--[[
MODEM_SIDES:
Fill this table with a list of sides which this computer should try to wrap as modems.
If the first element is "all" it will try to wrap a modem on every valid side.
If There isn't a modem on a side the program will skip it.
Default is "all".
It is recommended that you leave this on "all" unless you don't want it to wrap a specific modem or modems.

INPUT_SIDES:
Fill this table with list of sides which should be inputs.
If the first element is "all" all sides will be input.
If the first element is nil or "none" no sides will be inputs.
Default is "all".

OUTPUT_SIDES:
Fill this table with list of sides which this computer should output a received signal
If the first element is "all" it will output to all sides
If the first element is nil or "none" no sides will be outputs.
Default is "all".

FREQUENCIES:
Fill this table with a  list of sides which this computer should send a receive modem messages
These are NOT modem channels.
This program uses one modem channel but allows for an infinite amount of frequencies
Frequencies can be either a number or string
A computer can be connected to as many frequencies as you would like.

MODEM_RS_CHANNEL:
This is the modem channel this program uses to send and receive messages.
Default is 127; it is not recommended that you change this.

INVERT_INPUT:
If true the signal on input computers will be inverted.
This only affects bundled and digital inputs
default is false.

INVERT_OUTPUT:
If true the signal on output computers will be inverted.
This only affects bundled and digital outputs.
default is false.

OUTPUT_ANALOG:
Outputs combined analog (1-15) signal strength.
Doesn't Apply to bundled cable.
If this is enabled it ignored output logic
Default is false

OUTPUT_LOGIC:
Logic can be used to specify how many computers have to be on for the ouput to turn on.
This works for bundled too but treats every color as a different signal.
The first element in this array can either be "r" or "l"
"r" means range; "l" means list.
If "r" then the amount of "on" computers has to be between the next to elements in the array
If the 3rd element (or max range) is 0 then it will be infinite.
So if the first element is 2nd element is 1 and the 2nd is 0 it will be an or gate.
If "l" then any element after that will be an acceptable amount.
Any other number will be ignored.
So if the elements following "l" are 3,5,7 then if the amount of on computers equals anything else.
Default is {"r",1,0}

INPUT_LOGIC:
Can be either "or" or "and".
If "and" then all input sides have to be on for that computer to send an "on" signal.
If "or" then any of the inputs will turn on the output.
"or" is default.
]]

--Variables (dont edit these)
local version = "3.0.0"
local ID = os.getComputerID()
local analog = {lastNum=0,stack = 0}
local bundled = {lastStates = {},stacks = {},states = {},updates = {}}
local digital = {lastState=false,stack = 0}
local modems = {}
local freqs = {}
local event,senderID,message,void,handle

--local function errorCheck()

local function writeToFile(sText,sFile)
    handle = fs.open("Jyzarc/modemRS/"..sFile,"w")
    handle.write(sText)
    handle.close()
end

--Modem Wrapping Loop
local function wrapModems()
    if MODEM_SIDES[1] == "all" then
        for i = 1,6 do
            --Check if peripheral on side exists
            if peripheral.getType(rs.getSides()[i]) == "modem" then
                --Wraps peripheral
                modems[#modems+1] = peripheral.wrap(rs.getSides()[i])
            end
        end
    else
        for i = 1,#MODEM_SIDES do
            --Check if peripheral on side exists
            if peripheral.getType(MODEM_SIDES[i]) then
                --Wraps peripheral
                modems[#modems+1] = peripheral.wrap(MODEM_SIDES[i])
            end
        end
    end
end

--Opens Modem Channel on all connected modems
local function openChannel()
    for i = 1,#modems do
        --Opens up modem channel
        modems[i].open(MODEM_RS_CHANNEL)
    end
end

--Sets all of the frequencies in the "FREQUENCIES" table to true
local function addFrequencies()
    for i = 1,#FREQUENCIES do
        freqs[FREQUENCIES[i]] = true
    end
end

--Just resets all of the bundled info.
local function fillBundledInfo()
    for i = 1,16 do
        bundled.lastStates[i] = false
        bundled.stacks[i] = 0
    end
end

--Redstone functions

function digital.get()
    if INPUT_LOGIC == "or" then
        digital.state = false
        if INPUT_SIDES[1] == "all" then
            for i = 1,6 do
                digital.state = digital.state or rs.getInput(rs.getSides()[i])
            end
        else
            for i = 1,#INPUT_SIDES do
                digital.state = digital.state or rs.getInput(INPUT_SIDES[i])
            end
        end
    elseif INPUT_LOGIC == "and" then
        digital.state = true
        if INPUT_SIDES[1] == "all" then
            for i = 1,6 do
                digital.state = digital.state and rs.getInput(rs.getSides()[i])
            end
        else
            for i = 1,#INPUT_SIDES do
                digital.state = digital.state and rs.getInput(INPUT_SIDES[i])
            end
        end
    end
    --Inverts signal if invert option is true
    if INVERT_INPUT then
        digital.state = not digital.state
    end
    --Checks if this signal was the same as the last
    if digital.state == digital.lastState then
        digital.update = 0
    elseif digital.state then
        digital.update = 1
    else
        digital.update = -1
    end
    digital.lastState = digital.state
    return digital.update
end

function digital.updateSignal(sBool)
    if INVERT_OUTPUT then
        sBool = not sBool
    end
    if OUTPUT_SIDES[1] == "all" then
        for i = 1,6 do
            rs.setOutput(rs.getSides()[i],sBool)
        end
    else
        for i = 1,#OUTPUT_SIDES do
            rs.setOutput(OUTPUT_SIDES[i],sBool)
        end
    end
end

function digital.set(sUpdate)
    digital.temp = false
    digital.stack = digital.stack + sUpdate
    if digital.stack < 0 then
        digital.stack = 0
    end
    writeToFile(digital.stack,"digital")
    if OUTPUT_LOGIC[1] == "r" then
        if digital.stack >= OUTPUT_LOGIC[2]
        and (digital.stack <= OUTPUT_LOGIC[3]
        or OUTPUT_LOGIC[3] == 0) then
            digital.updateSignal(true)
        else
            digital.updateSignal(false)
        end
    elseif OUTPUT_LOGIC[1] == "l" then
        for i = 1,#OUTPUT_LOGIC-1 do
            digital.temp = digital.temp or digital.stack == OUTPUT_LOGIC[i+1]
        end
        if digital.temp then
            digital.updateSignal(true)
        else
            digital.updateSignal(false)
        end
    end
end

function analog.get()
    analog.num = 0
    if INPUT_SIDES[1] == "all" then
        for i = 1,6 do
            analog.num = analog.num + rs.getAnalogInput(rs.getSides()[i])
        end
    else
        for i = 1,#INPUT_SIDES do
            analog.num = analog.num + rs.getAnalogInput(INPUT_SIDES[i])
        end
    end
    analog.update = analog.num - analog.lastNum
    analog.lastNum = analog.num
    return analog.update
end

function analog.set(sUpdate)
    analog.stack = analog.stack + sUpdate
    if analog.stack < 0 then
        analog.stack = 0
    end
    if analog.stack > 15 then
        analog.stack = 15
    end
    writeToFile(analog.stack,"analog")
    if OUTPUT_SIDES[1] == "all" then
        for i = 1,6 do
            rs.setAnalogOutput(rs.getSides()[i],analog.stack)
        end
    else
        for i = 1,#OUTPUT_SIDES do
            rs.setAnalgOutput(OUTPUT_SIDES[i],analog.stack)
        end
    end
end

function bundled.get() --I've made a huge mistake
    for i = 1,16 do
        if INPUT_LOGIC == "or" then
            bundled.states[i] = false
            if INPUT_SIDES[1] == "all" then
                for s = 1,6 do
                    bundled.states[i] = bundled.states[i] or rs.testBundledInput(rs.getSides()[s],2^(i-1))
                end
            else
                for s = 1,#INPUT_SIDES do
                    bundled.states[i] = bundled.states[i] or rs.testBundledInput(INPUT_SIDES[s],2^(i-1))
                end
            end
        elseif INPUT_LOGIC == "and" then
            bundled.states[i] = true
            if INPUT_SIDES[1] == "all" then
                for s = 1,6 do
                    bundled.states[i] = bundled.state[i] and rs.testBundledInput(rs.getSides()[s],2^(i-1))
                end
            else
                for s = 1,#INPUT_SIDES do
                    bundled.states[i] = bundled.states[i] and rs.testBundledInput(INPUT_SIDES[s],2^(i-1))
                end
            end
        end
        if INVERT_INPUT then
            bundled.states[i] = not bundled.states[i]
        end
        if bundled.states[i] == bundled.lastStates[i] then
            bundled.updates[i] = 0
        elseif bundled.states[i] then
            bundled.updates[i] = 1
        else
            bundled.updates[i] = -1
        end
        bundled.lastStates[i] = bundled.states[i]
    end
    return bundled.updates
end

function bundled.updateSignal(sBools) --The fun continues
    bundled.number = 0
    for i = 1,16 do
        if INVERT_OUTPUT then
            sBools = not sBools
        end
        if sBools[i] then
            bundled.number = bundled.number + 2^(i-1)
        end
    end
    if OUTPUT_SIDES[1] == "all" then
        for y = 1,6 do
            rs.setBundledOutput(rs.getSides()[y],bundled.number)
        end
    else
        for y = 1,#OUTPUT_SIDES do
            rs.setBundledOutput(OUTPUT_SIDES[y],bundled.number)
        end
    end
end

function bundled.set(sUpdates) --Make it stop
    for i = 1,16 do
        bundled.temp = false
        bundled.stacks[i] = bundled.stacks[i] + sUpdates[i]
        if bundled.stacks[i] < 0 then
            bundled.stacks[i] = 0
        end
        if OUTPUT_LOGIC[1] == "r" then
            if bundled.stacks[i] >= OUTPUT_LOGIC[2]
            and (bundled.stacks[i] <= OUTPUT_LOGIC[3]
            or OUTPUT_LOGIC[3] == 0) then
                bundled.states[i] = true
            else
                bundled.states[i] = false
            end
            writeToFile(textutils.serialize(bundled.stacks),"bundled")
        elseif OUTPUT_LOGIC[1] == "l" then
            for i = 1,#OUTPUT_LOGIC-1 do
                bundled.temp = bundled.temp or bundled.stacks[i] == OUTPUT_LOGIC[i+1]
            end
            if bundled.temp then
                bundled.updateSignal(true)
            else
                bundled.updateSignal(false)
            end
        end
    end
    bundled.updateSignal(bundled.states)
end

local function setStartupSignals()
    if fs.exists("Jyzarc/modemRS/digital") then
        handle = fs.open("Jyzarc/modemRS/digital","r")
        digital.file = handle.readAll()
        handle.close()
        fs.delete("Jyzarc/modemRS/digital")
        if not OUTPUT_ANALOG then
            digital.set(tonumber(digital.file))
        end
    end
    if fs.exists("Jyzarc/modemRS/analog") then
        handle = fs.open("Jyzarc/modemRS/analog","r")
        analog.file = handle.readAll()
        handle.close()
        fs.delete("Jyzarc/modemRS/analog")
        if OUTPUT_ANALOG then
            analog.set(tonumber(analog.file))
        end
    end
    if fs.exists("Jyzarc/modemRS/bundled") then
        handle = fs.open("Jyzarc/modemRS/bundled","r")
        bundled.file = handle.readAll()
        handle.close()
        fs.delete("Jyzarc/modemRS/bundled")
        bundled.set(textutils.unserialize(bundled.file))
    end
end

local function send()
    for x = 1,#modems do
        for y = 1,#FREQUENCIES do
            modems[x].transmit(MODEM_RS_CHANNEL,ID,{FREQUENCIES[y],digital.get(),analog.get(),bundled.get()})
        end
    end
end

--This runs on startup and sets everything up
local function startup()
    --Clear screen
    term.clear()
    --Set cursor to top left
    term.setCursorPos(1,1)
    print("ModemRS version "..version.." by Jyzarc27")
    wrapModems()
    openChannel()
    addFrequencies()
    fillBundledInfo()
    if not fs.exists("Jyzarc/modemRS") then
        fs.makeDir("Jyzarc")
        fs.makeDir("Jyzarc/modemRS")
    end
    setStartupSignals()
end

startup()

while true do
    event,void,void,senderID,message = os.pullEvent()
    if event == "redstone" then
        if INPUT_SIDES[1] ~= nil
        and INPUT_SIDES[1] ~= "none" then
            send()
        end
    elseif event == "modem_message" then
        if OUTPUT_SIDES[1] ~= nil
        and OUTPUT_SIDES[1] ~= "none" then
            if freqs[message[1]] then
                if OUTPUT_ANALOG then
                    analog.set(message[3])
                else
                    digital.set(message[2])
                end
                bundled.set(message[4])
            end
        end
    end
end