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  1. /dts-v1/;
  2.  
  3. / {
  4. #address-cells = <0x2>;
  5. #size-cells = <0x2>;
  6. model = "Qualcomm Technologies, Inc. MSMTITANIUM QRD WT88553";
  7. compatible = "qcom,msm8953-qrd-wt88553", "qcom,msm8953-qrd", "qcom,msm8953", "qcom,qrd";
  8. qcom,msm-id = <0x125 0x0>;
  9. interrupt-parent = <0x1>;
  10. qcom,board-id = <0x1000b 0x1>;
  11.  
  12. cpus {
  13. #address-cells = <0x1>;
  14. #size-cells = <0x0>;
  15.  
  16. cpu-map {
  17.  
  18. cluster0 {
  19.  
  20. core0 {
  21. cpu = <0x2>;
  22. };
  23.  
  24. core1 {
  25. cpu = <0x3>;
  26. };
  27.  
  28. core2 {
  29. cpu = <0x4>;
  30. };
  31.  
  32. core3 {
  33. cpu = <0x5>;
  34. };
  35. };
  36.  
  37. cluster1 {
  38.  
  39. core0 {
  40. cpu = <0x6>;
  41. };
  42.  
  43. core1 {
  44. cpu = <0x7>;
  45. };
  46.  
  47. core2 {
  48. cpu = <0x8>;
  49. };
  50.  
  51. core3 {
  52. cpu = <0x9>;
  53. };
  54. };
  55. };
  56.  
  57. cpu@0 {
  58. device_type = "cpu";
  59. compatible = "arm,cortex-a53";
  60. reg = <0x0>;
  61. enable-method = "psci";
  62. qcom,acc = <0xa>;
  63. qcom,limits-info = <0xb>;
  64. qcom,ea = <0xc>;
  65. next-level-cache = <0xd>;
  66. linux,phandle = <0x2>;
  67. phandle = <0x2>;
  68.  
  69. l2-cache {
  70. compatible = "arm,arch-cache";
  71. cache-level = <0x2>;
  72. power-domain = <0xe>;
  73. qcom,dump-size = <0x0>;
  74. linux,phandle = <0xd>;
  75. phandle = <0xd>;
  76. };
  77.  
  78. l1-icache {
  79. compatible = "arm,arch-cache";
  80. qcom,dump-size = <0x8800>;
  81. linux,phandle = <0x26>;
  82. phandle = <0x26>;
  83. };
  84.  
  85. l1-dcache {
  86. compatible = "arm,arch-cache";
  87. qcom,dump-size = <0x9000>;
  88. linux,phandle = <0x2e>;
  89. phandle = <0x2e>;
  90. };
  91. };
  92.  
  93. cpu@1 {
  94. device_type = "cpu";
  95. compatible = "arm,cortex-a53";
  96. enable-method = "psci";
  97. reg = <0x1>;
  98. qcom,acc = <0xf>;
  99. qcom,limits-info = <0x10>;
  100. qcom,ea = <0x11>;
  101. next-level-cache = <0xd>;
  102. linux,phandle = <0x3>;
  103. phandle = <0x3>;
  104.  
  105. l1-icache {
  106. compatible = "arm,arch-cache";
  107. qcom,dump-size = <0x8800>;
  108. linux,phandle = <0x27>;
  109. phandle = <0x27>;
  110. };
  111.  
  112. l1-dcache {
  113. compatible = "arm,arch-cache";
  114. qcom,dump-size = <0x9000>;
  115. linux,phandle = <0x2f>;
  116. phandle = <0x2f>;
  117. };
  118. };
  119.  
  120. cpu@2 {
  121. device_type = "cpu";
  122. compatible = "arm,cortex-a53";
  123. enable-method = "psci";
  124. reg = <0x2>;
  125. qcom,acc = <0x12>;
  126. qcom,limits-info = <0x13>;
  127. qcom,ea = <0x14>;
  128. next-level-cache = <0xd>;
  129. linux,phandle = <0x4>;
  130. phandle = <0x4>;
  131.  
  132. l1-icache {
  133. compatible = "arm,arch-cache";
  134. qcom,dump-size = <0x8800>;
  135. linux,phandle = <0x28>;
  136. phandle = <0x28>;
  137. };
  138.  
  139. l1-dcache {
  140. compatible = "arm,arch-cache";
  141. qcom,dump-size = <0x9000>;
  142. linux,phandle = <0x30>;
  143. phandle = <0x30>;
  144. };
  145. };
  146.  
  147. cpu@3 {
  148. device_type = "cpu";
  149. compatible = "arm,cortex-a53";
  150. enable-method = "psci";
  151. reg = <0x3>;
  152. qcom,acc = <0x15>;
  153. qcom,limits-info = <0x16>;
  154. qcom,ea = <0x17>;
  155. next-level-cache = <0xd>;
  156. linux,phandle = <0x5>;
  157. phandle = <0x5>;
  158.  
  159. l1-icache {
  160. compatible = "arm,arch-cache";
  161. qcom,dump-size = <0x8800>;
  162. linux,phandle = <0x29>;
  163. phandle = <0x29>;
  164. };
  165.  
  166. l1-dcache {
  167. compatible = "arm,arch-cache";
  168. qcom,dump-size = <0x9000>;
  169. linux,phandle = <0x31>;
  170. phandle = <0x31>;
  171. };
  172. };
  173.  
  174. cpu@100 {
  175. device_type = "cpu";
  176. compatible = "arm,cortex-a53";
  177. enable-method = "psci";
  178. reg = <0x100>;
  179. qcom,acc = <0x18>;
  180. qcom,limits-info = <0x19>;
  181. qcom,ea = <0x1a>;
  182. next-level-cache = <0x1b>;
  183. linux,phandle = <0x6>;
  184. phandle = <0x6>;
  185.  
  186. l2-cache {
  187. compatible = "arm,arch-cache";
  188. cache-level = <0x2>;
  189. power-domain = <0x1c>;
  190. qcom,dump-size = <0x0>;
  191. linux,phandle = <0x1b>;
  192. phandle = <0x1b>;
  193. };
  194.  
  195. l1-icache {
  196. compatible = "arm,arch-cache";
  197. qcom,dump-size = <0x8800>;
  198. linux,phandle = <0x2a>;
  199. phandle = <0x2a>;
  200. };
  201.  
  202. l1-dcache {
  203. compatible = "arm,arch-cache";
  204. qcom,dump-size = <0x9000>;
  205. linux,phandle = <0x32>;
  206. phandle = <0x32>;
  207. };
  208. };
  209.  
  210. cpu@101 {
  211. device_type = "cpu";
  212. compatible = "arm,cortex-a53";
  213. enable-method = "psci";
  214. reg = <0x101>;
  215. qcom,acc = <0x1d>;
  216. qcom,limits-info = <0x1e>;
  217. qcom,ea = <0x1f>;
  218. next-level-cache = <0x1b>;
  219. linux,phandle = <0x7>;
  220. phandle = <0x7>;
  221.  
  222. l1-icache {
  223. compatible = "arm,arch-cache";
  224. qcom,dump-size = <0x8800>;
  225. linux,phandle = <0x2b>;
  226. phandle = <0x2b>;
  227. };
  228.  
  229. l1-dcache {
  230. compatible = "arm,arch-cache";
  231. qcom,dump-size = <0x9000>;
  232. linux,phandle = <0x33>;
  233. phandle = <0x33>;
  234. };
  235. };
  236.  
  237. cpu@102 {
  238. device_type = "cpu";
  239. compatible = "arm,cortex-a53";
  240. enable-method = "psci";
  241. reg = <0x102>;
  242. qcom,acc = <0x20>;
  243. qcom,limits-info = <0x21>;
  244. qcom,ea = <0x22>;
  245. next-level-cache = <0x1b>;
  246. linux,phandle = <0x8>;
  247. phandle = <0x8>;
  248.  
  249. l1-icache {
  250. compatible = "arm,arch-cache";
  251. qcom,dump-size = <0x8800>;
  252. linux,phandle = <0x2c>;
  253. phandle = <0x2c>;
  254. };
  255.  
  256. l1-dcache {
  257. compatible = "arm,arch-cache";
  258. qcom,dump-size = <0x9000>;
  259. linux,phandle = <0x34>;
  260. phandle = <0x34>;
  261. };
  262. };
  263.  
  264. cpu@103 {
  265. device_type = "cpu";
  266. compatible = "arm,cortex-a53";
  267. enable-method = "psci";
  268. reg = <0x103>;
  269. qcom,acc = <0x23>;
  270. qcom,limits-info = <0x24>;
  271. qcom,ea = <0x25>;
  272. next-level-cache = <0x1b>;
  273. linux,phandle = <0x9>;
  274. phandle = <0x9>;
  275.  
  276. l1-icache {
  277. compatible = "arm,arch-cache";
  278. qcom,dump-size = <0x8800>;
  279. linux,phandle = <0x2d>;
  280. phandle = <0x2d>;
  281. };
  282.  
  283. l1-dcache {
  284. compatible = "arm,arch-cache";
  285. qcom,dump-size = <0x9000>;
  286. linux,phandle = <0x35>;
  287. phandle = <0x35>;
  288. };
  289. };
  290. };
  291.  
  292. soc {
  293. #address-cells = <0x1>;
  294. #size-cells = <0x1>;
  295. ranges = <0x0 0x0 0x0 0xffffffff>;
  296. compatible = "simple-bus";
  297.  
  298. pinctrl@1000000 {
  299. compatible = "qcom,msm8953-pinctrl";
  300. reg = <0x1000000 0x300000>;
  301. interrupts = <0x0 0xd0 0x0>;
  302. gpio-controller;
  303. #gpio-cells = <0x2>;
  304. interrupt-controller;
  305. #interrupt-cells = <0x2>;
  306. linux,phandle = <0xbe>;
  307. phandle = <0xbe>;
  308.  
  309. pmx-uartconsole {
  310.  
  311. uart_console_active {
  312. linux,phandle = <0xca>;
  313. phandle = <0xca>;
  314.  
  315. mux {
  316. pins = "gpio4", "gpio5";
  317. function = "blsp_uart2";
  318. };
  319.  
  320. config {
  321. pins = "gpio4", "gpio5";
  322. drive-strength = <0x2>;
  323. bias-disable;
  324. };
  325. };
  326.  
  327. uart_console_sleep {
  328.  
  329. mux {
  330. pins = "gpio4", "gpio5";
  331. function = "blsp_uart2";
  332. };
  333.  
  334. config {
  335. pins = "gpio4", "gpio5";
  336. drive-strength = <0x2>;
  337. bias-pull-down;
  338. };
  339. };
  340. };
  341.  
  342. cci {
  343.  
  344. cci0_active {
  345. linux,phandle = <0x17f>;
  346. phandle = <0x17f>;
  347.  
  348. mux {
  349. pins = "gpio29", "gpio30";
  350. function = "cci_i2c";
  351. };
  352.  
  353. config {
  354. pins = "gpio29", "gpio30";
  355. drive-strength = <0x2>;
  356. bias-disable;
  357. };
  358. };
  359.  
  360. cci0_suspend {
  361. linux,phandle = <0x181>;
  362. phandle = <0x181>;
  363.  
  364. mux {
  365. pins = "gpio29", "gpio30";
  366. function = "cci_i2c";
  367. };
  368.  
  369. config {
  370. pins = "gpio29", "gpio30";
  371. drive-strength = <0x2>;
  372. bias-disable;
  373. };
  374. };
  375.  
  376. cci1_active {
  377. linux,phandle = <0x180>;
  378. phandle = <0x180>;
  379.  
  380. mux {
  381. pins = "gpio31", "gpio32";
  382. function = "cci_i2c";
  383. };
  384.  
  385. config {
  386. pins = "gpio31", "gpio32";
  387. drive-strength = <0x2>;
  388. bias-disable;
  389. };
  390. };
  391.  
  392. cci1_suspend {
  393. linux,phandle = <0x182>;
  394. phandle = <0x182>;
  395.  
  396. mux {
  397. pins = "gpio31", "gpio32";
  398. function = "cci_i2c";
  399. };
  400.  
  401. config {
  402. pins = "gpio31", "gpio32";
  403. drive-strength = <0x2>;
  404. bias-disable;
  405. };
  406. };
  407. };
  408.  
  409. cam_sensor_mclk0_default {
  410. linux,phandle = <0x187>;
  411. phandle = <0x187>;
  412.  
  413. mux {
  414. pins = "gpio26";
  415. function = "cam_mclk";
  416. };
  417.  
  418. config {
  419. pins = "gpio26";
  420. bias-disable;
  421. drive-strength = <0x2>;
  422. };
  423. };
  424.  
  425. cam_sensor_mclk0_sleep {
  426. linux,phandle = <0x189>;
  427. phandle = <0x189>;
  428.  
  429. mux {
  430. pins = "gpio26";
  431. function = "cam_mclk";
  432. };
  433.  
  434. config {
  435. pins = "gpio26";
  436. bias-pull-down;
  437. drive-strength = <0x2>;
  438. };
  439. };
  440.  
  441. cam_sensor_rear_default {
  442. linux,phandle = <0x188>;
  443. phandle = <0x188>;
  444.  
  445. mux {
  446. pins = "gpio40", "gpio39";
  447. function = "gpio";
  448. };
  449.  
  450. config {
  451. pins = "gpio40", "gpio39";
  452. bias-disable;
  453. drive-strength = <0x2>;
  454. };
  455. };
  456.  
  457. cam_sensor_rear_sleep {
  458. linux,phandle = <0x18a>;
  459. phandle = <0x18a>;
  460.  
  461. mux {
  462. pins = "gpio40", "gpio39";
  463. function = "gpio";
  464. };
  465.  
  466. config {
  467. pins = "gpio40", "gpio39";
  468. bias-disable;
  469. drive-strength = <0x2>;
  470. };
  471. };
  472.  
  473. cam_sensor_rear_vdig {
  474.  
  475. mux {
  476. pins = "gpio134";
  477. function = "gpio";
  478. };
  479.  
  480. config {
  481. pins = "gpio134";
  482. bias-disable;
  483. drive-strength = <0x2>;
  484. };
  485. };
  486.  
  487. cam_sensor_rear_vdig_sleep {
  488.  
  489. mux {
  490. pins = "gpio134";
  491. function = "gpio";
  492. };
  493.  
  494. config {
  495. pins = "gpio134";
  496. bias-disable;
  497. drive-strength = <0x2>;
  498. };
  499. };
  500.  
  501. cam_sensor_mclk1_default {
  502. linux,phandle = <0x18c>;
  503. phandle = <0x18c>;
  504.  
  505. mux {
  506. pins = "gpio27";
  507. function = "cam_mclk";
  508. };
  509.  
  510. config {
  511. pins = "gpio27";
  512. bias-disable;
  513. drive-strength = <0x2>;
  514. };
  515. };
  516.  
  517. cam_sensor_mclk1_sleep {
  518. linux,phandle = <0x18e>;
  519. phandle = <0x18e>;
  520.  
  521. mux {
  522. pins = "gpio27";
  523. function = "cam_mclk";
  524. };
  525.  
  526. config {
  527. pins = "gpio27";
  528. bias-pull-down;
  529. drive-strength = <0x2>;
  530. };
  531. };
  532.  
  533. cam_sensor_front_default {
  534.  
  535. mux {
  536. pins = "gpio131", "gpio132";
  537. function = "gpio";
  538. };
  539.  
  540. config {
  541. pins = "gpio131", "gpio132";
  542. bias-disable;
  543. drive-strength = <0x2>;
  544. };
  545. };
  546.  
  547. cam_sensor_front_sleep {
  548.  
  549. mux {
  550. pins = "gpio131", "gpio132";
  551. function = "gpio";
  552. };
  553.  
  554. config {
  555. pins = "gpio131", "gpio132";
  556. bias-disable;
  557. drive-strength = <0x2>;
  558. };
  559. };
  560.  
  561. cam_sensor_mclk2_default {
  562.  
  563. mux {
  564. pins = "gpio28";
  565. function = "cam_mclk";
  566. };
  567.  
  568. config {
  569. pins = "gpio28";
  570. bias-disable;
  571. drive-strength = <0x2>;
  572. };
  573. };
  574.  
  575. cam_sensor_mclk2_sleep {
  576.  
  577. mux {
  578. pins = "gpio28";
  579. function = "cam_mclk";
  580. };
  581.  
  582. config {
  583. pins = "gpio28";
  584. bias-pull-down;
  585. drive-strength = <0x2>;
  586. };
  587. };
  588.  
  589. cam_sensor_front1_default {
  590. linux,phandle = <0x18d>;
  591. phandle = <0x18d>;
  592.  
  593. mux {
  594. pins = "gpio129", "gpio130";
  595. function = "gpio";
  596. };
  597.  
  598. config {
  599. pins = "gpio129", "gpio130";
  600. bias-disable;
  601. drive-strength = <0x2>;
  602. };
  603. };
  604.  
  605. cam_sensor_front1_sleep {
  606. linux,phandle = <0x18f>;
  607. phandle = <0x18f>;
  608.  
  609. mux {
  610. pins = "gpio129", "gpio130";
  611. function = "gpio";
  612. };
  613.  
  614. config {
  615. pins = "gpio129", "gpio130";
  616. bias-disable;
  617. drive-strength = <0x2>;
  618. };
  619. };
  620.  
  621. pmx_adv7533_int {
  622.  
  623. adv7533_int_active {
  624. linux,phandle = <0xd5>;
  625. phandle = <0xd5>;
  626.  
  627. mux {
  628. pins = "gpio90";
  629. function = "gpio";
  630. };
  631.  
  632. config {
  633. pins = "gpio90";
  634. drive-strength = <0x10>;
  635. bias-disable;
  636. };
  637. };
  638.  
  639. adv7533_int_suspend {
  640. linux,phandle = <0xd6>;
  641. phandle = <0xd6>;
  642.  
  643. mux {
  644. pins = "gpio90";
  645. function = "gpio";
  646. };
  647.  
  648. config {
  649. pins = "gpio90";
  650. drive-strength = <0x10>;
  651. bias-disable;
  652. };
  653. };
  654. };
  655.  
  656. pmx_mdss {
  657.  
  658. mdss_dsi_active {
  659. linux,phandle = <0x1a1>;
  660. phandle = <0x1a1>;
  661.  
  662. mux {
  663. pins = "gpio61", "gpio59";
  664. function = "gpio";
  665. };
  666.  
  667. config {
  668. pins = "gpio61", "gpio59";
  669. drive-strength = <0x8>;
  670. bias-disable = <0x0>;
  671. output-high;
  672. };
  673. };
  674.  
  675. mdss_dsi_suspend {
  676. linux,phandle = <0x1a3>;
  677. phandle = <0x1a3>;
  678.  
  679. mux {
  680. pins = "gpio61", "gpio59";
  681. function = "gpio";
  682. };
  683.  
  684. config {
  685. pins = "gpio61", "gpio59";
  686. drive-strength = <0x2>;
  687. bias-pull-down;
  688. };
  689. };
  690. };
  691.  
  692. pmx_mdss_te {
  693.  
  694. mdss_te_active {
  695. linux,phandle = <0x1a2>;
  696. phandle = <0x1a2>;
  697.  
  698. mux {
  699. pins = "gpio24";
  700. function = "mdp_vsync";
  701. };
  702.  
  703. config {
  704. pins = "gpio24";
  705. drive-strength = <0x2>;
  706. bias-pull-down;
  707. };
  708. };
  709.  
  710. mdss_te_suspend {
  711. linux,phandle = <0x1a4>;
  712. phandle = <0x1a4>;
  713.  
  714. mux {
  715. pins = "gpio24";
  716. function = "mdp_vsync";
  717. };
  718.  
  719. config {
  720. pins = "gpio24";
  721. drive-strength = <0x2>;
  722. bias-pull-down;
  723. };
  724. };
  725. };
  726.  
  727. default {
  728. linux,phandle = <0xcd>;
  729. phandle = <0xcd>;
  730.  
  731. mux {
  732. pins = "gpio12", "gpio13", "gpio14", "gpio15";
  733. function = "blsp_uart4";
  734. };
  735.  
  736. config {
  737. pins = "gpio12", "gpio13", "gpio14", "gpio15";
  738. drive-strength = <0x10>;
  739. bias-disable;
  740. };
  741. };
  742.  
  743. sleep {
  744. linux,phandle = <0xcc>;
  745. phandle = <0xcc>;
  746.  
  747. mux {
  748. pins = "gpio12", "gpio13", "gpio14", "gpio15";
  749. function = "gpio";
  750. };
  751.  
  752. config {
  753. pins = "gpio12", "gpio13", "gpio14", "gpio15";
  754. drive-strength = <0x2>;
  755. bias-disable;
  756. };
  757. };
  758.  
  759. fpc_spi_active {
  760. linux,phandle = <0x1b4>;
  761. phandle = <0x1b4>;
  762.  
  763. mux {
  764. pins = "gpio135", "gpio136", "gpio137", "gpio138";
  765. function = "blsp_spi7";
  766. };
  767.  
  768. config {
  769. pins = "gpio135", "gpio136", "gpio137", "gpio138";
  770. drive-strength = <0x2>;
  771. bias-disable;
  772. };
  773. };
  774.  
  775. fpc_reset_reset {
  776. linux,phandle = <0x1b5>;
  777. phandle = <0x1b5>;
  778.  
  779. mux {
  780. pins = "gpio140";
  781. function = "gpio";
  782. };
  783.  
  784. config {
  785. pins = "gpio140";
  786. drive-strength = <0x2>;
  787. bias-disable;
  788. output-low;
  789. };
  790. };
  791.  
  792. fpc_reset_active {
  793. linux,phandle = <0x1b6>;
  794. phandle = <0x1b6>;
  795.  
  796. mux {
  797. pins = "gpio140";
  798. function = "gpio";
  799. };
  800.  
  801. config {
  802. pins = "gpio140";
  803. drive-strength = <0x2>;
  804. bias-disable;
  805. output-high;
  806. };
  807. };
  808.  
  809. fpc_irq_active {
  810. linux,phandle = <0x1b7>;
  811. phandle = <0x1b7>;
  812.  
  813. mux {
  814. pins = "gpio48";
  815. function = "gpio";
  816. };
  817.  
  818. config {
  819. pins = "gpio48";
  820. drive-strength = <0x2>;
  821. bias-disable;
  822. input-enable;
  823. };
  824. };
  825.  
  826. sdc1_clk_on {
  827. linux,phandle = <0x107>;
  828. phandle = <0x107>;
  829.  
  830. config {
  831. pins = "sdc1_clk";
  832. bias-disable;
  833. drive-strength = <0x10>;
  834. };
  835. };
  836.  
  837. sdc1_clk_off {
  838. linux,phandle = <0x10b>;
  839. phandle = <0x10b>;
  840.  
  841. config {
  842. pins = "sdc1_clk";
  843. bias-disable;
  844. drive-strength = <0x2>;
  845. };
  846. };
  847.  
  848. sdc1_cmd_on {
  849. linux,phandle = <0x108>;
  850. phandle = <0x108>;
  851.  
  852. config {
  853. pins = "sdc1_cmd";
  854. bias-pull-up;
  855. drive-strength = <0xa>;
  856. };
  857. };
  858.  
  859. sdc1_cmd_off {
  860. linux,phandle = <0x10c>;
  861. phandle = <0x10c>;
  862.  
  863. config {
  864. pins = "sdc1_cmd";
  865. num-grp-pins = <0x1>;
  866. bias-pull-up;
  867. drive-strength = <0x2>;
  868. };
  869. };
  870.  
  871. sdc1_data_on {
  872. linux,phandle = <0x109>;
  873. phandle = <0x109>;
  874.  
  875. config {
  876. pins = "sdc1_data";
  877. bias-pull-up;
  878. drive-strength = <0xa>;
  879. };
  880. };
  881.  
  882. sdc1_data_off {
  883. linux,phandle = <0x10d>;
  884. phandle = <0x10d>;
  885.  
  886. config {
  887. pins = "sdc1_data";
  888. bias-pull-up;
  889. drive-strength = <0x2>;
  890. };
  891. };
  892.  
  893. sdc1_rclk_on {
  894. linux,phandle = <0x10a>;
  895. phandle = <0x10a>;
  896.  
  897. config {
  898. pins = "sdc1_rclk";
  899. bias-pull-down;
  900. };
  901. };
  902.  
  903. sdc1_rclk_off {
  904. linux,phandle = <0x10e>;
  905. phandle = <0x10e>;
  906.  
  907. config {
  908. pins = "sdc1_rclk";
  909. bias-pull-down;
  910. };
  911. };
  912.  
  913. sdc2_clk_on {
  914. linux,phandle = <0x10f>;
  915. phandle = <0x10f>;
  916.  
  917. config {
  918. pins = "sdc2_clk";
  919. drive-strength = <0x10>;
  920. bias-disable;
  921. };
  922. };
  923.  
  924. sdc2_clk_off {
  925. linux,phandle = <0x113>;
  926. phandle = <0x113>;
  927.  
  928. config {
  929. pins = "sdc2_clk";
  930. bias-disable;
  931. drive-strength = <0x2>;
  932. };
  933. };
  934.  
  935. sdc2_cmd_on {
  936. linux,phandle = <0x110>;
  937. phandle = <0x110>;
  938.  
  939. config {
  940. pins = "sdc2_cmd";
  941. bias-pull-up;
  942. drive-strength = <0xc>;
  943. };
  944. };
  945.  
  946. sdc2_cmd_off {
  947. linux,phandle = <0x114>;
  948. phandle = <0x114>;
  949.  
  950. config {
  951. pins = "sdc2_cmd";
  952. bias-pull-up;
  953. drive-strength = <0x2>;
  954. };
  955. };
  956.  
  957. sdc2_data_on {
  958. linux,phandle = <0x111>;
  959. phandle = <0x111>;
  960.  
  961. config {
  962. pins = "sdc2_data";
  963. bias-pull-up;
  964. drive-strength = <0xc>;
  965. };
  966. };
  967.  
  968. sdc2_data_off {
  969. linux,phandle = <0x115>;
  970. phandle = <0x115>;
  971.  
  972. config {
  973. pins = "sdc2_data";
  974. bias-pull-up;
  975. drive-strength = <0x2>;
  976. };
  977. };
  978.  
  979. gpio_led_pins {
  980.  
  981. gpio_led_off {
  982. linux,phandle = <0x1b3>;
  983. phandle = <0x1b3>;
  984.  
  985. mux {
  986. pins = "gpio45";
  987. function = "gpio";
  988. };
  989.  
  990. config {
  991. pins = "gpio45";
  992. drive-strength = <0x2>;
  993. bias-disable;
  994. output-low;
  995. };
  996. };
  997. };
  998.  
  999. cd_on {
  1000. linux,phandle = <0x112>;
  1001. phandle = <0x112>;
  1002.  
  1003. mux {
  1004. pins = "gpio133";
  1005. function = "gpio";
  1006. };
  1007.  
  1008. config {
  1009. pins = "gpio133";
  1010. drive-strength = <0x2>;
  1011. bias-pull-up;
  1012. };
  1013. };
  1014.  
  1015. cd_off {
  1016. linux,phandle = <0x116>;
  1017. phandle = <0x116>;
  1018.  
  1019. mux {
  1020. pins = "gpio133";
  1021. function = "gpio";
  1022. };
  1023.  
  1024. config {
  1025. pins = "gpio133";
  1026. drive-strength = <0x2>;
  1027. bias-disable;
  1028. };
  1029. };
  1030.  
  1031. i2c_2 {
  1032.  
  1033. i2c_2_active {
  1034. linux,phandle = <0xd2>;
  1035. phandle = <0xd2>;
  1036.  
  1037. mux {
  1038. pins = "gpio6", "gpio7";
  1039. function = "blsp_i2c2";
  1040. };
  1041.  
  1042. config {
  1043. pins = "gpio6", "gpio7";
  1044. drive-strength = <0x2>;
  1045. bias-disable;
  1046. };
  1047. };
  1048.  
  1049. i2c_2_sleep {
  1050. linux,phandle = <0xd3>;
  1051. phandle = <0xd3>;
  1052.  
  1053. mux {
  1054. pins = "gpio6", "gpio7";
  1055. function = "gpio";
  1056. };
  1057.  
  1058. config {
  1059. pins = "gpio6", "gpio7";
  1060. drive-strength = <0x2>;
  1061. bias-disable;
  1062. };
  1063. };
  1064. };
  1065.  
  1066. i2c_3 {
  1067.  
  1068. i2c_3_active {
  1069. linux,phandle = <0xdf>;
  1070. phandle = <0xdf>;
  1071.  
  1072. mux {
  1073. pins = "gpio10", "gpio11";
  1074. function = "blsp_i2c3";
  1075. };
  1076.  
  1077. config {
  1078. pins = "gpio10", "gpio11";
  1079. drive-strength = <0x2>;
  1080. bias-disable;
  1081. };
  1082. };
  1083.  
  1084. i2c_3_sleep {
  1085. linux,phandle = <0xe0>;
  1086. phandle = <0xe0>;
  1087.  
  1088. mux {
  1089. pins = "gpio10", "gpio11";
  1090. function = "gpio";
  1091. };
  1092.  
  1093. config {
  1094. pins = "gpio10", "gpio11";
  1095. drive-strength = <0x2>;
  1096. bias-disable;
  1097. };
  1098. };
  1099. };
  1100.  
  1101. i2c_5 {
  1102.  
  1103. i2c_5_active {
  1104. linux,phandle = <0xe7>;
  1105. phandle = <0xe7>;
  1106.  
  1107. mux {
  1108. pins = "gpio18", "gpio19";
  1109. function = "blsp_i2c5";
  1110. };
  1111.  
  1112. config {
  1113. pins = "gpio18", "gpio19";
  1114. drive-strength = <0x2>;
  1115. bias-disable;
  1116. };
  1117. };
  1118.  
  1119. i2c_5_sleep {
  1120. linux,phandle = <0xe8>;
  1121. phandle = <0xe8>;
  1122.  
  1123. mux {
  1124. pins = "gpio18", "gpio19";
  1125. function = "gpio";
  1126. };
  1127.  
  1128. config {
  1129. pins = "gpio18", "gpio19";
  1130. drive-strength = <0x2>;
  1131. bias-disable;
  1132. };
  1133. };
  1134. };
  1135.  
  1136. pmx_rd_nfc_int {
  1137. pins = "gpio17";
  1138. qcom,pin-func = <0x0>;
  1139. qcom,num-grp-pins = <0x1>;
  1140. label = "pmx_nfc_int";
  1141.  
  1142. active {
  1143. drive-strength = <0x6>;
  1144. bias-pull-up;
  1145. linux,phandle = <0xeb>;
  1146. phandle = <0xeb>;
  1147. };
  1148.  
  1149. suspend {
  1150. drive-strength = <0x6>;
  1151. bias-pull-up;
  1152. linux,phandle = <0xed>;
  1153. phandle = <0xed>;
  1154. };
  1155. };
  1156.  
  1157. pmx_nfc_reset {
  1158. pins = "gpio16";
  1159. qcom,pin-func = <0x0>;
  1160. qcom,num-grp-pins = <0x1>;
  1161. label = "pmx_nfc_disable";
  1162.  
  1163. active {
  1164. drive-strength = <0x6>;
  1165. bias-pull-up;
  1166. linux,phandle = <0xec>;
  1167. phandle = <0xec>;
  1168. };
  1169.  
  1170. suspend {
  1171. drive-strength = <0x6>;
  1172. bias-disable;
  1173. linux,phandle = <0xee>;
  1174. phandle = <0xee>;
  1175. };
  1176. };
  1177.  
  1178. wcnss_pmux_5wire {
  1179.  
  1180. wcnss_default {
  1181. linux,phandle = <0xfe>;
  1182. phandle = <0xfe>;
  1183.  
  1184. wcss_wlan2 {
  1185. pins = "gpio76";
  1186. function = "wcss_wlan2";
  1187. };
  1188.  
  1189. wcss_wlan1 {
  1190. pins = "gpio77";
  1191. function = "wcss_wlan1";
  1192. };
  1193.  
  1194. wcss_wlan0 {
  1195. pins = "gpio78";
  1196. function = "wcss_wlan0";
  1197. };
  1198.  
  1199. wcss_wlan {
  1200. pins = "gpio79", "gpio80";
  1201. function = "wcss_wlan";
  1202. };
  1203.  
  1204. config {
  1205. pins = "gpio76", "gpio77", "gpio78", "gpio79", "gpio80";
  1206. drive-strength = <0x6>;
  1207. bias-pull-up;
  1208. };
  1209. };
  1210.  
  1211. wcnss_sleep {
  1212. linux,phandle = <0xff>;
  1213. phandle = <0xff>;
  1214.  
  1215. wcss_wlan2 {
  1216. pins = "gpio76";
  1217. function = "wcss_wlan2";
  1218. };
  1219.  
  1220. wcss_wlan1 {
  1221. pins = "gpio77";
  1222. function = "wcss_wlan1";
  1223. };
  1224.  
  1225. wcss_wlan0 {
  1226. pins = "gpio78";
  1227. function = "wcss_wlan0";
  1228. };
  1229.  
  1230. wcss_wlan {
  1231. pins = "gpio79", "gpio80";
  1232. function = "wcss_wlan";
  1233. };
  1234.  
  1235. config {
  1236. pins = "gpio76", "gpio77", "gpio78", "gpio79", "gpio80";
  1237. drive-strength = <0x2>;
  1238. bias-pull-down;
  1239. };
  1240. };
  1241. };
  1242.  
  1243. wcnss_pmux_gpio {
  1244.  
  1245. wcnss_gpio_default {
  1246. linux,phandle = <0x100>;
  1247. phandle = <0x100>;
  1248.  
  1249. mux {
  1250. pins = "gpio76", "gpio77", "gpio78", "gpio79", "gpio80";
  1251. function = "gpio";
  1252. };
  1253.  
  1254. config {
  1255. pins = "gpio76", "gpio77", "gpio78", "gpio79", "gpio80";
  1256. drive-strength = <0x6>;
  1257. bias-pull-up;
  1258. };
  1259. };
  1260. };
  1261.  
  1262. wcd9xxx_intr {
  1263.  
  1264. wcd_intr_default {
  1265. linux,phandle = <0x173>;
  1266. phandle = <0x173>;
  1267.  
  1268. mux {
  1269. pins = "gpio73";
  1270. function = "gpio";
  1271. };
  1272.  
  1273. config {
  1274. pins = "gpio73";
  1275. drive-strength = <0x2>;
  1276. bias-pull-down;
  1277. input-enable;
  1278. };
  1279. };
  1280. };
  1281.  
  1282. cdc_reset_ctrl {
  1283.  
  1284. cdc_reset_sleep {
  1285. linux,phandle = <0x175>;
  1286. phandle = <0x175>;
  1287.  
  1288. mux {
  1289. pins = "gpio67";
  1290. function = "gpio";
  1291. };
  1292.  
  1293. config {
  1294. pins = "gpio67";
  1295. drive-strength = <0x10>;
  1296. bias-disable;
  1297. output-low;
  1298. };
  1299. };
  1300.  
  1301. cdc_reset_active {
  1302. linux,phandle = <0x174>;
  1303. phandle = <0x174>;
  1304.  
  1305. mux {
  1306. pins = "gpio67";
  1307. function = "gpio";
  1308. };
  1309.  
  1310. config {
  1311. pins = "gpio67";
  1312. drive-strength = <0x10>;
  1313. bias-pull-down;
  1314. output-high;
  1315. };
  1316. };
  1317. };
  1318.  
  1319. cdc_mclk2_pin {
  1320.  
  1321. cdc_mclk2_sleep {
  1322. linux,phandle = <0x176>;
  1323. phandle = <0x176>;
  1324.  
  1325. mux {
  1326. pins = "gpio66";
  1327. function = "pri_mi2s";
  1328. };
  1329.  
  1330. config {
  1331. pins = "gpio66";
  1332. drive-strength = <0x2>;
  1333. bias-pull-down;
  1334. };
  1335. };
  1336.  
  1337. cdc_mclk2_active {
  1338. linux,phandle = <0x177>;
  1339. phandle = <0x177>;
  1340.  
  1341. mux {
  1342. pins = "gpio66";
  1343. function = "pri_mi2s";
  1344. };
  1345.  
  1346. config {
  1347. pins = "gpio66";
  1348. drive-strength = <0x8>;
  1349. bias-disable;
  1350. };
  1351. };
  1352. };
  1353.  
  1354. cdc-pdm-2-lines {
  1355.  
  1356. pdm_lines_2_on {
  1357. linux,phandle = <0x13b>;
  1358. phandle = <0x13b>;
  1359.  
  1360. mux {
  1361. pins = "gpio70", "gpio71", "gpio72";
  1362. function = "cdc_pdm0";
  1363. };
  1364.  
  1365. config {
  1366. pins = "gpio70", "gpio71", "gpio72";
  1367. drive-strength = <0x8>;
  1368. };
  1369. };
  1370.  
  1371. pdm_lines_2_off {
  1372. linux,phandle = <0x136>;
  1373. phandle = <0x136>;
  1374.  
  1375. mux {
  1376. pins = "gpio70", "gpio71", "gpio72";
  1377. function = "cdc_pdm0";
  1378. };
  1379.  
  1380. config {
  1381. pins = "gpio70", "gpio71", "gpio72";
  1382. drive-strength = <0x2>;
  1383. bias-disable;
  1384. };
  1385. };
  1386. };
  1387.  
  1388. cdc-pdm-lines {
  1389.  
  1390. pdm_lines_on {
  1391. linux,phandle = <0x13a>;
  1392. phandle = <0x13a>;
  1393.  
  1394. mux {
  1395. pins = "gpio69", "gpio73", "gpio74";
  1396. function = "cdc_pdm0";
  1397. };
  1398.  
  1399. config {
  1400. pins = "gpio69", "gpio73", "gpio74";
  1401. drive-strength = <0x8>;
  1402. };
  1403. };
  1404.  
  1405. pdm_lines_off {
  1406. linux,phandle = <0x134>;
  1407. phandle = <0x134>;
  1408.  
  1409. mux {
  1410. pins = "gpio69", "gpio73", "gpio74";
  1411. function = "cdc_pdm0";
  1412. };
  1413.  
  1414. config {
  1415. pins = "gpio69", "gpio73", "gpio74";
  1416. drive-strength = <0x2>;
  1417. bias-disable;
  1418. };
  1419. };
  1420. };
  1421.  
  1422. cdc-pdm-comp-lines {
  1423.  
  1424. pdm_comp_lines_on {
  1425. linux,phandle = <0x166>;
  1426. phandle = <0x166>;
  1427.  
  1428. mux {
  1429. pins = "gpio67", "gpio68";
  1430. function = "cdc_pdm0";
  1431. };
  1432.  
  1433. config {
  1434. pins = "gpio67", "gpio68";
  1435. drive-strength = <0x8>;
  1436. };
  1437. };
  1438.  
  1439. pdm_comp_lines_off {
  1440. linux,phandle = <0x135>;
  1441. phandle = <0x135>;
  1442.  
  1443. mux {
  1444. pins = "gpio67", "gpio68";
  1445. function = "cdc_pdm0";
  1446. };
  1447.  
  1448. config {
  1449. pins = "gpio67", "gpio68";
  1450. drive-strength = <0x2>;
  1451. bias-disable;
  1452. };
  1453. };
  1454. };
  1455.  
  1456. cross-conn-det {
  1457.  
  1458. lines_on {
  1459. linux,phandle = <0x13c>;
  1460. phandle = <0x13c>;
  1461.  
  1462. mux {
  1463. pins = "gpio63";
  1464. function = "gpio";
  1465. };
  1466.  
  1467. config {
  1468. pins = "gpio63";
  1469. drive-strength = <0x8>;
  1470. output-low;
  1471. bias-pull-down;
  1472. };
  1473. };
  1474.  
  1475. lines_off {
  1476. linux,phandle = <0x137>;
  1477. phandle = <0x137>;
  1478.  
  1479. mux {
  1480. pins = "gpio63";
  1481. function = "gpio";
  1482. };
  1483.  
  1484. config {
  1485. pins = "gpio63";
  1486. drive-strength = <0x2>;
  1487. bias-pull-down;
  1488. };
  1489. };
  1490. };
  1491.  
  1492. wsa-vi {
  1493.  
  1494. wsa_vi_on {
  1495. linux,phandle = <0xdd>;
  1496. phandle = <0xdd>;
  1497.  
  1498. mux {
  1499. pins = "gpio94", "gpio95";
  1500. function = "wsa_io";
  1501. };
  1502.  
  1503. config {
  1504. pins = "gpio94", "gpio95";
  1505. drive-strength = <0x8>;
  1506. bias-disable;
  1507. };
  1508. };
  1509.  
  1510. wsa_vi_off {
  1511. linux,phandle = <0xda>;
  1512. phandle = <0xda>;
  1513.  
  1514. mux {
  1515. pins = "gpio94", "gpio95";
  1516. function = "wsa_io";
  1517. };
  1518.  
  1519. config {
  1520. pins = "gpio94", "gpio95";
  1521. drive-strength = <0x2>;
  1522. bias-pull-down;
  1523. };
  1524. };
  1525. };
  1526.  
  1527. wsa_reset {
  1528.  
  1529. wsa_reset_on {
  1530. linux,phandle = <0xdc>;
  1531. phandle = <0xdc>;
  1532.  
  1533. mux {
  1534. pins = "gpio96";
  1535. function = "gpio";
  1536. };
  1537.  
  1538. config {
  1539. pins = "gpio96";
  1540. drive-strength = <0x2>;
  1541. output-high;
  1542. };
  1543. };
  1544.  
  1545. wsa_reset_off {
  1546. linux,phandle = <0xd9>;
  1547. phandle = <0xd9>;
  1548.  
  1549. mux {
  1550. pins = "gpio96";
  1551. function = "gpio";
  1552. };
  1553.  
  1554. config {
  1555. pins = "gpio96";
  1556. drive-strength = <0x2>;
  1557. output-low;
  1558. };
  1559. };
  1560. };
  1561.  
  1562. wsa_clk {
  1563.  
  1564. wsa_clk_on {
  1565. linux,phandle = <0xdb>;
  1566. phandle = <0xdb>;
  1567.  
  1568. mux {
  1569. pins = "gpio25";
  1570. function = "pri_mi2s_mclk_a";
  1571. };
  1572.  
  1573. config {
  1574. pins = "gpio25";
  1575. drive-strength = <0x8>;
  1576. output-high;
  1577. };
  1578. };
  1579.  
  1580. wsa_clk_off {
  1581. linux,phandle = <0xd8>;
  1582. phandle = <0xd8>;
  1583.  
  1584. mux {
  1585. pins = "gpio25";
  1586. function = "pri_mi2s_mclk_a";
  1587. };
  1588.  
  1589. config {
  1590. pins = "gpio25";
  1591. drive-strength = <0x2>;
  1592. output-low;
  1593. bias-pull-down;
  1594. };
  1595. };
  1596. };
  1597.  
  1598. pri-tlmm-lines {
  1599.  
  1600. pri_tlmm_lines_act {
  1601. linux,phandle = <0x13d>;
  1602. phandle = <0x13d>;
  1603.  
  1604. mux {
  1605. pins = "gpio91", "gpio93";
  1606. function = "pri_mi2s";
  1607. };
  1608.  
  1609. config {
  1610. pins = "gpio91", "gpio93";
  1611. drive-strength = <0x8>;
  1612. };
  1613. };
  1614.  
  1615. pri_tlmm_lines_sus {
  1616. linux,phandle = <0x138>;
  1617. phandle = <0x138>;
  1618.  
  1619. mux {
  1620. pins = "gpio91", "gpio93";
  1621. function = "pri_mi2s";
  1622. };
  1623.  
  1624. config {
  1625. pins = "gpio91", "gpio93";
  1626. drive-strength = <0x2>;
  1627. bias-pull-down;
  1628. };
  1629. };
  1630. };
  1631.  
  1632. pri-tlmm-ws-lines {
  1633.  
  1634. pri_tlmm_ws_act {
  1635. linux,phandle = <0x13e>;
  1636. phandle = <0x13e>;
  1637.  
  1638. mux {
  1639. pins = "gpio92";
  1640. function = "pri_mi2s_ws";
  1641. };
  1642.  
  1643. config {
  1644. pins = "gpio92";
  1645. drive-strength = <0x8>;
  1646. };
  1647. };
  1648.  
  1649. pri_tlmm_ws_sus {
  1650. linux,phandle = <0x139>;
  1651. phandle = <0x139>;
  1652.  
  1653. mux {
  1654. pins = "gpio92";
  1655. function = "pri_mi2s_ws";
  1656. };
  1657.  
  1658. config {
  1659. pins = "gpio92";
  1660. drive-strength = <0x2>;
  1661. bias-pull-down;
  1662. };
  1663. };
  1664. };
  1665.  
  1666. spi3 {
  1667.  
  1668. spi3_default {
  1669. linux,phandle = <0xce>;
  1670. phandle = <0xce>;
  1671.  
  1672. mux {
  1673. pins = "gpio8", "gpio9", "gpio11";
  1674. function = "blsp_spi3";
  1675. };
  1676.  
  1677. config {
  1678. pins = "gpio8", "gpio9", "gpio11";
  1679. drive-strength = <0xc>;
  1680. bias-disable = <0x0>;
  1681. };
  1682. };
  1683.  
  1684. spi3_sleep {
  1685. linux,phandle = <0xd0>;
  1686. phandle = <0xd0>;
  1687.  
  1688. mux {
  1689. pins = "gpio8", "gpio9", "gpio11";
  1690. function = "gpio";
  1691. };
  1692.  
  1693. config {
  1694. pins = "gpio8", "gpio9", "gpio11";
  1695. drive-strength = <0x2>;
  1696. bias-pull-down;
  1697. };
  1698. };
  1699.  
  1700. cs0_active {
  1701. linux,phandle = <0xcf>;
  1702. phandle = <0xcf>;
  1703.  
  1704. mux {
  1705. pins = "gpio10";
  1706. function = "blsp_spi3";
  1707. };
  1708.  
  1709. config {
  1710. pins = "gpio10";
  1711. drive-strength = <0x2>;
  1712. bias-disable = <0x0>;
  1713. };
  1714. };
  1715.  
  1716. cs0_sleep {
  1717. linux,phandle = <0xd1>;
  1718. phandle = <0xd1>;
  1719.  
  1720. mux {
  1721. pins = "gpio10";
  1722. function = "gpio";
  1723. };
  1724.  
  1725. config {
  1726. pins = "gpio10";
  1727. drive-strength = <0x2>;
  1728. bias-disable = <0x0>;
  1729. };
  1730. };
  1731. };
  1732.  
  1733. goodix_spi_active {
  1734. linux,phandle = <0x1af>;
  1735. phandle = <0x1af>;
  1736.  
  1737. mux {
  1738. pins = "gpio135", "gpio136", "gpio137", "gpio138";
  1739. function = "blsp_spi6";
  1740. };
  1741.  
  1742. config {
  1743. pins = "gpio135", "gpio136", "gpio137", "gpio138";
  1744. drive-strength = <0x2>;
  1745. bias-disable = <0x0>;
  1746. };
  1747. };
  1748.  
  1749. goodix_reset_reset {
  1750. linux,phandle = <0x1b0>;
  1751. phandle = <0x1b0>;
  1752.  
  1753. mux {
  1754. pins = "gpio140";
  1755. function = "gpio";
  1756. };
  1757.  
  1758. config {
  1759. pins = "gpio140";
  1760. drive-strength = <0x2>;
  1761. bias-disable = <0x0>;
  1762. output-low;
  1763. };
  1764. };
  1765.  
  1766. goodix_reset_active {
  1767. linux,phandle = <0x1b1>;
  1768. phandle = <0x1b1>;
  1769.  
  1770. mux {
  1771. pins = "gpio140";
  1772. function = "gpio";
  1773. };
  1774.  
  1775. config {
  1776. pins = "gpio140";
  1777. drive-strength = <0x2>;
  1778. bias-disable = <0x0>;
  1779. output-high;
  1780. };
  1781. };
  1782.  
  1783. goodix_irq_active {
  1784. linux,phandle = <0x1b2>;
  1785. phandle = <0x1b2>;
  1786.  
  1787. mux {
  1788. pins = "gpio48";
  1789. function = "gpio";
  1790. };
  1791.  
  1792. config {
  1793. pins = "gpio48";
  1794. drive-strength = <0x2>;
  1795. bias-disable = <0x0>;
  1796. input-enable;
  1797. };
  1798. };
  1799.  
  1800. pmx_ts_active {
  1801.  
  1802. ts_int_active {
  1803. linux,phandle = <0xe2>;
  1804. phandle = <0xe2>;
  1805.  
  1806. mux {
  1807. pins = "gpio65";
  1808. function = "gpio";
  1809. };
  1810.  
  1811. config {
  1812. pins = "gpio65";
  1813. drive-strength = <0x8>;
  1814. bias-pull-up;
  1815. };
  1816. };
  1817.  
  1818. ts_reset_active {
  1819. linux,phandle = <0xe3>;
  1820. phandle = <0xe3>;
  1821.  
  1822. mux {
  1823. pins = "gpio64";
  1824. function = "gpio";
  1825. };
  1826.  
  1827. config {
  1828. pins = "gpio64";
  1829. drive-strength = <0x8>;
  1830. bias-pull-up;
  1831. };
  1832. };
  1833. };
  1834.  
  1835. pmx_ts_suspend {
  1836.  
  1837. ts_int_suspend {
  1838. linux,phandle = <0xe4>;
  1839. phandle = <0xe4>;
  1840.  
  1841. mux {
  1842. pins = "gpio65";
  1843. function = "gpio";
  1844. };
  1845.  
  1846. config {
  1847. pins = "gpio65";
  1848. drive-strength = <0x2>;
  1849. bias-pull-down;
  1850. };
  1851. };
  1852.  
  1853. ts_reset_suspend {
  1854. linux,phandle = <0xe5>;
  1855. phandle = <0xe5>;
  1856.  
  1857. mux {
  1858. pins = "gpio64";
  1859. function = "gpio";
  1860. };
  1861.  
  1862. config {
  1863. pins = "gpio64";
  1864. drive-strength = <0x2>;
  1865. bias-pull-down;
  1866. };
  1867. };
  1868. };
  1869.  
  1870. pmx_ts_release {
  1871.  
  1872. ts_release {
  1873. linux,phandle = <0xe6>;
  1874. phandle = <0xe6>;
  1875.  
  1876. mux {
  1877. pins = "gpio65", "gpio64";
  1878. function = "gpio";
  1879. };
  1880.  
  1881. config {
  1882. pins = "gpio65", "gpio64";
  1883. drive-strength = <0x2>;
  1884. bias-pull-down;
  1885. };
  1886. };
  1887. };
  1888.  
  1889. tlmm_gpio_key {
  1890.  
  1891. gpio_key_active {
  1892. linux,phandle = <0x1ad>;
  1893. phandle = <0x1ad>;
  1894.  
  1895. mux {
  1896. pins = "gpio85", "gpio86", "gpio87";
  1897. function = "gpio";
  1898. };
  1899.  
  1900. config {
  1901. pins = "gpio85", "gpio86", "gpio87";
  1902. drive-strength = <0x2>;
  1903. bias-pull-up;
  1904. };
  1905. };
  1906.  
  1907. gpio_key_suspend {
  1908. linux,phandle = <0x1ae>;
  1909. phandle = <0x1ae>;
  1910.  
  1911. mux {
  1912. pins = "gpio85", "gpio86", "gpio87";
  1913. function = "gpio";
  1914. };
  1915.  
  1916. config {
  1917. pins = "gpio85", "gpio86", "gpio87";
  1918. drive-strength = <0x2>;
  1919. bias-pull-up;
  1920. };
  1921. };
  1922. };
  1923.  
  1924. pmx_qdsd_clk {
  1925.  
  1926. clk_sdcard {
  1927. linux,phandle = <0x4a>;
  1928. phandle = <0x4a>;
  1929.  
  1930. config {
  1931. pins = "qdsd_clk";
  1932. bias-disable;
  1933. drive-strength = <0x10>;
  1934. };
  1935. };
  1936.  
  1937. clk_trace {
  1938. linux,phandle = <0x50>;
  1939. phandle = <0x50>;
  1940.  
  1941. config {
  1942. pins = "qdsd_clk";
  1943. bias-pull-down;
  1944. drive-strength = <0x2>;
  1945. };
  1946. };
  1947.  
  1948. clk_swdtrc {
  1949. linux,phandle = <0x5b>;
  1950. phandle = <0x5b>;
  1951.  
  1952. config {
  1953. pins = "qdsd_clk";
  1954. bias-pull-down;
  1955. drive-strength = <0x2>;
  1956. };
  1957. };
  1958.  
  1959. clk_spmi {
  1960. linux,phandle = <0x66>;
  1961. phandle = <0x66>;
  1962.  
  1963. config {
  1964. pins = "qdsd_clk";
  1965. bias-pull-down;
  1966. drive-strength = <0x2>;
  1967. };
  1968. };
  1969. };
  1970.  
  1971. pmx_qdsd_cmd {
  1972.  
  1973. cmd_sdcard {
  1974. linux,phandle = <0x4b>;
  1975. phandle = <0x4b>;
  1976.  
  1977. config {
  1978. pins = "qdsd_cmd";
  1979. bias-pull-down;
  1980. drive-strength = <0x8>;
  1981. };
  1982. };
  1983.  
  1984. cmd_trace {
  1985. linux,phandle = <0x51>;
  1986. phandle = <0x51>;
  1987.  
  1988. config {
  1989. pins = "qdsd_cmd";
  1990. bias-pull-down;
  1991. drive-strength = <0x2>;
  1992. };
  1993. };
  1994.  
  1995. cmd_uart {
  1996. linux,phandle = <0x56>;
  1997. phandle = <0x56>;
  1998.  
  1999. config {
  2000. pins = "qdsd_cmd";
  2001. bias-pull-up;
  2002. drive-strength = <0x2>;
  2003. };
  2004. };
  2005.  
  2006. cmd_swdtrc {
  2007. linux,phandle = <0x5c>;
  2008. phandle = <0x5c>;
  2009.  
  2010. config {
  2011. pins = "qdsd_cmd";
  2012. bias-pull-up;
  2013. drive-strength = <0x2>;
  2014. };
  2015. };
  2016.  
  2017. cmd_jtag {
  2018. linux,phandle = <0x61>;
  2019. phandle = <0x61>;
  2020.  
  2021. config {
  2022. pins = "qdsd_cmd";
  2023. bias-disable;
  2024. drive-strength = <0x8>;
  2025. };
  2026. };
  2027.  
  2028. cmd_spmi {
  2029. linux,phandle = <0x67>;
  2030. phandle = <0x67>;
  2031.  
  2032. config {
  2033. pins = "qdsd_cmd";
  2034. bias-pull-down;
  2035. drive-strength = <0xa>;
  2036. };
  2037. };
  2038. };
  2039.  
  2040. pmx_qdsd_data0 {
  2041.  
  2042. data0_sdcard {
  2043. linux,phandle = <0x4c>;
  2044. phandle = <0x4c>;
  2045.  
  2046. config {
  2047. pins = "qdsd_data0";
  2048. bias-pull-down;
  2049. drive-strength = <0x8>;
  2050. };
  2051. };
  2052.  
  2053. data0_trace {
  2054. linux,phandle = <0x52>;
  2055. phandle = <0x52>;
  2056.  
  2057. config {
  2058. pins = "qdsd_data0";
  2059. bias-pull-down;
  2060. drive-strength = <0x8>;
  2061. };
  2062. };
  2063.  
  2064. data0_uart {
  2065. linux,phandle = <0x57>;
  2066. phandle = <0x57>;
  2067.  
  2068. config {
  2069. pins = "qdsd_data0";
  2070. bias-pull-down;
  2071. drive-strength = <0x2>;
  2072. };
  2073. };
  2074.  
  2075. data0_swdtrc {
  2076. linux,phandle = <0x5d>;
  2077. phandle = <0x5d>;
  2078.  
  2079. config {
  2080. pins = "qdsd_data0";
  2081. bias-pull-down;
  2082. drive-strength = <0x2>;
  2083. };
  2084. };
  2085.  
  2086. data0_jtag {
  2087. linux,phandle = <0x62>;
  2088. phandle = <0x62>;
  2089.  
  2090. config {
  2091. pins = "qdsd_data0";
  2092. bias-pull-up;
  2093. drive-strength = <0x2>;
  2094. };
  2095. };
  2096.  
  2097. data0_spmi {
  2098. linux,phandle = <0x68>;
  2099. phandle = <0x68>;
  2100.  
  2101. config {
  2102. pins = "qdsd_data0";
  2103. bias-pull-down;
  2104. drive-strength = <0x2>;
  2105. };
  2106. };
  2107. };
  2108.  
  2109. pmx_qdsd_data1 {
  2110.  
  2111. data1_sdcard {
  2112. linux,phandle = <0x4d>;
  2113. phandle = <0x4d>;
  2114.  
  2115. config {
  2116. pins = "qdsd_data1";
  2117. bias-pull-down;
  2118. drive-strength = <0x8>;
  2119. };
  2120. };
  2121.  
  2122. data1_trace {
  2123. linux,phandle = <0x53>;
  2124. phandle = <0x53>;
  2125.  
  2126. config {
  2127. pins = "qdsd_data1";
  2128. bias-pull-down;
  2129. drive-strength = <0x8>;
  2130. };
  2131. };
  2132.  
  2133. data1_uart {
  2134. linux,phandle = <0x58>;
  2135. phandle = <0x58>;
  2136.  
  2137. config {
  2138. pins = "qdsd_data1";
  2139. bias-pull-down;
  2140. drive-strength = <0x2>;
  2141. };
  2142. };
  2143.  
  2144. data1_swdtrc {
  2145. linux,phandle = <0x5e>;
  2146. phandle = <0x5e>;
  2147.  
  2148. config {
  2149. pins = "qdsd_data1";
  2150. bias-pull-down;
  2151. drive-strength = <0x2>;
  2152. };
  2153. };
  2154.  
  2155. data1_jtag {
  2156. linux,phandle = <0x63>;
  2157. phandle = <0x63>;
  2158.  
  2159. config {
  2160. pins = "qdsd_data1";
  2161. bias-pull-down;
  2162. drive-strength = <0x2>;
  2163. };
  2164. };
  2165. };
  2166.  
  2167. pmx_qdsd_data2 {
  2168.  
  2169. data2_sdcard {
  2170. linux,phandle = <0x4e>;
  2171. phandle = <0x4e>;
  2172.  
  2173. config {
  2174. pins = "qdsd_data2";
  2175. bias-pull-down;
  2176. drive-strength = <0x8>;
  2177. };
  2178. };
  2179.  
  2180. data2_trace {
  2181. linux,phandle = <0x54>;
  2182. phandle = <0x54>;
  2183.  
  2184. config {
  2185. pins = "qdsd_data2";
  2186. bias-pull-down;
  2187. drive-strength = <0x8>;
  2188. };
  2189. };
  2190.  
  2191. data2_uart {
  2192. linux,phandle = <0x59>;
  2193. phandle = <0x59>;
  2194.  
  2195. config {
  2196. pins = "qdsd_data2";
  2197. bias-pull-down;
  2198. drive-strength = <0x2>;
  2199. };
  2200. };
  2201.  
  2202. data2_swdtrc {
  2203. linux,phandle = <0x5f>;
  2204. phandle = <0x5f>;
  2205.  
  2206. config {
  2207. pins = "qdsd_data2";
  2208. bias-pull-down;
  2209. drive-strength = <0x2>;
  2210. };
  2211. };
  2212.  
  2213. data2_jtag {
  2214. linux,phandle = <0x64>;
  2215. phandle = <0x64>;
  2216.  
  2217. config {
  2218. pins = "qdsd_data2";
  2219. bias-pull-up;
  2220. drive-strength = <0x8>;
  2221. };
  2222. };
  2223. };
  2224.  
  2225. pmx_qdsd_data3 {
  2226.  
  2227. data3_sdcard {
  2228. linux,phandle = <0x4f>;
  2229. phandle = <0x4f>;
  2230.  
  2231. config {
  2232. pins = "qdsd_data3";
  2233. bias-pull-down;
  2234. drive-strength = <0x8>;
  2235. };
  2236. };
  2237.  
  2238. data3_trace {
  2239. linux,phandle = <0x55>;
  2240. phandle = <0x55>;
  2241.  
  2242. config {
  2243. pins = "qdsd_data3";
  2244. bias-pull-down;
  2245. drive-strength = <0x8>;
  2246. };
  2247. };
  2248.  
  2249. data3_uart {
  2250. linux,phandle = <0x5a>;
  2251. phandle = <0x5a>;
  2252.  
  2253. config {
  2254. pins = "qdsd_data3";
  2255. bias-pull-up;
  2256. drive-strength = <0x2>;
  2257. };
  2258. };
  2259.  
  2260. data3_swdtrc {
  2261. linux,phandle = <0x60>;
  2262. phandle = <0x60>;
  2263.  
  2264. config {
  2265. pins = "qdsd_data3";
  2266. bias-pull-up;
  2267. drive-strength = <0x2>;
  2268. };
  2269. };
  2270.  
  2271. data3_jtag {
  2272. linux,phandle = <0x65>;
  2273. phandle = <0x65>;
  2274.  
  2275. config {
  2276. pins = "qdsd_data3";
  2277. bias-pull-up;
  2278. drive-strength = <0x2>;
  2279. };
  2280. };
  2281.  
  2282. data3_spmi {
  2283. linux,phandle = <0x69>;
  2284. phandle = <0x69>;
  2285.  
  2286. config {
  2287. pins = "qdsd_data3";
  2288. bias-pull-down;
  2289. drive-strength = <0x8>;
  2290. };
  2291. };
  2292. };
  2293.  
  2294. typec_ssmux_config {
  2295. linux,phandle = <0x119>;
  2296. phandle = <0x119>;
  2297.  
  2298. mux {
  2299. pins = "gpio139";
  2300. function = "gpio";
  2301. };
  2302.  
  2303. config {
  2304. pins = "gpio139";
  2305. drive-strength = <0x2>;
  2306. bias-disable;
  2307. };
  2308. };
  2309. };
  2310.  
  2311. clock-controller@b111000 {
  2312. compatible = "qcom,8953-l2ccc";
  2313. reg = <0xb111000 0x1000>;
  2314. linux,phandle = <0xe>;
  2315. phandle = <0xe>;
  2316. };
  2317.  
  2318. clock-controller@b011000 {
  2319. compatible = "qcom,8953-l2ccc";
  2320. reg = <0xb011000 0x1000>;
  2321. linux,phandle = <0x1c>;
  2322. phandle = <0x1c>;
  2323. };
  2324.  
  2325. clock-controller@b188000 {
  2326. compatible = "qcom,arm-cortex-acc";
  2327. reg = <0xb188000 0x1000>;
  2328. linux,phandle = <0xa>;
  2329. phandle = <0xa>;
  2330. };
  2331.  
  2332. clock-controller@b198000 {
  2333. compatible = "qcom,arm-cortex-acc";
  2334. reg = <0xb198000 0x1000>;
  2335. linux,phandle = <0xf>;
  2336. phandle = <0xf>;
  2337. };
  2338.  
  2339. clock-controller@b1a8000 {
  2340. compatible = "qcom,arm-cortex-acc";
  2341. reg = <0xb1a8000 0x1000>;
  2342. linux,phandle = <0x12>;
  2343. phandle = <0x12>;
  2344. };
  2345.  
  2346. clock-controller@b1b8000 {
  2347. compatible = "qcom,arm-cortex-acc";
  2348. reg = <0xb1b8000 0x1000>;
  2349. linux,phandle = <0x15>;
  2350. phandle = <0x15>;
  2351. };
  2352.  
  2353. clock-controller@b088000 {
  2354. compatible = "qcom,arm-cortex-acc";
  2355. reg = <0xb088000 0x1000>;
  2356. linux,phandle = <0x18>;
  2357. phandle = <0x18>;
  2358. };
  2359.  
  2360. clock-controller@b098000 {
  2361. compatible = "qcom,arm-cortex-acc";
  2362. reg = <0xb098000 0x1000>;
  2363. linux,phandle = <0x1d>;
  2364. phandle = <0x1d>;
  2365. };
  2366.  
  2367. clock-controller@b0a8000 {
  2368. compatible = "qcom,arm-cortex-acc";
  2369. reg = <0xb0a8000 0x1000>;
  2370. linux,phandle = <0x20>;
  2371. phandle = <0x20>;
  2372. };
  2373.  
  2374. clock-controller@b0b8000 {
  2375. compatible = "qcom,arm-cortex-acc";
  2376. reg = <0xb0b8000 0x1000>;
  2377. linux,phandle = <0x23>;
  2378. phandle = <0x23>;
  2379. };
  2380.  
  2381. cpuss_dump {
  2382. compatible = "qcom,cpuss-dump";
  2383.  
  2384. qcom,l2_dump0 {
  2385. qcom,dump-node = <0xd>;
  2386. qcom,dump-id = <0xc0>;
  2387. };
  2388.  
  2389. qcom,l2_dump1 {
  2390. qcom,dump-node = <0x1b>;
  2391. qcom,dump-id = <0xc1>;
  2392. };
  2393.  
  2394. qcom,l1_i_cache0 {
  2395. qcom,dump-node = <0x26>;
  2396. qcom,dump-id = <0x60>;
  2397. };
  2398.  
  2399. qcom,l1_i_cache1 {
  2400. qcom,dump-node = <0x27>;
  2401. qcom,dump-id = <0x61>;
  2402. };
  2403.  
  2404. qcom,l1_i_cache2 {
  2405. qcom,dump-node = <0x28>;
  2406. qcom,dump-id = <0x62>;
  2407. };
  2408.  
  2409. qcom,l1_i_cache3 {
  2410. qcom,dump-node = <0x29>;
  2411. qcom,dump-id = <0x63>;
  2412. };
  2413.  
  2414. qcom,l1_i_cache100 {
  2415. qcom,dump-node = <0x2a>;
  2416. qcom,dump-id = <0x64>;
  2417. };
  2418.  
  2419. qcom,l1_i_cache101 {
  2420. qcom,dump-node = <0x2b>;
  2421. qcom,dump-id = <0x65>;
  2422. };
  2423.  
  2424. qcom,l1_i_cache102 {
  2425. qcom,dump-node = <0x2c>;
  2426. qcom,dump-id = <0x66>;
  2427. };
  2428.  
  2429. qcom,l1_i_cache103 {
  2430. qcom,dump-node = <0x2d>;
  2431. qcom,dump-id = <0x67>;
  2432. };
  2433.  
  2434. qcom,l1_d_cache0 {
  2435. qcom,dump-node = <0x2e>;
  2436. qcom,dump-id = <0x80>;
  2437. };
  2438.  
  2439. qcom,l1_d_cache1 {
  2440. qcom,dump-node = <0x2f>;
  2441. qcom,dump-id = <0x81>;
  2442. };
  2443.  
  2444. qcom,l1_d_cache2 {
  2445. qcom,dump-node = <0x30>;
  2446. qcom,dump-id = <0x82>;
  2447. };
  2448.  
  2449. qcom,l1_d_cache3 {
  2450. qcom,dump-node = <0x31>;
  2451. qcom,dump-id = <0x83>;
  2452. };
  2453.  
  2454. qcom,l1_d_cache100 {
  2455. qcom,dump-node = <0x32>;
  2456. qcom,dump-id = <0x84>;
  2457. };
  2458.  
  2459. qcom,l1_d_cache101 {
  2460. qcom,dump-node = <0x33>;
  2461. qcom,dump-id = <0x85>;
  2462. };
  2463.  
  2464. qcom,l1_d_cache102 {
  2465. qcom,dump-node = <0x34>;
  2466. qcom,dump-id = <0x86>;
  2467. };
  2468.  
  2469. qcom,l1_d_cache103 {
  2470. qcom,dump-node = <0x35>;
  2471. qcom,dump-id = <0x87>;
  2472. };
  2473. };
  2474.  
  2475. qcom,kgsl-hyp {
  2476. compatible = "qcom,pil-tz-generic";
  2477. qcom,pas-id = <0xd>;
  2478. qcom,firmware-name = "a506_zap";
  2479. memory-region = <0x36>;
  2480. clocks = <0x37 0xd390d2 0x37 0x94de4919 0x37 0xd4415c9b 0x37 0x37a21414>;
  2481. clock-names = "scm_core_clk", "scm_iface_clk", "scm_bus_clk", "scm_core_clk_src";
  2482. qcom,proxy-clock-names = "scm_core_clk", "scm_iface_clk", "scm_bus_clk", "scm_core_clk_src";
  2483. qcom,scm_core_clk_src-freq = <0x4c4b400>;
  2484. };
  2485.  
  2486. qcom,kgsl-busmon {
  2487. label = "kgsl-busmon";
  2488. compatible = "qcom,kgsl-busmon";
  2489. };
  2490.  
  2491. qcom,gpubw {
  2492. compatible = "qcom,devbw";
  2493. governor = "bw_vbif";
  2494. qcom,src-dst-ports = <0x1a 0x200>;
  2495. qcom,active-only;
  2496. qcom,bw-tbl = <0x0 0x64b 0x84c 0xb71 0xc96 0x1098 0x1406 0x16e3 0x1808 0x192d 0x1bc0>;
  2497. linux,phandle = <0x39>;
  2498. phandle = <0x39>;
  2499. };
  2500.  
  2501. qcom,kgsl-3d0@1c00000 {
  2502. label = "kgsl-3d0";
  2503. compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";
  2504. status = "ok";
  2505. reg = <0x1c00000 0x40000>;
  2506. reg-names = "kgsl_3d0_reg_memory";
  2507. interrupts = <0x0 0x21 0x0>;
  2508. interrupt-names = "kgsl_3d0_irq";
  2509. qcom,id = <0x0>;
  2510. qcom,chipid = <0x5000600>;
  2511. qcom,initial-pwrlevel = <0x4>;
  2512. qcom,idle-timeout = <0x50>;
  2513. qcom,deep-nap-timeout = <0x64>;
  2514. qcom,strtstp-sleepwake;
  2515. qcom,highest-bank-bit = <0xe>;
  2516. clocks = <0x38 0x49a51fd9 0x38 0xd15c8a00 0x38 0x3edd69ad 0x38 0x19922503 0x38 0x1180db06 0x38 0xae18e54d>;
  2517. clock-names = "core_clk", "iface_clk", "mem_iface_clk", "alt_mem_iface_clk", "rbbmtimer_clk", "alwayson_clk";
  2518. qcom,gpubw-dev = <0x39>;
  2519. qcom,bus-control;
  2520. qcom,bus-width = <0x10>;
  2521. qcom,msm-bus,name = "grp3d";
  2522. qcom,msm-bus,num-cases = <0xb>;
  2523. qcom,msm-bus,num-paths = <0x1>;
  2524. qcom,msm-bus,vectors-KBps = <0x1a 0x200 0x0 0x0 0x1a 0x200 0x0 0x19c800 0x1a 0x200 0x0 0x21fc00 0x1a 0x200 0x0 0x2ee000 0x1a 0x200 0x0 0x339000 0x1a 0x200 0x0 0x43f800 0x1a 0x200 0x0 0x520800 0x1a 0x200 0x0 0x5dc000 0x1a 0x200 0x0 0x627000 0x1a 0x200 0x0 0x672000 0x1a 0x200 0x0 0x71ac00>;
  2525. regulator-names = "vddcx", "vdd";
  2526. vddcx-supply = <0x3a>;
  2527. vdd-supply = <0x3b>;
  2528. qcom,pm-qos-active-latency = <0xd5>;
  2529. qcom,pm-qos-wakeup-latency = <0xd5>;
  2530. qcom,gpu-quirk-two-pass-use-wfi;
  2531. coresight-id = <0x43>;
  2532. coresight-name = "coresight-gfx";
  2533. coresight-nr-inports = <0x0>;
  2534. coresight-outports = <0x0>;
  2535. coresight-child-list = <0x3c>;
  2536. coresight-child-ports = <0x6>;
  2537. qcom,enable-ca-jump;
  2538. qcom,ca-busy-penalty = <0x2ee0>;
  2539. qcom,ca-target-pwrlevel = <0x3>;
  2540.  
  2541. qcom,gpu-pwrlevels {
  2542. #address-cells = <0x1>;
  2543. #size-cells = <0x0>;
  2544. compatible = "qcom,gpu-pwrlevels";
  2545.  
  2546. qcom,gpu-pwrlevel@0 {
  2547. reg = <0x0>;
  2548. qcom,gpu-freq = <0x26be3680>;
  2549. qcom,bus-freq = <0xa>;
  2550. qcom,bus-min = <0xa>;
  2551. qcom,bus-max = <0xa>;
  2552. };
  2553.  
  2554. qcom,gpu-pwrlevel@1 {
  2555. reg = <0x1>;
  2556. qcom,gpu-freq = <0x2160ec00>;
  2557. qcom,bus-freq = <0xa>;
  2558. qcom,bus-min = <0x8>;
  2559. qcom,bus-max = <0xa>;
  2560. };
  2561.  
  2562. qcom,gpu-pwrlevel@2 {
  2563. reg = <0x2>;
  2564. qcom,gpu-freq = <0x1e65fb80>;
  2565. qcom,bus-freq = <0x9>;
  2566. qcom,bus-min = <0x6>;
  2567. qcom,bus-max = <0xa>;
  2568. };
  2569.  
  2570. qcom,gpu-pwrlevel@3 {
  2571. reg = <0x3>;
  2572. qcom,gpu-freq = <0x17d78400>;
  2573. qcom,bus-freq = <0x7>;
  2574. qcom,bus-min = <0x4>;
  2575. qcom,bus-max = <0x8>;
  2576. };
  2577.  
  2578. qcom,gpu-pwrlevel@4 {
  2579. reg = <0x4>;
  2580. qcom,gpu-freq = <0x1312d000>;
  2581. qcom,bus-freq = <0x4>;
  2582. qcom,bus-min = <0x2>;
  2583. qcom,bus-max = <0x6>;
  2584. };
  2585.  
  2586. qcom,gpu-pwrlevel@5 {
  2587. reg = <0x5>;
  2588. qcom,gpu-freq = <0xcdfe600>;
  2589. qcom,bus-freq = <0x1>;
  2590. qcom,bus-min = <0x1>;
  2591. qcom,bus-max = <0x4>;
  2592. };
  2593.  
  2594. qcom,gpu-pwrlevel@6 {
  2595. reg = <0x6>;
  2596. qcom,gpu-freq = <0x124f800>;
  2597. qcom,bus-freq = <0x0>;
  2598. qcom,bus-min = <0x0>;
  2599. qcom,bus-max = <0x0>;
  2600. };
  2601. };
  2602. };
  2603.  
  2604. qcom,kgsl-iommu@1c40000 {
  2605. compatible = "qcom,kgsl-smmu-v2";
  2606. reg = <0x1c40000 0x10000>;
  2607. qcom,protect = <0x40000 0x10000>;
  2608. qcom,micro-mmu-control = <0x6000>;
  2609. clocks = <0x38 0xd15c8a00 0x38 0x3edd69ad>;
  2610. clock-names = "gpu_ahb_clk", "gcc_bimc_gfx_clk";
  2611. qcom,secure_align_mask = <0xfff>;
  2612. qcom,retention;
  2613.  
  2614. gfx3d_user {
  2615. compatible = "qcom,smmu-kgsl-cb";
  2616. label = "gfx3d_user";
  2617. iommus = <0x3d 0x0>;
  2618. qcom,gpu-offset = <0x48000>;
  2619. };
  2620.  
  2621. gfx3d_secure {
  2622. compatible = "qcom,smmu-kgsl-cb";
  2623. iommus = <0x3d 0x2>;
  2624. memory-region = <0x3e>;
  2625. };
  2626. };
  2627.  
  2628. qcom,ion {
  2629. compatible = "qcom,msm-ion";
  2630. #address-cells = <0x1>;
  2631. #size-cells = <0x0>;
  2632.  
  2633. qcom,ion-heap@25 {
  2634. reg = <0x19>;
  2635. qcom,ion-heap-type = "SYSTEM";
  2636. };
  2637.  
  2638. qcom,ion-heap@8 {
  2639. reg = <0x8>;
  2640. memory-region = <0x3e>;
  2641. qcom,ion-heap-type = "SECURE_DMA";
  2642. };
  2643.  
  2644. qcom,ion-heap@27 {
  2645. reg = <0x1b>;
  2646. memory-region = <0x3f>;
  2647. qcom,ion-heap-type = "DMA";
  2648. };
  2649. };
  2650.  
  2651. qcom,smp2p-modem@0x0b011008 {
  2652. compatible = "qcom,smp2p";
  2653. reg = <0xb011008 0x4>;
  2654. qcom,remote-pid = <0x1>;
  2655. qcom,irq-bitmask = <0x4000>;
  2656. interrupts = <0x0 0x1b 0x1>;
  2657. };
  2658.  
  2659. qcom,smp2p-wcnss@0x0b011008 {
  2660. compatible = "qcom,smp2p";
  2661. reg = <0xb011008 0x4>;
  2662. qcom,remote-pid = <0x4>;
  2663. qcom,irq-bitmask = <0x40000>;
  2664. interrupts = <0x0 0x8f 0x1>;
  2665. };
  2666.  
  2667. qcom,smp2p-adsp@0x0b011008 {
  2668. compatible = "qcom,smp2p";
  2669. reg = <0xb011008 0x4>;
  2670. qcom,remote-pid = <0x2>;
  2671. qcom,irq-bitmask = <0x400>;
  2672. interrupts = <0x0 0x123 0x1>;
  2673. };
  2674.  
  2675. qcom,smp2pgpio-smp2p-15-in {
  2676. compatible = "qcom,smp2pgpio";
  2677. qcom,entry-name = "smp2p";
  2678. qcom,remote-pid = <0xf>;
  2679. qcom,is-inbound;
  2680. gpio-controller;
  2681. #gpio-cells = <0x2>;
  2682. interrupt-controller;
  2683. #interrupt-cells = <0x2>;
  2684. linux,phandle = <0x40>;
  2685. phandle = <0x40>;
  2686. };
  2687.  
  2688. qcom,smp2pgpio_test_smp2p_15_in {
  2689. compatible = "qcom,smp2pgpio_test_smp2p_15_in";
  2690. gpios = <0x40 0x0 0x0>;
  2691. };
  2692.  
  2693. qcom,smp2pgpio-smp2p-15-out {
  2694. compatible = "qcom,smp2pgpio";
  2695. qcom,entry-name = "smp2p";
  2696. qcom,remote-pid = <0xf>;
  2697. gpio-controller;
  2698. #gpio-cells = <0x2>;
  2699. interrupt-controller;
  2700. #interrupt-cells = <0x2>;
  2701. linux,phandle = <0x41>;
  2702. phandle = <0x41>;
  2703. };
  2704.  
  2705. qcom,smp2pgpio_test_smp2p_15_out {
  2706. compatible = "qcom,smp2pgpio_test_smp2p_15_out";
  2707. gpios = <0x41 0x0 0x0>;
  2708. };
  2709.  
  2710. qcom,smp2pgpio-smp2p-1-in {
  2711. compatible = "qcom,smp2pgpio";
  2712. qcom,entry-name = "smp2p";
  2713. qcom,remote-pid = <0x1>;
  2714. qcom,is-inbound;
  2715. gpio-controller;
  2716. #gpio-cells = <0x2>;
  2717. interrupt-controller;
  2718. #interrupt-cells = <0x2>;
  2719. linux,phandle = <0x42>;
  2720. phandle = <0x42>;
  2721. };
  2722.  
  2723. qcom,smp2pgpio_test_smp2p_1_in {
  2724. compatible = "qcom,smp2pgpio_test_smp2p_1_in";
  2725. gpios = <0x42 0x0 0x0>;
  2726. };
  2727.  
  2728. qcom,smp2pgpio-smp2p-1-out {
  2729. compatible = "qcom,smp2pgpio";
  2730. qcom,entry-name = "smp2p";
  2731. qcom,remote-pid = <0x1>;
  2732. gpio-controller;
  2733. #gpio-cells = <0x2>;
  2734. interrupt-controller;
  2735. #interrupt-cells = <0x2>;
  2736. linux,phandle = <0x43>;
  2737. phandle = <0x43>;
  2738. };
  2739.  
  2740. qcom,smp2pgpio_test_smp2p_1_out {
  2741. compatible = "qcom,smp2pgpio_test_smp2p_1_out";
  2742. gpios = <0x43 0x0 0x0>;
  2743. };
  2744.  
  2745. qcom,smp2pgpio-smp2p-4-in {
  2746. compatible = "qcom,smp2pgpio";
  2747. qcom,entry-name = "smp2p";
  2748. qcom,remote-pid = <0x4>;
  2749. qcom,is-inbound;
  2750. gpio-controller;
  2751. #gpio-cells = <0x2>;
  2752. interrupt-controller;
  2753. #interrupt-cells = <0x2>;
  2754. linux,phandle = <0x44>;
  2755. phandle = <0x44>;
  2756. };
  2757.  
  2758. qcom,smp2pgpio_test_smp2p_4_in {
  2759. compatible = "qcom,smp2pgpio_test_smp2p_4_in";
  2760. gpios = <0x44 0x0 0x0>;
  2761. };
  2762.  
  2763. qcom,smp2pgpio-smp2p-4-out {
  2764. compatible = "qcom,smp2pgpio";
  2765. qcom,entry-name = "smp2p";
  2766. qcom,remote-pid = <0x4>;
  2767. gpio-controller;
  2768. #gpio-cells = <0x2>;
  2769. interrupt-controller;
  2770. #interrupt-cells = <0x2>;
  2771. linux,phandle = <0x45>;
  2772. phandle = <0x45>;
  2773. };
  2774.  
  2775. qcom,smp2pgpio_test_smp2p_4_out {
  2776. compatible = "qcom,smp2pgpio_test_smp2p_4_out";
  2777. gpios = <0x45 0x0 0x0>;
  2778. };
  2779.  
  2780. qcom,smp2pgpio-smp2p-2-in {
  2781. compatible = "qcom,smp2pgpio";
  2782. qcom,entry-name = "smp2p";
  2783. qcom,remote-pid = <0x2>;
  2784. qcom,is-inbound;
  2785. gpio-controller;
  2786. #gpio-cells = <0x2>;
  2787. interrupt-controller;
  2788. #interrupt-cells = <0x2>;
  2789. linux,phandle = <0x46>;
  2790. phandle = <0x46>;
  2791. };
  2792.  
  2793. qcom,smp2pgpio_test_smp2p_2_in {
  2794. compatible = "qcom,smp2pgpio_test_smp2p_2_in";
  2795. gpios = <0x46 0x0 0x0>;
  2796. };
  2797.  
  2798. qcom,smp2pgpio-smp2p-2-out {
  2799. compatible = "qcom,smp2pgpio";
  2800. qcom,entry-name = "smp2p";
  2801. qcom,remote-pid = <0x2>;
  2802. gpio-controller;
  2803. #gpio-cells = <0x2>;
  2804. interrupt-controller;
  2805. #interrupt-cells = <0x2>;
  2806. linux,phandle = <0x47>;
  2807. phandle = <0x47>;
  2808. };
  2809.  
  2810. qcom,smp2pgpio_test_smp2p_2_out {
  2811. compatible = "qcom,smp2pgpio_test_smp2p_2_out";
  2812. gpios = <0x47 0x0 0x0>;
  2813. };
  2814.  
  2815. qcom,smp2pgpio-ssr-smp2p-1-in {
  2816. compatible = "qcom,smp2pgpio";
  2817. qcom,entry-name = "slave-kernel";
  2818. qcom,remote-pid = <0x1>;
  2819. qcom,is-inbound;
  2820. gpio-controller;
  2821. #gpio-cells = <0x2>;
  2822. interrupt-controller;
  2823. #interrupt-cells = <0x2>;
  2824. linux,phandle = <0x11f>;
  2825. phandle = <0x11f>;
  2826. };
  2827.  
  2828. qcom,smp2pgpio-ssr-smp2p-1-out {
  2829. compatible = "qcom,smp2pgpio";
  2830. qcom,entry-name = "master-kernel";
  2831. qcom,remote-pid = <0x1>;
  2832. gpio-controller;
  2833. #gpio-cells = <0x2>;
  2834. interrupt-controller;
  2835. #interrupt-cells = <0x2>;
  2836. linux,phandle = <0x120>;
  2837. phandle = <0x120>;
  2838. };
  2839.  
  2840. qcom,smp2pgpio-ssr-smp2p-2-in {
  2841. compatible = "qcom,smp2pgpio";
  2842. qcom,entry-name = "slave-kernel";
  2843. qcom,remote-pid = <0x2>;
  2844. qcom,is-inbound;
  2845. gpio-controller;
  2846. #gpio-cells = <0x2>;
  2847. interrupt-controller;
  2848. #interrupt-cells = <0x2>;
  2849. linux,phandle = <0x122>;
  2850. phandle = <0x122>;
  2851. };
  2852.  
  2853. qcom,smp2pgpio-ssr-smp2p-2-out {
  2854. compatible = "qcom,smp2pgpio";
  2855. qcom,entry-name = "master-kernel";
  2856. qcom,remote-pid = <0x2>;
  2857. gpio-controller;
  2858. #gpio-cells = <0x2>;
  2859. interrupt-controller;
  2860. #interrupt-cells = <0x2>;
  2861. linux,phandle = <0x123>;
  2862. phandle = <0x123>;
  2863. };
  2864.  
  2865. qcom,smp2pgpio-ssr-smp2p-4-in {
  2866. compatible = "qcom,smp2pgpio";
  2867. qcom,entry-name = "slave-kernel";
  2868. qcom,remote-pid = <0x4>;
  2869. qcom,is-inbound;
  2870. gpio-controller;
  2871. #gpio-cells = <0x2>;
  2872. interrupt-controller;
  2873. #interrupt-cells = <0x2>;
  2874. linux,phandle = <0x126>;
  2875. phandle = <0x126>;
  2876. };
  2877.  
  2878. qcom,smp2pgpio-ssr-smp2p-4-out {
  2879. compatible = "qcom,smp2pgpio";
  2880. qcom,entry-name = "master-kernel";
  2881. qcom,remote-pid = <0x4>;
  2882. gpio-controller;
  2883. #gpio-cells = <0x2>;
  2884. interrupt-controller;
  2885. #interrupt-cells = <0x2>;
  2886. linux,phandle = <0x127>;
  2887. phandle = <0x127>;
  2888. };
  2889.  
  2890. arm,smmu-kgsl@1c40000 {
  2891. status = "ok";
  2892. compatible = "qcom,smmu-v2";
  2893. qcom,tz-device-id = "GPU";
  2894. reg = <0x1c40000 0x10000>;
  2895. #iommu-cells = <0x1>;
  2896. #global-interrupts = <0x1>;
  2897. interrupts = <0x0 0xc7 0x0 0x0 0xe1 0x0 0x0 0xe8 0x0 0x0 0xe9 0x0 0x0 0xea 0x0>;
  2898. qcom,register-save;
  2899. qcom,skip-init;
  2900. qcom,dynamic;
  2901. qcom,enable-smmu-halt;
  2902. qcom,enable-static-cb;
  2903. qcom,no-smr-check;
  2904. vdd-supply = <0x3a>;
  2905. clocks = <0x38 0xd15c8a00 0x38 0x3edd69ad>;
  2906. clock-names = "gpu_ahb_clk", "gcc_bimc_gfx_clk";
  2907. #clock-cells = <0x1>;
  2908. attach-impl-defs = <0x6000 0x270 0x6060 0x1055 0x6800 0x6 0x6900 0x3ff 0x6924 0x204 0x6928 0x10800 0x6930 0x400 0x6960 0xffffffff 0x6b64 0xa0000 0x6b68 0xaaab92a>;
  2909. linux,phandle = <0x3d>;
  2910. phandle = <0x3d>;
  2911. };
  2912.  
  2913. qcom,iommu@1e00000 {
  2914. compatible = "qcom,msm-smmu-v2", "qcom,msm-mmu-500";
  2915. #address-cells = <0x1>;
  2916. #size-cells = <0x1>;
  2917. ranges;
  2918. reg = <0x1e00000 0x40000>;
  2919. reg-names = "iommu_base";
  2920. interrupts = <0x0 0x29 0x0 0x0 0x26 0x0>;
  2921. interrupt-names = "global_cfg_NS_irq", "global_cfg_S_irq";
  2922. label = "apps_iommu";
  2923. qcom,iommu-secure-id = <0x11>;
  2924. clocks = <0x37 0x75eaefa5 0x37 0x8fbc51da>;
  2925. clock-names = "iface_clk", "core_clk";
  2926. qcom,cb-base-offset = <0x20000>;
  2927. status = "ok";
  2928. linux,phandle = <0x17c>;
  2929. phandle = <0x17c>;
  2930.  
  2931. qcom,iommu-ctx@1e20000 {
  2932. compatible = "qcom,msm-smmu-v2-ctx";
  2933. reg = <0x1e20000 0x1000>;
  2934. qcom,secure-context;
  2935. interrupts = <0x0 0xfd 0x0 0x0 0xfd 0x0>;
  2936. qcom,iommu-ctx-sids = <0x2400>;
  2937. qcom,iommu-sid-mask = <0x3f0>;
  2938. label = "adsp_elf";
  2939. };
  2940.  
  2941. qcom,iommu-ctx@1e21000 {
  2942. compatible = "qcom,msm-smmu-v2-ctx";
  2943. reg = <0x1e21000 0x1000>;
  2944. qcom,secure-context;
  2945. interrupts = <0x0 0xfe 0x0 0x0 0xfe 0x0>;
  2946. qcom,iommu-ctx-sids = <0x2402>;
  2947. qcom,iommu-sid-mask = <0x3f1>;
  2948. label = "adsp_sec_pixel";
  2949. };
  2950.  
  2951. qcom,iommu-ctx@1e22000 {
  2952. compatible = "qcom,msm-smmu-v2-ctx";
  2953. reg = <0x1e22000 0x1000>;
  2954. qcom,secure-context;
  2955. interrupts = <0x0 0xff 0x0 0x0 0xff 0x0>;
  2956. qcom,iommu-ctx-sids = <0xc01>;
  2957. label = "mdp_1";
  2958. };
  2959.  
  2960. qcom,iommu-ctx@1e23000 {
  2961. compatible = "qcom,msm-smmu-v2-ctx";
  2962. reg = <0x1e23000 0x1000>;
  2963. qcom,secure-context;
  2964. interrupts = <0x0 0x35 0x0 0x0 0x35 0x0>;
  2965. qcom,iommu-ctx-sids = <0x980 0x986 0x903>;
  2966. qcom,iommu-sid-mask = <0x200 0x200 0x220>;
  2967. label = "venus_fw";
  2968. qcom,report-error-on-fault;
  2969. };
  2970.  
  2971. qcom,iommu-ctx@1e24000 {
  2972. compatible = "qcom,msm-smmu-v2-ctx";
  2973. reg = <0x1e24000 0x1000>;
  2974. qcom,secure-context;
  2975. interrupts = <0x0 0x36 0x0 0x0 0x36 0x0>;
  2976. qcom,iommu-ctx-sids = <0x908 0x905 0x925 0x928>;
  2977. qcom,iommu-sid-mask = <0x200 0x20a 0x208 0x200>;
  2978. label = "venus_sec_non_pixel";
  2979. qcom,report-error-on-fault;
  2980. linux,phandle = <0xb7>;
  2981. phandle = <0xb7>;
  2982. };
  2983.  
  2984. qcom,iommu-ctx@1e25000 {
  2985. compatible = "qcom,msm-smmu-v2-ctx";
  2986. reg = <0x1e25000 0x1000>;
  2987. qcom,secure-context;
  2988. interrupts = <0x0 0x3a 0x0 0x0 0x3a 0x0>;
  2989. qcom,iommu-ctx-sids = <0x900 0x902 0x909 0x90e 0x926 0x929>;
  2990. qcom,iommu-sid-mask = <0x200 0x208 0x202 0x200 0x200 0x202>;
  2991. label = "venus_sec_bitstream";
  2992. qcom,report-error-on-fault;
  2993. linux,phandle = <0xb5>;
  2994. phandle = <0xb5>;
  2995. };
  2996.  
  2997. qcom,iommu-ctx@1e26000 {
  2998. compatible = "qcom,msm-smmu-v2-ctx";
  2999. reg = <0x1e26000 0x1000>;
  3000. qcom,secure-context;
  3001. interrupts = <0x0 0x3c 0x0 0x0 0x3c 0x0>;
  3002. qcom,iommu-ctx-sids = <0x904 0x910 0x92c>;
  3003. qcom,iommu-sid-mask = <0x208 0x200 0x200>;
  3004. label = "venus_sec_pixel";
  3005. qcom,report-error-on-fault;
  3006. linux,phandle = <0xb6>;
  3007. phandle = <0xb6>;
  3008. };
  3009.  
  3010. qcom,iommu-ctx@1e28000 {
  3011. compatible = "qcom,msm-smmu-v2-ctx";
  3012. reg = <0x1e28000 0x1000>;
  3013. interrupts = <0x0 0x4c 0x0>;
  3014. qcom,iommu-ctx-sids = <0x1401 0x1402 0x1404>;
  3015. qcom,iommu-sid-mask = <0x3f2 0x3f0 0x3f0>;
  3016. label = "pronto_pil";
  3017. };
  3018.  
  3019. qcom,iommu-ctx@1e29000 {
  3020. compatible = "qcom,msm-smmu-v2-ctx";
  3021. reg = <0x1e29000 0x1000>;
  3022. interrupts = <0x0 0x4d 0x0>;
  3023. qcom,iommu-ctx-sids = <0x1000>;
  3024. qcom,iommu-sid-mask = <0x3fe>;
  3025. label = "q6";
  3026. };
  3027.  
  3028. qcom,iommu-ctx@1e2a000 {
  3029. compatible = "qcom,msm-smmu-v2-ctx";
  3030. reg = <0x1e2a000 0x1000>;
  3031. interrupts = <0x0 0x50 0x0>;
  3032. qcom,iommu-ctx-sids = <0x40>;
  3033. qcom,iommu-sid-mask = <0x3f>;
  3034. label = "periph_rpm";
  3035. };
  3036.  
  3037. qcom,iommu-ctx@1e2b000 {
  3038. compatible = "qcom,msm-smmu-v2-ctx";
  3039. reg = <0x1e2b000 0x1000>;
  3040. interrupts = <0x0 0x5e 0x0>;
  3041. qcom,iommu-ctx-sids = <0x1c0 0x1ca 0x1cc 0x1d0 0x1d6 0x1d8 0x1e0 0x1e4 0x1e8 0x1f0>;
  3042. qcom,iommu-sid-mask = <0x7 0x1 0x3 0x3 0x1 0x7 0x3 0x1 0x7 0x1>;
  3043. label = "lpass";
  3044. };
  3045.  
  3046. qcom,iommu-ctx@1e2f000 {
  3047. compatible = "qcom,msm-smmu-v2-ctx";
  3048. reg = <0x1e2f000 0x1000>;
  3049. interrupts = <0x0 0x68 0x0>;
  3050. qcom,iommu-ctx-sids = <0x2401>;
  3051. qcom,iommu-sid-mask = <0x3f0>;
  3052. label = "adsp_io";
  3053. qcom,virtual-addr-pool = <0x10000000 0xfffffff>;
  3054. #iommu-cells = <0x1>;
  3055. linux,phandle = <0x133>;
  3056. phandle = <0x133>;
  3057. };
  3058.  
  3059. qcom,iommu-ctx@1e30000 {
  3060. compatible = "qcom,msm-smmu-v2-ctx";
  3061. reg = <0x1e30000 0x1000>;
  3062. interrupts = <0x0 0x69 0x0>;
  3063. qcom,iommu-ctx-sids = <0x2404>;
  3064. qcom,iommu-sid-mask = <0x3f0>;
  3065. label = "adsp_opendsp";
  3066. };
  3067.  
  3068. qcom,iommu-ctx@1e31000 {
  3069. compatible = "qcom,msm-smmu-v2-ctx";
  3070. reg = <0x1e31000 0x1000>;
  3071. interrupts = <0x0 0x6a 0x0>;
  3072. qcom,iommu-ctx-sids = <0x2408>;
  3073. qcom,iommu-sid-mask = <0x3f7>;
  3074. label = "adsp_shared";
  3075. linux,phandle = <0x104>;
  3076. phandle = <0x104>;
  3077. };
  3078.  
  3079. qcom,iommu-ctx@1e32000 {
  3080. compatible = "qcom,msm-smmu-v2-ctx";
  3081. reg = <0x1e32000 0x1000>;
  3082. interrupts = <0x0 0x6d 0x0>;
  3083. qcom,iommu-ctx-sids = <0x1c00>;
  3084. qcom,iommu-sid-mask = <0x3fc>;
  3085. label = "cpp";
  3086. };
  3087.  
  3088. qcom,iommu-ctx@1e33000 {
  3089. compatible = "qcom,msm-smmu-v2-ctx";
  3090. reg = <0x1e33000 0x1000>;
  3091. interrupts = <0x0 0x6e 0x0>;
  3092. qcom,iommu-ctx-sids = <0x1800>;
  3093. qcom,iommu-sid-mask = <0x3fe>;
  3094. label = "jpeg_enc0";
  3095. };
  3096.  
  3097. qcom,iommu-ctx@1e34000 {
  3098. compatible = "qcom,msm-smmu-v2-ctx";
  3099. reg = <0x1e34000 0x1000>;
  3100. interrupts = <0x0 0x6f 0x0>;
  3101. qcom,iommu-ctx-sids = <0x400 0x2800>;
  3102. qcom,iommu-sid-mask = <0x3fc 0x3fc>;
  3103. label = "vfe";
  3104. };
  3105.  
  3106. qcom,iommu-ctx@1e35000 {
  3107. compatible = "qcom,msm-smmu-v2-ctx";
  3108. reg = <0x1e35000 0x1000>;
  3109. interrupts = <0x0 0x70 0x0>;
  3110. qcom,iommu-ctx-sids = <0xc00>;
  3111. qcom,iommu-sid-mask = <0x3fe>;
  3112. label = "mdp_0";
  3113. };
  3114.  
  3115. qcom,iommu-ctx@1e36000 {
  3116. compatible = "qcom,msm-smmu-v2-ctx";
  3117. reg = <0x1e36000 0x1000>;
  3118. interrupts = <0x0 0x71 0x0>;
  3119. qcom,iommu-ctx-sids = <0x800 0x807 0x808 0x810 0x828 0x82c 0x821>;
  3120. qcom,iommu-sid-mask = <0x201 0x200 0x207 0x201 0x203 0x201 0x210>;
  3121. label = "venus_ns";
  3122. qcom,report-error-on-fault;
  3123. linux,phandle = <0xb4>;
  3124. phandle = <0xb4>;
  3125. };
  3126.  
  3127. qcom,iommu-ctx@1e38000 {
  3128. compatible = "qcom,msm-smmu-v2-ctx";
  3129. reg = <0x1e38000 0x1000>;
  3130. interrupts = <0x0 0x73 0x0>;
  3131. qcom,iommu-ctx-sids = <0x2000 0x2004>;
  3132. qcom,iommu-sid-mask = <0x3fa 0x3f8>;
  3133. label = "ipa";
  3134. };
  3135.  
  3136. qcom,iommu-ctx@1e37000 {
  3137. compatible = "qcom,msm-smmu-v2-ctx";
  3138. reg = <0x1e37000 0x1000>;
  3139. interrupts = <0x0 0x72 0x0>;
  3140. qcom,iommu-ctx-sids = <0x1406 0x1408 0x140c 0x100 0x1d4 0x1e6 0x340>;
  3141. qcom,iommu-sid-mask = <0x3f1 0x3f3 0x3f1 0x7f 0x1 0x1 0x3f>;
  3142. label = "access_control";
  3143. };
  3144. };
  3145.  
  3146. tmc@6028000 {
  3147. compatible = "arm,coresight-tmc";
  3148. reg = <0x6028000 0x1000 0x6044000 0x15000>;
  3149. reg-names = "tmc-base", "bam-base";
  3150. interrupts = <0x0 0xa6 0x0>;
  3151. interrupt-names = "byte-cntr-irq";
  3152. qcom,memory-size = <0x100000>;
  3153. qcom,sg-enable;
  3154. qcom,force-reg-dump;
  3155. coresight-id = <0x0>;
  3156. coresight-name = "coresight-tmc-etr";
  3157. coresight-nr-inports = <0x1>;
  3158. coresight-ctis = <0x48 0x49>;
  3159. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  3160. clock-names = "core_clk", "core_a_clk";
  3161. linux,phandle = <0x6c>;
  3162. phandle = <0x6c>;
  3163. };
  3164.  
  3165. tpiu@6020000 {
  3166. compatible = "arm,coresight-tpiu";
  3167. reg = <0x6020000 0x1000 0x1100000 0xb0000>;
  3168. reg-names = "tpiu-base", "nidnt-base";
  3169. coresight-id = <0x1>;
  3170. coresight-name = "coresight-tpiu";
  3171. coresight-nr-inports = <0x1>;
  3172. pinctrl-names = "sdcard", "trace", "swduart", "swdtrc", "jtag", "spmi";
  3173. pinctrl-0 = <0x4a 0x4b 0x4c 0x4d 0x4e 0x4f>;
  3174. pinctrl-1 = <0x50 0x51 0x52 0x53 0x54 0x55>;
  3175. pinctrl-2 = <0x56 0x57 0x58 0x59 0x5a>;
  3176. pinctrl-3 = <0x5b 0x5c 0x5d 0x5e 0x5f 0x60>;
  3177. pinctrl-4 = <0x61 0x62 0x63 0x64 0x65>;
  3178. pinctrl-5 = <0x66 0x67 0x68 0x69>;
  3179. qcom,nidnthw;
  3180. qcom,nidnt-swduart;
  3181. qcom,nidnt-swdtrc;
  3182. qcom,nidnt-jtag;
  3183. qcom,nidnt-spmi;
  3184. nidnt-gpio = <0x85>;
  3185. nidnt-gpio-polarity = <0x1>;
  3186. interrupts = <0x0 0x52 0x0>;
  3187. interrupt-names = "nidnt-irq";
  3188. vdd-supply = <0x6a>;
  3189. qcom,vdd-voltage-level = <0x2d0370 0x2d0370>;
  3190. qcom,vdd-current-level = <0x3a98 0x61a80>;
  3191. vdd-io-supply = <0x6b>;
  3192. qcom,vdd-io-voltage-level = <0x2d0370 0x2d0370>;
  3193. qcom,vdd-io-current-level = <0xc8 0xc350>;
  3194. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  3195. clock-names = "core_clk", "core_a_clk";
  3196. linux,phandle = <0x6d>;
  3197. phandle = <0x6d>;
  3198. };
  3199.  
  3200. replicator@6026000 {
  3201. compatible = "qcom,coresight-replicator";
  3202. reg = <0x6026000 0x1000>;
  3203. reg-names = "replicator-base";
  3204. coresight-id = <0x2>;
  3205. coresight-name = "coresight-replicator";
  3206. coresight-nr-inports = <0x1>;
  3207. coresight-outports = <0x0 0x1>;
  3208. coresight-child-list = <0x6c 0x6d>;
  3209. coresight-child-ports = <0x0 0x0>;
  3210. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  3211. clock-names = "core_clk", "core_a_clk";
  3212. linux,phandle = <0x6e>;
  3213. phandle = <0x6e>;
  3214. };
  3215.  
  3216. tmc@6027000 {
  3217. compatible = "arm,coresight-tmc";
  3218. reg = <0x6027000 0x1000>;
  3219. reg-names = "tmc-base";
  3220. coresight-id = <0x3>;
  3221. coresight-name = "coresight-tmc-etf";
  3222. coresight-nr-inports = <0x1>;
  3223. coresight-outports = <0x0>;
  3224. coresight-child-list = <0x6e>;
  3225. coresight-child-ports = <0x0>;
  3226. coresight-default-sink;
  3227. coresight-ctis = <0x48 0x49>;
  3228. qcom,force-reg-dump;
  3229. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  3230. clock-names = "core_clk", "core_a_clk";
  3231. linux,phandle = <0x6f>;
  3232. phandle = <0x6f>;
  3233. };
  3234.  
  3235. funnel@6021000 {
  3236. compatible = "arm,coresight-funnel";
  3237. reg = <0x6021000 0x1000>;
  3238. reg-names = "funnel-base";
  3239. coresight-id = <0x4>;
  3240. coresight-name = "coresight-funnel-in0";
  3241. coresight-nr-inports = <0x8>;
  3242. coresight-outports = <0x0>;
  3243. coresight-child-list = <0x6f>;
  3244. coresight-child-ports = <0x0>;
  3245. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  3246. clock-names = "core_clk", "core_a_clk";
  3247. linux,phandle = <0x70>;
  3248. phandle = <0x70>;
  3249. };
  3250.  
  3251. funnel@6100000 {
  3252. compatible = "arm,coresight-funnel";
  3253. reg = <0x6100000 0x1000>;
  3254. reg-names = "funnel-base";
  3255. coresight-id = <0x5>;
  3256. coresight-name = "coresight-funnel-center";
  3257. coresight-nr-inports = <0x8>;
  3258. coresight-outports = <0x0>;
  3259. coresight-child-list = <0x70>;
  3260. coresight-child-ports = <0x3>;
  3261. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  3262. clock-names = "core_clk", "core_a_clk";
  3263. linux,phandle = <0x74>;
  3264. phandle = <0x74>;
  3265. };
  3266.  
  3267. funnel@6120000 {
  3268. compatible = "arm,coresight-funnel";
  3269. reg = <0x6120000 0x1000>;
  3270. reg-names = "funnel-base";
  3271. coresight-id = <0x6>;
  3272. coresight-name = "coresight-funnel-right";
  3273. coresight-nr-inports = <0x8>;
  3274. coresight-outports = <0x0>;
  3275. coresight-child-list = <0x70>;
  3276. coresight-child-ports = <0x4>;
  3277. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  3278. clock-names = "core_clk", "core_a_clk";
  3279. linux,phandle = <0x71>;
  3280. phandle = <0x71>;
  3281. };
  3282.  
  3283. funnel@6130000 {
  3284. compatible = "arm,coresight-funnel";
  3285. reg = <0x6130000 0x1000>;
  3286. reg-names = "funnel-base";
  3287. coresight-id = <0x7>;
  3288. coresight-name = "coesight-funnel-mm";
  3289. coresight-nr-inports = <0x8>;
  3290. coresight-outports = <0x0>;
  3291. coresight-child-list = <0x70>;
  3292. coresight-child-ports = <0x5>;
  3293. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  3294. clock-names = "core_clk", "core_a_clk";
  3295. linux,phandle = <0x3c>;
  3296. phandle = <0x3c>;
  3297. };
  3298.  
  3299. funnel@6132000 {
  3300. compatible = "arm,coresight-funnel";
  3301. reg = <0x6132000 0x1000>;
  3302. reg-names = "funnel-base";
  3303. coresight-id = <0x8>;
  3304. coresight-name = "coresight-funnel-cam";
  3305. coresight-nr-inports = <0x8>;
  3306. coresight-outports = <0x0>;
  3307. coresight-child-list = <0x3c>;
  3308. coresight-child-ports = <0x4>;
  3309. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  3310. clock-names = "core_clk", "core_a_clk";
  3311. };
  3312.  
  3313. funnel@61d0000 {
  3314. compatible = "arm,coresight-funnel";
  3315. reg = <0x61d0000 0x1000>;
  3316. reg-names = "funnel-base";
  3317. coresight-id = <0x9>;
  3318. coresight-name = "coresight-funnel-apss1";
  3319. coresight-nr-inports = <0x8>;
  3320. coresight-outports = <0x0>;
  3321. coresight-child-list = <0x71>;
  3322. coresight-child-ports = <0x3>;
  3323. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  3324. clock-names = "core_clk", "core_a_clk";
  3325. linux,phandle = <0x72>;
  3326. phandle = <0x72>;
  3327. };
  3328.  
  3329. funnel@61a1000 {
  3330. compatible = "arm,coresight-funnel";
  3331. reg = <0x61a1000 0x1000>;
  3332. reg-names = "funnel-base";
  3333. coresight-id = <0xa>;
  3334. coresight-name = "coresight-funnel-apss0";
  3335. coresight-nr-inports = <0x8>;
  3336. coresight-outports = <0x0>;
  3337. coresight-child-list = <0x72>;
  3338. coresight-child-ports = <0x0>;
  3339. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  3340. clock-names = "core_clk", "core_a_clk";
  3341. linux,phandle = <0x73>;
  3342. phandle = <0x73>;
  3343. };
  3344.  
  3345. etm@619c000 {
  3346. compatible = "arm,coresight-etmv4";
  3347. reg = <0x619c000 0x1000>;
  3348. reg-names = "etm-base";
  3349. coresight-id = <0xb>;
  3350. coresight-name = "coresight-etm0";
  3351. coresight-nr-inports = <0x0>;
  3352. coresight-outports = <0x0>;
  3353. coresight-child-list = <0x73>;
  3354. coresight-child-ports = <0x0>;
  3355. coresight-etm-cpu = <0x2>;
  3356. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  3357. clock-names = "core_clk", "core_a_clk";
  3358. };
  3359.  
  3360. etm@619d000 {
  3361. compatible = "arm,coresight-etmv4";
  3362. reg = <0x619d000 0x1000>;
  3363. reg-names = "etm-base";
  3364. coresight-id = <0xc>;
  3365. coresight-name = "coresight-etm1";
  3366. coresight-nr-inports = <0x0>;
  3367. coresight-outports = <0x0>;
  3368. coresight-child-list = <0x73>;
  3369. coresight-child-ports = <0x1>;
  3370. coresight-etm-cpu = <0x3>;
  3371. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  3372. clock-names = "core_clk", "core_a_clk";
  3373. };
  3374.  
  3375. etm@619e000 {
  3376. compatible = "arm,coresight-etmv4";
  3377. reg = <0x619e000 0x1000>;
  3378. reg-names = "etm-base";
  3379. coresight-id = <0xd>;
  3380. coresight-name = "coresight-etm2";
  3381. coresight-nr-inports = <0x0>;
  3382. coresight-outports = <0x0>;
  3383. coresight-child-list = <0x73>;
  3384. coresight-child-ports = <0x2>;
  3385. coresight-etm-cpu = <0x4>;
  3386. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  3387. clock-names = "core_clk", "core_a_clk";
  3388. };
  3389.  
  3390. etm@619f000 {
  3391. compatible = "arm,coresight-etmv4";
  3392. reg = <0x619f000 0x1000>;
  3393. reg-names = "etm-base";
  3394. coresight-id = <0xe>;
  3395. coresight-name = "coresight-etm3";
  3396. coresight-nr-inports = <0x0>;
  3397. coresight-outports = <0x0>;
  3398. coresight-child-list = <0x73>;
  3399. coresight-child-ports = <0x3>;
  3400. coresight-etm-cpu = <0x5>;
  3401. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  3402. clock-names = "core_clk", "core_a_clk";
  3403. };
  3404.  
  3405. etm@61bc000 {
  3406. compatible = "arm,coresight-etmv4";
  3407. reg = <0x61bc000 0x1000>;
  3408. reg-names = "etm-base";
  3409. coresight-id = <0xf>;
  3410. coresight-name = "coresight-etm4";
  3411. coresight-nr-inports = <0x0>;
  3412. coresight-outports = <0x0>;
  3413. coresight-child-list = <0x73>;
  3414. coresight-child-ports = <0x4>;
  3415. coresight-etm-cpu = <0x6>;
  3416. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  3417. clock-names = "core_clk", "core_a_clk";
  3418. };
  3419.  
  3420. etm@61bd000 {
  3421. compatible = "arm,coresight-etmv4";
  3422. reg = <0x61bd000 0x1000>;
  3423. reg-names = "etm-base";
  3424. coresight-id = <0x10>;
  3425. coresight-name = "coresight-etm5";
  3426. coresight-nr-inports = <0x0>;
  3427. coresight-outports = <0x0>;
  3428. coresight-child-list = <0x73>;
  3429. coresight-child-ports = <0x5>;
  3430. coresight-etm-cpu = <0x7>;
  3431. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  3432. clock-names = "core_clk", "core_a_clk";
  3433. };
  3434.  
  3435. etm@61be000 {
  3436. compatible = "arm,coresight-etmv4";
  3437. reg = <0x61be000 0x1000>;
  3438. reg-names = "etm-base";
  3439. coresight-id = <0x11>;
  3440. coresight-name = "coresight-etm6";
  3441. coresight-nr-inports = <0x0>;
  3442. coresight-outports = <0x0>;
  3443. coresight-child-list = <0x73>;
  3444. coresight-child-ports = <0x6>;
  3445. coresight-etm-cpu = <0x8>;
  3446. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  3447. clock-names = "core_clk", "core_a_clk";
  3448. };
  3449.  
  3450. etm@61bf000 {
  3451. compatible = "arm,coresight-etmv4";
  3452. reg = <0x61bf000 0x1000>;
  3453. reg-names = "etm-base";
  3454. coresight-id = <0x12>;
  3455. coresight-name = "coresight-etm7";
  3456. coresight-nr-inports = <0x0>;
  3457. coresight-outports = <0x0>;
  3458. coresight-child-list = <0x73>;
  3459. coresight-child-ports = <0x7>;
  3460. coresight-etm-cpu = <0x9>;
  3461. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  3462. clock-names = "core_clk", "core_a_clk";
  3463. };
  3464.  
  3465. stm@6002000 {
  3466. compatible = "arm,coresight-stm";
  3467. reg = <0x6002000 0x1000 0x9280000 0x180000>;
  3468. reg-names = "stm-base", "stm-data-base";
  3469. coresight-id = <0x13>;
  3470. coresight-name = "coresight-stm";
  3471. coresight-nr-inports = <0x0>;
  3472. coresight-outports = <0x0>;
  3473. coresight-child-list = <0x70>;
  3474. coresight-child-ports = <0x7>;
  3475. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  3476. clock-names = "core_clk", "core_a_clk";
  3477. };
  3478.  
  3479. cti@6010000 {
  3480. compatible = "arm,coresight-cti";
  3481. reg = <0x6010000 0x1000>;
  3482. reg-names = "cti-base";
  3483. coresight-id = <0x14>;
  3484. coresight-name = "coresight-cti0";
  3485. coresight-nr-inports = <0x0>;
  3486. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  3487. clock-names = "core_clk", "core_a_clk";
  3488. linux,phandle = <0x48>;
  3489. phandle = <0x48>;
  3490. };
  3491.  
  3492. cti@6011000 {
  3493. compatible = "arm,coresight-cti";
  3494. reg = <0x6011000 0x1000>;
  3495. reg-names = "cti-base";
  3496. coresight-id = <0x15>;
  3497. coresight-name = "coresight-cti1";
  3498. coresight-nr-inports = <0x0>;
  3499. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  3500. clock-names = "core_clk", "core_a_clk";
  3501. };
  3502.  
  3503. cti@6012000 {
  3504. compatible = "arm,coresight-cti";
  3505. reg = <0x6012000 0x1000>;
  3506. reg-names = "cti-base";
  3507. coresight-id = <0x16>;
  3508. coresight-name = "coresight-cti2";
  3509. coresight-nr-inports = <0x0>;
  3510. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  3511. clock-names = "core_clk", "core_a_clk";
  3512. };
  3513.  
  3514. cti@6013000 {
  3515. compatible = "arm,coresight-cti";
  3516. reg = <0x6013000 0x1000>;
  3517. reg-names = "cti-base";
  3518. coresight-id = <0x17>;
  3519. coresight-name = "coresight-cti3";
  3520. coresight-nr-inports = <0x0>;
  3521. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  3522. clock-names = "core_clk", "core_a_clk";
  3523. };
  3524.  
  3525. cti@6014000 {
  3526. compatible = "arm,coresight-cti";
  3527. reg = <0x6014000 0x1000>;
  3528. reg-names = "cti-base";
  3529. coresight-id = <0x18>;
  3530. coresight-name = "coresight-cti4";
  3531. coresight-nr-inports = <0x0>;
  3532. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  3533. clock-names = "core_clk", "core_a_clk";
  3534. };
  3535.  
  3536. cti@6015000 {
  3537. compatible = "arm,coresight-cti";
  3538. reg = <0x6015000 0x1000>;
  3539. reg-names = "cti-base";
  3540. coresight-id = <0x19>;
  3541. coresight-name = "coresight-cti5";
  3542. coresight-nr-inports = <0x0>;
  3543. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  3544. clock-names = "core_clk", "core_a_clk";
  3545. };
  3546.  
  3547. cti@6016000 {
  3548. compatible = "arm,coresight-cti";
  3549. reg = <0x6016000 0x1000>;
  3550. reg-names = "cti-base";
  3551. coresight-id = <0x1a>;
  3552. coresight-name = "coresight-cti6";
  3553. coresight-nr-inports = <0x0>;
  3554. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  3555. clock-names = "core_clk", "core_a_clk";
  3556. };
  3557.  
  3558. cti@6017000 {
  3559. compatible = "arm,coresight-cti";
  3560. reg = <0x6017000 0x1000>;
  3561. reg-names = "cti-base";
  3562. coresight-id = <0x1b>;
  3563. coresight-name = "coresight-cti7";
  3564. coresight-nr-inports = <0x0>;
  3565. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  3566. clock-names = "core_clk", "core_a_clk";
  3567. };
  3568.  
  3569. cti@6018000 {
  3570. compatible = "arm,coresight-cti";
  3571. reg = <0x6018000 0x1000>;
  3572. reg-names = "cti-base";
  3573. coresight-id = <0x1c>;
  3574. coresight-name = "coresight-cti8";
  3575. coresight-nr-inports = <0x0>;
  3576. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  3577. clock-names = "core_clk", "core_a_clk";
  3578. linux,phandle = <0x49>;
  3579. phandle = <0x49>;
  3580. };
  3581.  
  3582. cti@6019000 {
  3583. compatible = "arm,coresight-cti";
  3584. reg = <0x6019000 0x1000>;
  3585. reg-names = "cti-base";
  3586. coresight-id = <0x1d>;
  3587. coresight-name = "coresight-cti9";
  3588. coresight-nr-inports = <0x0>;
  3589. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  3590. clock-names = "core_clk", "core_a_clk";
  3591. };
  3592.  
  3593. cti@601a000 {
  3594. compatible = "arm,coresight-cti";
  3595. reg = <0x601a000 0x1000>;
  3596. reg-names = "cti-base";
  3597. coresight-id = <0x1e>;
  3598. coresight-name = "coresight-cti10";
  3599. coresight-nr-inports = <0x0>;
  3600. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  3601. clock-names = "core_clk", "core_a_clk";
  3602. };
  3603.  
  3604. cti@601b000 {
  3605. compatible = "arm,coresight-cti";
  3606. reg = <0x601b000 0x1000>;
  3607. reg-names = "cti-base";
  3608. coresight-id = <0x1f>;
  3609. coresight-name = "coresight-cti11";
  3610. coresight-nr-inports = <0x0>;
  3611. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  3612. clock-names = "core_clk", "core_a_clk";
  3613. };
  3614.  
  3615. cti@601c000 {
  3616. compatible = "arm,coresight-cti";
  3617. reg = <0x601c000 0x1000>;
  3618. reg-names = "cti-base";
  3619. coresight-id = <0x20>;
  3620. coresight-name = "coresight-cti12";
  3621. coresight-nr-inports = <0x0>;
  3622. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  3623. clock-names = "core_clk", "core_a_clk";
  3624. };
  3625.  
  3626. cti@601d000 {
  3627. compatible = "arm,coresight-cti";
  3628. reg = <0x601d000 0x1000>;
  3629. reg-names = "cti-base";
  3630. coresight-id = <0x21>;
  3631. coresight-name = "coresight-cti13";
  3632. coresight-nr-inports = <0x0>;
  3633. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  3634. clock-names = "core_clk", "core_a_clk";
  3635. };
  3636.  
  3637. cti@601e000 {
  3638. compatible = "arm,coresight-cti";
  3639. reg = <0x601e000 0x1000>;
  3640. reg-names = "cti-base";
  3641. coresight-id = <0x22>;
  3642. coresight-name = "coresight-cti14";
  3643. coresight-nr-inports = <0x0>;
  3644. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  3645. clock-names = "core_clk", "core_a_clk";
  3646. };
  3647.  
  3648. cti@601f000 {
  3649. compatible = "arm,coresight-cti";
  3650. reg = <0x601f000 0x1000>;
  3651. reg-names = "cti-base";
  3652. coresight-id = <0x23>;
  3653. coresight-name = "coresight-cti15";
  3654. coresight-nr-inports = <0x0>;
  3655. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  3656. clock-names = "core_clk", "core_a_clk";
  3657. };
  3658.  
  3659. cti@6198000 {
  3660. compatible = "arm,coresight-cti";
  3661. reg = <0x6198000 0x1000>;
  3662. reg-names = "cti-base";
  3663. coresight-id = <0x24>;
  3664. coresight-name = "coresight-cti-cpu0";
  3665. coresight-nr-inports = <0x0>;
  3666. coresight-cti-cpu = <0x2>;
  3667. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  3668. clock-names = "core_clk", "core_a_clk";
  3669. };
  3670.  
  3671. cti@6199000 {
  3672. compatible = "arm,coresight-cti";
  3673. reg = <0x6199000 0x1000>;
  3674. reg-names = "cti-base";
  3675. coresight-id = <0x25>;
  3676. coresight-name = "coresight-cti-cpu1";
  3677. coresight-nr-inports = <0x0>;
  3678. coresight-cti-cpu = <0x3>;
  3679. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  3680. clock-names = "core_clk", "core_a_clk";
  3681. };
  3682.  
  3683. cti@619a000 {
  3684. compatible = "arm,coresight-cti";
  3685. reg = <0x619a000 0x1000>;
  3686. reg-names = "cti-base";
  3687. coresight-id = <0x26>;
  3688. coresight-name = "coresight-cti-cpu2";
  3689. coresight-nr-inports = <0x0>;
  3690. coresight-cti-cpu = <0x4>;
  3691. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  3692. clock-names = "core_clk", "core_a_clk";
  3693. };
  3694.  
  3695. cti@619b000 {
  3696. compatible = "arm,coresight-cti";
  3697. reg = <0x619b000 0x1000>;
  3698. reg-names = "cti-base";
  3699. coresight-id = <0x27>;
  3700. coresight-name = "coresight-cti-cpu3";
  3701. coresight-nr-inports = <0x0>;
  3702. coresight-cti-cpu = <0x5>;
  3703. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  3704. clock-names = "core_clk", "core_a_clk";
  3705. };
  3706.  
  3707. cti@61b8000 {
  3708. compatible = "arm,coresight-cti";
  3709. reg = <0x61b8000 0x1000>;
  3710. reg-names = "cti-base";
  3711. coresight-id = <0x28>;
  3712. coresight-name = "coresight-cti-cpu4";
  3713. coresight-nr-inports = <0x0>;
  3714. coresight-cti-cpu = <0x6>;
  3715. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  3716. clock-names = "core_clk", "core_a_clk";
  3717. };
  3718.  
  3719. cti@61b9000 {
  3720. compatible = "arm,coresight-cti";
  3721. reg = <0x61b9000 0x1000>;
  3722. reg-names = "cti-base";
  3723. coresight-id = <0x29>;
  3724. coresight-name = "coresight-cti-cpu5";
  3725. coresight-nr-inports = <0x0>;
  3726. coresight-cti-cpu = <0x7>;
  3727. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  3728. clock-names = "core_clk", "core_a_clk";
  3729. };
  3730.  
  3731. cti@61ba000 {
  3732. compatible = "arm,coresight-cti";
  3733. reg = <0x61ba000 0x1000>;
  3734. reg-names = "cti-base";
  3735. coresight-id = <0x2a>;
  3736. coresight-name = "coresight-cti-cpu6";
  3737. coresight-nr-inports = <0x0>;
  3738. coresight-cti-cpu = <0x8>;
  3739. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  3740. clock-names = "core_clk", "core_a_clk";
  3741. };
  3742.  
  3743. cti@61bb000 {
  3744. compatible = "arm,coresight-cti";
  3745. reg = <0x61bb000 0x1000>;
  3746. reg-names = "cti-base";
  3747. coresight-id = <0x2b>;
  3748. coresight-name = "coresight-cti-cpu7";
  3749. coresight-nr-inports = <0x0>;
  3750. coresight-cti-cpu = <0x9>;
  3751. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  3752. clock-names = "core_clk", "core_a_clk";
  3753. };
  3754.  
  3755. cti@6124000 {
  3756. compatible = "arm,coresight-cti";
  3757. reg = <0x6124000 0x1000>;
  3758. reg-names = "cti-base";
  3759. coresight-id = <0x2c>;
  3760. coresight-name = "coresight-cti-modem-cpu0";
  3761. coresight-nr-inports = <0x0>;
  3762. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  3763. clock-names = "core_clk", "core_a_clk";
  3764. };
  3765.  
  3766. cti@6128000 {
  3767. compatible = "arm,coresight-cti";
  3768. reg = <0x6128000 0x1000>;
  3769. reg-names = "cti-base";
  3770. coresight-id = <0x2d>;
  3771. coresight-name = "coresight-cti-modem-cpu1";
  3772. coresight-nr-inports = <0x0>;
  3773. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  3774. clock-names = "core_clk", "core_a_clk";
  3775. };
  3776.  
  3777. cti@6134000 {
  3778. compatible = "arm,coresight-cti";
  3779. reg = <0x6134000 0x1000>;
  3780. reg-names = "cti-base";
  3781. coresight-id = <0x2e>;
  3782. coresight-name = "coresight-cti-video-cpu0";
  3783. coresight-nr-inports = <0x0>;
  3784. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  3785. clock-names = "core_clk", "core_a_clk";
  3786. };
  3787.  
  3788. cti@6139000 {
  3789. compatible = "arm,coresight-cti";
  3790. reg = <0x6139000 0x1000>;
  3791. reg-names = "cti-base";
  3792. coresight-id = <0x2f>;
  3793. coresight-name = "coresight-cti-wcn-cpu0";
  3794. coresight-nr-inports = <0x0>;
  3795. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  3796. clock-names = "core_clk", "core_a_clk";
  3797. };
  3798.  
  3799. cti@613c000 {
  3800. compatible = "arm,coresight-cti";
  3801. reg = <0x613c000 0x1000>;
  3802. reg-names = "cti-base";
  3803. coresight-id = <0x30>;
  3804. coresight-name = "coresight-cti-audio-cpu0";
  3805. coresight-nr-inports = <0x0>;
  3806. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  3807. clock-names = "core_clk", "core_a_clk";
  3808. };
  3809.  
  3810. cti@610c000 {
  3811. compatible = "arm,coresight-cti";
  3812. reg = <0x610c000 0x1000>;
  3813. reg-names = "cti-base";
  3814. coresight-id = <0x31>;
  3815. coresight-name = "coresight-cti-rpm-cpu0";
  3816. coresight-nr-inports = <0x0>;
  3817. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  3818. clock-names = "core_clk", "core_a_clk";
  3819. };
  3820.  
  3821. wcn_etm0 {
  3822. compatible = "qcom,coresight-remote-etm";
  3823. coresight-id = <0x32>;
  3824. coresight-name = "coresight-wcn-etm0";
  3825. coresight-nr-inports = <0x0>;
  3826. coresight-outports = <0x0>;
  3827. coresight-child-list = <0x3c>;
  3828. coresight-child-ports = <0x0>;
  3829. qcom,inst-id = <0x3>;
  3830. };
  3831.  
  3832. rpm_etm0 {
  3833. compatible = "qcom,coresight-remote-etm";
  3834. coresight-id = <0x33>;
  3835. coresight-name = "coresight-rpm-etm0";
  3836. coresight-nr-inports = <0x0>;
  3837. coresight-outports = <0x0>;
  3838. coresight-child-list = <0x74>;
  3839. coresight-child-ports = <0x0>;
  3840. qcom,inst-id = <0x4>;
  3841. };
  3842.  
  3843. audio_etm0 {
  3844. compatible = "qcom,coresight-remote-etm";
  3845. coresight-id = <0x34>;
  3846. coresight-name = "coresight-audio-etm0";
  3847. coresight-nr-inports = <0x0>;
  3848. coresight-outports = <0x0>;
  3849. coresight-child-list = <0x3c>;
  3850. coresight-child-ports = <0x5>;
  3851. qcom,inst-id = <0x5>;
  3852. };
  3853.  
  3854. modem_etm0 {
  3855. compatible = "qcom,coresight-remote-etm";
  3856. coresight-id = <0x35>;
  3857. coresight-name = "coresight-modem-etm0";
  3858. coresight-nr-inports = <0x0>;
  3859. coresight-outports = <0x0>;
  3860. coresight-child-list = <0x71>;
  3861. coresight-child-ports = <0x2>;
  3862. qcom,inst-id = <0xb>;
  3863. };
  3864.  
  3865. modem_etm1 {
  3866. compatible = "qcom,coresight-remote-etm";
  3867. coresight-id = <0x36>;
  3868. coresight-name = "coresight-modem-etm1";
  3869. coresight-nr-inports = <0x0>;
  3870. coresight-outports = <0x0>;
  3871. coresight-child-list = <0x71>;
  3872. coresight-child-ports = <0x1>;
  3873. qcom,inst-id = <0x2>;
  3874. };
  3875.  
  3876. csr@6001000 {
  3877. compatible = "qcom,coresight-csr";
  3878. reg = <0x6001000 0x1000>;
  3879. reg-names = "csr-base";
  3880. coresight-id = <0x37>;
  3881. coresight-name = "coresight-csr";
  3882. coresight-nr-inports = <0x0>;
  3883. qcom,blk-size = <0x1>;
  3884. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  3885. clock-names = "core_clk", "core_a_clk";
  3886. };
  3887.  
  3888. dbgui@6108000 {
  3889. compatible = "qcom,coresight-dbgui";
  3890. reg = <0x6108000 0x1000>;
  3891. reg-names = "dbgui-base";
  3892. coresight-id = <0x38>;
  3893. coresight-name = "coresight-dbgui";
  3894. coresight-nr-inports = <0x0>;
  3895. coresight-outports = <0x0>;
  3896. coresight-child-list = <0x74>;
  3897. coresight-child-ports = <0x2>;
  3898. qcom,dbgui-addr-offset = <0x30>;
  3899. qcom,dbgui-data-offset = <0x130>;
  3900. qcom,dbgui-size = <0x40>;
  3901. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  3902. clock-names = "core_clk", "core_a_clk";
  3903. };
  3904.  
  3905. tpda@6003000 {
  3906. compatible = "qcom,coresight-tpda";
  3907. reg = <0x6003000 0x1000>;
  3908. reg-names = "tpda-base";
  3909. coresight-id = <0x39>;
  3910. coresight-name = "coresight-tpda";
  3911. coresight-nr-inports = <0x2>;
  3912. coresight-outports = <0x0>;
  3913. coresight-child-list = <0x70>;
  3914. coresight-child-ports = <0x6>;
  3915. qcom,tpda-atid = <0x40>;
  3916. qcom,cmb-elem-size = <0x0 0x20>;
  3917. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  3918. clock-names = "core_clk", "core_a_clk";
  3919. linux,phandle = <0x75>;
  3920. phandle = <0x75>;
  3921. };
  3922.  
  3923. tpdm@6110000 {
  3924. compatible = "qcom,coresight-tpdm";
  3925. reg = <0x6110000 0x1000>;
  3926. reg-names = "tpdm-base";
  3927. coresight-id = <0x3a>;
  3928. coresight-name = "coresight-tpdm-dcc";
  3929. coresight-nr-inports = <0x1>;
  3930. coresight-outports = <0x0>;
  3931. coresight-child-list = <0x75>;
  3932. coresight-child-ports = <0x0>;
  3933. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  3934. clock-names = "core_clk", "core_a_clk";
  3935. };
  3936.  
  3937. hwevent@6101000 {
  3938. compatible = "qcom,coresight-hwevent";
  3939. reg = <0x6101000 0x148 0x6101fb0 0x4 0x6121000 0x148 0x6121fb0 0x4 0x6131000 0x148 0x6131fb0 0x4 0x7105010 0x4 0x7885010 0x4>;
  3940. reg-names = "center-wrapper-mux", "center-wrapper-lockaccess", "right-wrapper-mux", "right-wrapper-lockaccess", "mm-wrapper-mux", "mm-wrapper-lockaccess", "usbbam-mux", "blsp-mux";
  3941. coresight-id = <0x3b>;
  3942. coresight-name = "coresight-hwevent";
  3943. coresight-nr-inports = <0x0>;
  3944. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  3945. clock-names = "core_clk", "core_a_clk";
  3946. };
  3947.  
  3948. fuse@a601c {
  3949. compatible = "arm,coresight-fuse-v2";
  3950. reg = <0xa601c 0x8 0xa6004 0x4 0xa600c 0x4>;
  3951. reg-names = "fuse-base", "nidnt-fuse-base", "qpdi-fuse-base";
  3952. coresight-id = <0x3c>;
  3953. coresight-name = "coresight-fuse";
  3954. coresight-nr-inports = <0x0>;
  3955. };
  3956.  
  3957. qpdi@1941000 {
  3958. compatible = "qcom,coresight-qpdi";
  3959. reg = <0x1941000 0x4>;
  3960. reg-names = "qpdi-base";
  3961. coresight-id = <0x3d>;
  3962. coresight-name = "coresight-qpdi";
  3963. coresight-nr-inports = <0x0>;
  3964. vdd-supply = <0x6a>;
  3965. qcom,vdd-voltage-level = <0x2d0370 0x2d0370>;
  3966. qcom,vdd-current-level = <0x3a98 0x61a80>;
  3967. vdd-io-supply = <0x6b>;
  3968. qcom,vdd-io-voltage-level = <0x2d0370 0x2d0370>;
  3969. qcom,vdd-io-current-level = <0xc8 0xc350>;
  3970. };
  3971.  
  3972. ad-hoc-bus@580000 {
  3973. compatible = "qcom,msm-bus-device";
  3974. reg = <0x580000 0x16080 0x580000 0x16080 0x400000 0x5a000 0x500000 0x12080>;
  3975. reg-names = "snoc-base", "snoc-mm-base", "bimc-base", "pcnoc-base";
  3976.  
  3977. fab-bimc {
  3978. cell-id = <0x0>;
  3979. label = "fab-bimc";
  3980. qcom,fab-dev;
  3981. qcom,base-name = "bimc-base";
  3982. qcom,bus-type = <0x2>;
  3983. qcom,util-fact = <0x99>;
  3984. clock-names = "bus_clk", "bus_a_clk";
  3985. clocks = <0x37 0xd212feea 0x37 0x71d1a499>;
  3986. coresight-id = <0xcb>;
  3987. coresight-name = "coresight-bimc";
  3988. coresight-nr-inports = <0x0>;
  3989. coresight-outports = <0x0>;
  3990. coresight-child-list = <0x70>;
  3991. coresight-child-ports = <0x2>;
  3992. linux,phandle = <0x78>;
  3993. phandle = <0x78>;
  3994. };
  3995.  
  3996. fab-pcnoc {
  3997. cell-id = <0x1000>;
  3998. label = "fab-pcnoc";
  3999. qcom,fab-dev;
  4000. qcom,base-name = "pcnoc-base";
  4001. qcom,base-offset = <0x7000>;
  4002. qcom,qos-off = <0x1000>;
  4003. qcom,bus-type = <0x1>;
  4004. clock-names = "bus_clk", "bus_a_clk";
  4005. clocks = <0x37 0x2b53b688 0x37 0x9753a54f>;
  4006. coresight-id = <0xc9>;
  4007. coresight-name = "coresight-pcnoc";
  4008. coresight-nr-inports = <0x0>;
  4009. coresight-outports = <0x0>;
  4010. coresight-child-list = <0x74>;
  4011. coresight-child-ports = <0x3>;
  4012. linux,phandle = <0x7a>;
  4013. phandle = <0x7a>;
  4014.  
  4015. qcom,node-qos-clks {
  4016. clock-names = "pcnoc-usb3-axi-no-rate";
  4017. clocks = <0x37 0xf7f4b314>;
  4018. };
  4019. };
  4020.  
  4021. fab-snoc {
  4022. cell-id = <0x400>;
  4023. label = "fab-snoc";
  4024. qcom,fab-dev;
  4025. qcom,base-name = "snoc-base";
  4026. qcom,base-offset = <0x7000>;
  4027. qcom,qos-off = <0x1000>;
  4028. qcom,bus-type = <0x1>;
  4029. clock-names = "bus_clk", "bus_a_clk";
  4030. clocks = <0x37 0xe6900bb6 0x37 0x5d4683bd>;
  4031. coresight-id = <0xc8>;
  4032. coresight-name = "coresight-snoc";
  4033. coresight-nr-inports = <0x0>;
  4034. coresight-outports = <0x0>;
  4035. coresight-child-list = <0x74>;
  4036. coresight-child-ports = <0x4>;
  4037. linux,phandle = <0x7f>;
  4038. phandle = <0x7f>;
  4039. };
  4040.  
  4041. fab-snoc-mm {
  4042. cell-id = <0x800>;
  4043. label = "fab-snoc-mm";
  4044. qcom,fab-dev;
  4045. qcom,base-name = "snoc-mm-base";
  4046. qcom,base-offset = <0x7000>;
  4047. qcom,qos-off = <0x1000>;
  4048. qcom,bus-type = <0x1>;
  4049. qcom,util-fact = <0x99>;
  4050. clock-names = "bus_clk", "bus_a_clk";
  4051. clocks = <0x37 0xd61e5721 0x37 0x50600f1b>;
  4052. linux,phandle = <0x84>;
  4053. phandle = <0x84>;
  4054. };
  4055.  
  4056. mas-apps-proc {
  4057. cell-id = <0x1>;
  4058. label = "mas-apps-proc";
  4059. qcom,buswidth = <0x8>;
  4060. qcom,agg-ports = <0x1>;
  4061. qcom,ap-owned;
  4062. qcom,qport = <0x0>;
  4063. qcom,qos-mode = "fixed";
  4064. qcom,connections = <0x76 0x77>;
  4065. qcom,prio-lvl = <0x0>;
  4066. qcom,prio-rd = <0x0>;
  4067. qcom,prio-wr = <0x0>;
  4068. qcom,bus-dev = <0x78>;
  4069. qcom,mas-rpm-id = <0x0>;
  4070. };
  4071.  
  4072. mas-oxili {
  4073. cell-id = <0x1a>;
  4074. label = "mas-oxili";
  4075. qcom,buswidth = <0x8>;
  4076. qcom,agg-ports = <0x1>;
  4077. qcom,ap-owned;
  4078. qcom,qport = <0x2>;
  4079. qcom,qos-mode = "fixed";
  4080. qcom,connections = <0x76 0x77>;
  4081. qcom,prio-lvl = <0x0>;
  4082. qcom,prio-rd = <0x0>;
  4083. qcom,prio-wr = <0x0>;
  4084. qcom,bus-dev = <0x78>;
  4085. qcom,mas-rpm-id = <0x6>;
  4086. };
  4087.  
  4088. mas-snoc-bimc-0 {
  4089. cell-id = <0x2717>;
  4090. label = "mas-snoc-bimc-0";
  4091. qcom,buswidth = <0x8>;
  4092. qcom,agg-ports = <0x1>;
  4093. qcom,ap-owned;
  4094. qcom,qport = <0x3>;
  4095. qcom,qos-mode = "bypass";
  4096. qcom,connections = <0x76 0x77>;
  4097. qcom,bus-dev = <0x78>;
  4098. qcom,mas-rpm-id = <0x3>;
  4099. linux,phandle = <0xaf>;
  4100. phandle = <0xaf>;
  4101. };
  4102.  
  4103. mas-snoc-bimc-2 {
  4104. cell-id = <0x273d>;
  4105. label = "mas-snoc-bimc-2";
  4106. qcom,buswidth = <0x8>;
  4107. qcom,agg-ports = <0x1>;
  4108. qcom,ap-owned;
  4109. qcom,qport = <0x4>;
  4110. qcom,qos-mode = "bypass";
  4111. qcom,connections = <0x76 0x77>;
  4112. qcom,bus-dev = <0x78>;
  4113. qcom,mas-rpm-id = <0x6c>;
  4114. linux,phandle = <0xb1>;
  4115. phandle = <0xb1>;
  4116. };
  4117.  
  4118. mas-snoc-bimc-1 {
  4119. cell-id = <0x2718>;
  4120. label = "mas-snoc-bimc-1";
  4121. qcom,buswidth = <0x8>;
  4122. qcom,agg-ports = <0x1>;
  4123. qcom,qport = <0x5>;
  4124. qcom,qos-mode = "bypass";
  4125. qcom,connections = <0x76>;
  4126. qcom,bus-dev = <0x78>;
  4127. qcom,mas-rpm-id = <0x4c>;
  4128. linux,phandle = <0xb0>;
  4129. phandle = <0xb0>;
  4130. };
  4131.  
  4132. mas-tcu-0 {
  4133. cell-id = <0x68>;
  4134. label = "mas-tcu-0";
  4135. qcom,buswidth = <0x8>;
  4136. qcom,agg-ports = <0x1>;
  4137. qcom,ap-owned;
  4138. qcom,qport = <0x6>;
  4139. qcom,qos-mode = "fixed";
  4140. qcom,connections = <0x76 0x77>;
  4141. qcom,prio-lvl = <0x2>;
  4142. qcom,prio-rd = <0x2>;
  4143. qcom,bus-dev = <0x78>;
  4144. qcom,mas-rpm-id = <0x66>;
  4145. };
  4146.  
  4147. mas-spdm {
  4148. cell-id = <0x24>;
  4149. label = "mas-spdm";
  4150. qcom,buswidth = <0x4>;
  4151. qcom,agg-ports = <0x1>;
  4152. qcom,ap-owned;
  4153. qcom,connections = <0x79>;
  4154. qcom,bus-dev = <0x7a>;
  4155. qcom,mas-rpm-id = <0x32>;
  4156. };
  4157.  
  4158. mas-blsp-1 {
  4159. cell-id = <0x56>;
  4160. label = "mas-blsp-1";
  4161. qcom,buswidth = <0x4>;
  4162. qcom,agg-ports = <0x1>;
  4163. qcom,connections = <0x7b>;
  4164. qcom,bus-dev = <0x7a>;
  4165. qcom,mas-rpm-id = <0x29>;
  4166. };
  4167.  
  4168. mas-blsp-2 {
  4169. cell-id = <0x54>;
  4170. label = "mas-blsp-2";
  4171. qcom,buswidth = <0x4>;
  4172. qcom,agg-ports = <0x1>;
  4173. qcom,connections = <0x7b>;
  4174. qcom,bus-dev = <0x7a>;
  4175. qcom,mas-rpm-id = <0x27>;
  4176. };
  4177.  
  4178. mas-usb3 {
  4179. cell-id = <0x3d>;
  4180. label = "mas-usb3";
  4181. qcom,buswidth = <0x8>;
  4182. qcom,agg-ports = <0x1>;
  4183. qcom,ap-owned;
  4184. qcom,qport = <0xb>;
  4185. qcom,qos-mode = "fixed";
  4186. qcom,connections = <0x7c>;
  4187. qcom,prio1 = <0x1>;
  4188. qcom,prio0 = <0x1>;
  4189. qcom,bus-dev = <0x7a>;
  4190. qcom,mas-rpm-id = <0x20>;
  4191. };
  4192.  
  4193. mas-crypto {
  4194. cell-id = <0x37>;
  4195. label = "mas-crypto";
  4196. qcom,buswidth = <0x8>;
  4197. qcom,agg-ports = <0x1>;
  4198. qcom,ap-owned;
  4199. qcom,qport = <0x0>;
  4200. qcom,qos-mode = "fixed";
  4201. qcom,connections = <0x7c>;
  4202. qcom,prio1 = <0x1>;
  4203. qcom,prio0 = <0x1>;
  4204. qcom,bus-dev = <0x7a>;
  4205. qcom,mas-rpm-id = <0x17>;
  4206. };
  4207.  
  4208. mas-sdcc-1 {
  4209. cell-id = <0x4e>;
  4210. label = "mas-sdcc-1";
  4211. qcom,buswidth = <0x8>;
  4212. qcom,agg-ports = <0x1>;
  4213. qcom,qport = <0x7>;
  4214. qcom,qos-mode = "fixed";
  4215. qcom,connections = <0x7c>;
  4216. qcom,bus-dev = <0x7a>;
  4217. qcom,mas-rpm-id = <0x21>;
  4218. };
  4219.  
  4220. mas-sdcc-2 {
  4221. cell-id = <0x51>;
  4222. label = "mas-sdcc-2";
  4223. qcom,buswidth = <0x8>;
  4224. qcom,agg-ports = <0x1>;
  4225. qcom,qport = <0x8>;
  4226. qcom,qos-mode = "fixed";
  4227. qcom,connections = <0x7c>;
  4228. qcom,bus-dev = <0x7a>;
  4229. qcom,mas-rpm-id = <0x23>;
  4230. };
  4231.  
  4232. mas-snoc-pcnoc {
  4233. cell-id = <0x2739>;
  4234. label = "mas-snoc-pcnoc";
  4235. qcom,buswidth = <0x8>;
  4236. qcom,agg-ports = <0x1>;
  4237. qcom,qport = <0x9>;
  4238. qcom,qos-mode = "fixed";
  4239. qcom,connections = <0x7d>;
  4240. qcom,bus-dev = <0x7a>;
  4241. qcom,mas-rpm-id = <0x4d>;
  4242. linux,phandle = <0xb2>;
  4243. phandle = <0xb2>;
  4244. };
  4245.  
  4246. mas-qdss-bam {
  4247. cell-id = <0x35>;
  4248. label = "mas-qdss-bam";
  4249. qcom,buswidth = <0x4>;
  4250. qcom,agg-ports = <0x1>;
  4251. qcom,ap-owned;
  4252. qcom,qport = <0xb>;
  4253. qcom,qos-mode = "fixed";
  4254. qcom,connections = <0x7e>;
  4255. qcom,prio1 = <0x1>;
  4256. qcom,prio0 = <0x1>;
  4257. qcom,bus-dev = <0x7f>;
  4258. qcom,mas-rpm-id = <0x13>;
  4259. };
  4260.  
  4261. mas-bimc-snoc {
  4262. cell-id = <0x2720>;
  4263. label = "mas-bimc-snoc";
  4264. qcom,buswidth = <0x8>;
  4265. qcom,agg-ports = <0x1>;
  4266. qcom,connections = <0x80 0x81 0x82>;
  4267. qcom,bus-dev = <0x7f>;
  4268. qcom,mas-rpm-id = <0x15>;
  4269. linux,phandle = <0xad>;
  4270. phandle = <0xad>;
  4271. };
  4272.  
  4273. mas-jpeg {
  4274. cell-id = <0x3e>;
  4275. label = "mas-jpeg";
  4276. qcom,buswidth = <0x10>;
  4277. qcom,agg-ports = <0x1>;
  4278. qcom,ap-owned;
  4279. qcom,qport = <0x6>;
  4280. qcom,qos-mode = "bypass";
  4281. qcom,connections = <0x83>;
  4282. qcom,bus-dev = <0x84>;
  4283. qcom,mas-rpm-id = <0x7>;
  4284. };
  4285.  
  4286. mas-mdp {
  4287. cell-id = <0x16>;
  4288. label = "mas-mdp";
  4289. qcom,buswidth = <0x10>;
  4290. qcom,agg-ports = <0x1>;
  4291. qcom,ap-owned;
  4292. qcom,qport = <0x7>;
  4293. qcom,qos-mode = "bypass";
  4294. qcom,connections = <0x85>;
  4295. qcom,bus-dev = <0x84>;
  4296. qcom,mas-rpm-id = <0x8>;
  4297. };
  4298.  
  4299. mas-pcnoc-snoc {
  4300. cell-id = <0x271a>;
  4301. label = "mas-pcnoc-snoc";
  4302. qcom,buswidth = <0x8>;
  4303. qcom,agg-ports = <0x1>;
  4304. qcom,qport = <0x5>;
  4305. qcom,qos-mode = "fixed";
  4306. qcom,connections = <0x80 0x81 0x86>;
  4307. qcom,bus-dev = <0x7f>;
  4308. qcom,mas-rpm-id = <0x1d>;
  4309. qcom,blacklist = <0x87>;
  4310. linux,phandle = <0xae>;
  4311. phandle = <0xae>;
  4312. };
  4313.  
  4314. mas-venus {
  4315. cell-id = <0x3f>;
  4316. label = "mas-venus";
  4317. qcom,buswidth = <0x10>;
  4318. qcom,agg-ports = <0x1>;
  4319. qcom,ap-owned;
  4320. qcom,qport = <0x8>;
  4321. qcom,qos-mode = "bypass";
  4322. qcom,connections = <0x83>;
  4323. qcom,bus-dev = <0x84>;
  4324. qcom,mas-rpm-id = <0x9>;
  4325. };
  4326.  
  4327. mas-vfe0 {
  4328. cell-id = <0x1d>;
  4329. label = "mas-vfe0";
  4330. qcom,buswidth = <0x10>;
  4331. qcom,agg-ports = <0x1>;
  4332. qcom,ap-owned;
  4333. qcom,qport = <0x9>;
  4334. qcom,qos-mode = "bypass";
  4335. qcom,connections = <0x85>;
  4336. qcom,bus-dev = <0x84>;
  4337. qcom,mas-rpm-id = <0xb>;
  4338. };
  4339.  
  4340. mas-vfe1 {
  4341. cell-id = <0x6d>;
  4342. label = "mas-vfe1";
  4343. qcom,buswidth = <0x10>;
  4344. qcom,agg-ports = <0x1>;
  4345. qcom,ap-owned;
  4346. qcom,qport = <0xd>;
  4347. qcom,qos-mode = "bypass";
  4348. qcom,connections = <0x85>;
  4349. qcom,bus-dev = <0x84>;
  4350. qcom,mas-rpm-id = <0x85>;
  4351. };
  4352.  
  4353. mas-cpp {
  4354. cell-id = <0x6a>;
  4355. label = "mas-cpp";
  4356. qcom,buswidth = <0x10>;
  4357. qcom,agg-ports = <0x1>;
  4358. qcom,ap-owned;
  4359. qcom,qport = <0xc>;
  4360. qcom,qos-mode = "bypass";
  4361. qcom,connections = <0x83>;
  4362. qcom,bus-dev = <0x84>;
  4363. qcom,mas-rpm-id = <0x73>;
  4364. };
  4365.  
  4366. mas-ipa {
  4367. cell-id = <0x5a>;
  4368. label = "mas-ipa";
  4369. qcom,buswidth = <0x8>;
  4370. qcom,agg-ports = <0x1>;
  4371. qcom,ap-owned;
  4372. qcom,qport = <0xe>;
  4373. qcom,qos-mode = "fixed";
  4374. qcom,connections = <0x80 0x81 0x86>;
  4375. qcom,prio1 = <0x0>;
  4376. qcom,prio0 = <0x0>;
  4377. qcom,bus-dev = <0x7f>;
  4378. qcom,mas-rpm-id = <0x3b>;
  4379. };
  4380.  
  4381. mas-qdss-etr {
  4382. cell-id = <0x3c>;
  4383. label = "mas-qdss-etr";
  4384. qcom,buswidth = <0x8>;
  4385. qcom,agg-ports = <0x1>;
  4386. qcom,ap-owned;
  4387. qcom,qport = <0xa>;
  4388. qcom,qos-mode = "fixed";
  4389. qcom,connections = <0x7e>;
  4390. qcom,prio1 = <0x1>;
  4391. qcom,prio0 = <0x1>;
  4392. qcom,bus-dev = <0x7f>;
  4393. qcom,mas-rpm-id = <0x1f>;
  4394. };
  4395.  
  4396. pcnoc-m-0 {
  4397. cell-id = <0x271e>;
  4398. label = "pcnoc-m-0";
  4399. qcom,buswidth = <0x4>;
  4400. qcom,agg-ports = <0x1>;
  4401. qcom,ap-owned;
  4402. qcom,qport = <0x5>;
  4403. qcom,qos-mode = "fixed";
  4404. qcom,connections = <0x7c>;
  4405. qcom,prio1 = <0x1>;
  4406. qcom,prio0 = <0x1>;
  4407. qcom,bus-dev = <0x7a>;
  4408. qcom,mas-rpm-id = <0x57>;
  4409. qcom,slv-rpm-id = <0x74>;
  4410. linux,phandle = <0x79>;
  4411. phandle = <0x79>;
  4412. };
  4413.  
  4414. pcnoc-m-1 {
  4415. cell-id = <0x271f>;
  4416. label = "pcnoc-m-1";
  4417. qcom,buswidth = <0x4>;
  4418. qcom,agg-ports = <0x1>;
  4419. qcom,qport = <0x6>;
  4420. qcom,qos-mode = "fixed";
  4421. qcom,connections = <0x7c>;
  4422. qcom,bus-dev = <0x7a>;
  4423. qcom,mas-rpm-id = <0x58>;
  4424. qcom,slv-rpm-id = <0x75>;
  4425. linux,phandle = <0x7b>;
  4426. phandle = <0x7b>;
  4427. };
  4428.  
  4429. pcnoc-int-1 {
  4430. cell-id = <0x271d>;
  4431. label = "pcnoc-int-1";
  4432. qcom,buswidth = <0x8>;
  4433. qcom,agg-ports = <0x1>;
  4434. qcom,connections = <0x7d 0x88>;
  4435. qcom,bus-dev = <0x7a>;
  4436. qcom,mas-rpm-id = <0x56>;
  4437. qcom,slv-rpm-id = <0x73>;
  4438. linux,phandle = <0x7c>;
  4439. phandle = <0x7c>;
  4440. };
  4441.  
  4442. pcnoc-int-2 {
  4443. cell-id = <0x2741>;
  4444. label = "pcnoc-int-2";
  4445. qcom,buswidth = <0x8>;
  4446. qcom,agg-ports = <0x1>;
  4447. qcom,connections = <0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90 0x91 0x92 0x93>;
  4448. qcom,bus-dev = <0x7a>;
  4449. qcom,mas-rpm-id = <0x7c>;
  4450. qcom,slv-rpm-id = <0xb8>;
  4451. linux,phandle = <0x7d>;
  4452. phandle = <0x7d>;
  4453. };
  4454.  
  4455. pcnoc-s-0 {
  4456. cell-id = <0x2722>;
  4457. label = "pcnoc-s-0";
  4458. qcom,buswidth = <0x4>;
  4459. qcom,agg-ports = <0x1>;
  4460. qcom,connections = <0x94 0x95>;
  4461. qcom,bus-dev = <0x7a>;
  4462. qcom,mas-rpm-id = <0x59>;
  4463. qcom,slv-rpm-id = <0x76>;
  4464. linux,phandle = <0x8b>;
  4465. phandle = <0x8b>;
  4466. };
  4467.  
  4468. pcnoc-s-1 {
  4469. cell-id = <0x2723>;
  4470. label = "pcnoc-s-1";
  4471. qcom,buswidth = <0x4>;
  4472. qcom,agg-ports = <0x1>;
  4473. qcom,connections = <0x96>;
  4474. qcom,bus-dev = <0x7a>;
  4475. qcom,mas-rpm-id = <0x5a>;
  4476. qcom,slv-rpm-id = <0x77>;
  4477. linux,phandle = <0x89>;
  4478. phandle = <0x89>;
  4479. };
  4480.  
  4481. pcnoc-s-2 {
  4482. cell-id = <0x2724>;
  4483. label = "pcnoc-s-2";
  4484. qcom,buswidth = <0x4>;
  4485. qcom,agg-ports = <0x1>;
  4486. qcom,connections = <0x97>;
  4487. qcom,bus-dev = <0x7a>;
  4488. qcom,mas-rpm-id = <0x5b>;
  4489. qcom,slv-rpm-id = <0x78>;
  4490. linux,phandle = <0x8a>;
  4491. phandle = <0x8a>;
  4492. };
  4493.  
  4494. pcnoc-s-3 {
  4495. cell-id = <0x2725>;
  4496. label = "pcnoc-s-3";
  4497. qcom,buswidth = <0x4>;
  4498. qcom,agg-ports = <0x1>;
  4499. qcom,connections = <0x98 0x99 0x9a 0x9b 0x9c>;
  4500. qcom,bus-dev = <0x7a>;
  4501. qcom,mas-rpm-id = <0x5c>;
  4502. qcom,slv-rpm-id = <0x79>;
  4503. linux,phandle = <0x93>;
  4504. phandle = <0x93>;
  4505. };
  4506.  
  4507. pcnoc-s-4 {
  4508. cell-id = <0x2726>;
  4509. label = "pcnoc-s-4";
  4510. qcom,buswidth = <0x4>;
  4511. qcom,agg-ports = <0x1>;
  4512. qcom,ap-owned;
  4513. qcom,connections = <0x9d 0x9e 0x9f>;
  4514. qcom,bus-dev = <0x7a>;
  4515. qcom,mas-rpm-id = <0x5d>;
  4516. qcom,slv-rpm-id = <0x7a>;
  4517. linux,phandle = <0x8c>;
  4518. phandle = <0x8c>;
  4519. };
  4520.  
  4521. pcnoc-s-6 {
  4522. cell-id = <0x2d1>;
  4523. label = "pcnoc-s-6";
  4524. qcom,buswidth = <0x4>;
  4525. qcom,agg-ports = <0x1>;
  4526. qcom,connections = <0xa0 0xa1 0xa2>;
  4527. qcom,bus-dev = <0x7a>;
  4528. qcom,mas-rpm-id = <0x5e>;
  4529. qcom,slv-rpm-id = <0x7b>;
  4530. linux,phandle = <0x8d>;
  4531. phandle = <0x8d>;
  4532. };
  4533.  
  4534. pcnoc-s-7 {
  4535. cell-id = <0x2740>;
  4536. label = "pcnoc-s-7";
  4537. qcom,buswidth = <0x4>;
  4538. qcom,agg-ports = <0x1>;
  4539. qcom,connections = <0xa3>;
  4540. qcom,bus-dev = <0x7a>;
  4541. qcom,mas-rpm-id = <0x5f>;
  4542. qcom,slv-rpm-id = <0x7c>;
  4543. linux,phandle = <0x8e>;
  4544. phandle = <0x8e>;
  4545. };
  4546.  
  4547. pcnoc-s-8 {
  4548. cell-id = <0x2727>;
  4549. label = "pcnoc-s-8";
  4550. qcom,buswidth = <0x4>;
  4551. qcom,agg-ports = <0x1>;
  4552. qcom,ap-owned;
  4553. qcom,connections = <0xa4>;
  4554. qcom,bus-dev = <0x7a>;
  4555. qcom,mas-rpm-id = <0x60>;
  4556. qcom,slv-rpm-id = <0x7d>;
  4557. linux,phandle = <0x8f>;
  4558. phandle = <0x8f>;
  4559. };
  4560.  
  4561. pcnoc-s-9 {
  4562. cell-id = <0x2728>;
  4563. label = "pcnoc-s-9";
  4564. qcom,buswidth = <0x4>;
  4565. qcom,agg-ports = <0x1>;
  4566. qcom,ap-owned;
  4567. qcom,connections = <0xa5>;
  4568. qcom,bus-dev = <0x7a>;
  4569. qcom,mas-rpm-id = <0x61>;
  4570. qcom,slv-rpm-id = <0x7e>;
  4571. linux,phandle = <0x90>;
  4572. phandle = <0x90>;
  4573. };
  4574.  
  4575. qdss-int {
  4576. cell-id = <0x2719>;
  4577. label = "qdss-int";
  4578. qcom,buswidth = <0x8>;
  4579. qcom,agg-ports = <0x1>;
  4580. qcom,ap-owned;
  4581. qcom,connections = <0x81 0x86>;
  4582. qcom,bus-dev = <0x7f>;
  4583. qcom,mas-rpm-id = <0x62>;
  4584. qcom,slv-rpm-id = <0x80>;
  4585. linux,phandle = <0x7e>;
  4586. phandle = <0x7e>;
  4587. };
  4588.  
  4589. snoc-int-0 {
  4590. cell-id = <0x2714>;
  4591. label = "snoc-int-0";
  4592. qcom,buswidth = <0x8>;
  4593. qcom,agg-ports = <0x1>;
  4594. qcom,ap-owned;
  4595. qcom,connections = <0xa6 0xa7 0xa8>;
  4596. qcom,bus-dev = <0x7f>;
  4597. qcom,mas-rpm-id = <0x63>;
  4598. qcom,slv-rpm-id = <0x82>;
  4599. linux,phandle = <0x80>;
  4600. phandle = <0x80>;
  4601. };
  4602.  
  4603. snoc-int-1 {
  4604. cell-id = <0x2715>;
  4605. label = "snoc-int-1";
  4606. qcom,buswidth = <0x8>;
  4607. qcom,agg-ports = <0x1>;
  4608. qcom,connections = <0xa9 0xaa 0x87>;
  4609. qcom,bus-dev = <0x7f>;
  4610. qcom,mas-rpm-id = <0x64>;
  4611. qcom,slv-rpm-id = <0x83>;
  4612. linux,phandle = <0x81>;
  4613. phandle = <0x81>;
  4614. };
  4615.  
  4616. snoc-int-2 {
  4617. cell-id = <0x2752>;
  4618. label = "snoc-int-2";
  4619. qcom,buswidth = <0x8>;
  4620. qcom,agg-ports = <0x1>;
  4621. qcom,ap-owned;
  4622. qcom,connections = <0xab 0xac>;
  4623. qcom,bus-dev = <0x7f>;
  4624. qcom,mas-rpm-id = <0x86>;
  4625. qcom,slv-rpm-id = <0xc5>;
  4626. linux,phandle = <0x82>;
  4627. phandle = <0x82>;
  4628. };
  4629.  
  4630. slv-ebi {
  4631. cell-id = <0x200>;
  4632. label = "slv-ebi";
  4633. qcom,buswidth = <0x8>;
  4634. qcom,agg-ports = <0x1>;
  4635. qcom,bus-dev = <0x78>;
  4636. qcom,slv-rpm-id = <0x0>;
  4637. linux,phandle = <0x76>;
  4638. phandle = <0x76>;
  4639. };
  4640.  
  4641. slv-bimc-snoc {
  4642. cell-id = <0x2721>;
  4643. label = "slv-bimc-snoc";
  4644. qcom,buswidth = <0x8>;
  4645. qcom,agg-ports = <0x1>;
  4646. qcom,bus-dev = <0x78>;
  4647. qcom,connections = <0xad>;
  4648. qcom,slv-rpm-id = <0x2>;
  4649. linux,phandle = <0x77>;
  4650. phandle = <0x77>;
  4651. };
  4652.  
  4653. slv-spdm {
  4654. cell-id = <0x279>;
  4655. label = "slv-spdm";
  4656. qcom,buswidth = <0x4>;
  4657. qcom,agg-ports = <0x1>;
  4658. qcom,ap-owned;
  4659. qcom,bus-dev = <0x7a>;
  4660. qcom,slv-rpm-id = <0x3c>;
  4661. linux,phandle = <0x95>;
  4662. phandle = <0x95>;
  4663. };
  4664.  
  4665. slv-pdm {
  4666. cell-id = <0x267>;
  4667. label = "slv-pdm";
  4668. qcom,buswidth = <0x4>;
  4669. qcom,agg-ports = <0x1>;
  4670. qcom,bus-dev = <0x7a>;
  4671. qcom,slv-rpm-id = <0x29>;
  4672. linux,phandle = <0x94>;
  4673. phandle = <0x94>;
  4674. };
  4675.  
  4676. slv-tcsr {
  4677. cell-id = <0x26f>;
  4678. label = "slv-tcsr";
  4679. qcom,buswidth = <0x4>;
  4680. qcom,agg-ports = <0x1>;
  4681. qcom,bus-dev = <0x7a>;
  4682. qcom,slv-rpm-id = <0x32>;
  4683. linux,phandle = <0x96>;
  4684. phandle = <0x96>;
  4685. };
  4686.  
  4687. slv-snoc-cfg {
  4688. cell-id = <0x282>;
  4689. label = "slv-snoc-cfg";
  4690. qcom,buswidth = <0x4>;
  4691. qcom,agg-ports = <0x1>;
  4692. qcom,bus-dev = <0x7a>;
  4693. qcom,slv-rpm-id = <0x46>;
  4694. linux,phandle = <0x97>;
  4695. phandle = <0x97>;
  4696. };
  4697.  
  4698. slv-tlmm {
  4699. cell-id = <0x270>;
  4700. label = "slv-tlmm";
  4701. qcom,buswidth = <0x4>;
  4702. qcom,agg-ports = <0x1>;
  4703. qcom,bus-dev = <0x7a>;
  4704. qcom,slv-rpm-id = <0x33>;
  4705. linux,phandle = <0x98>;
  4706. phandle = <0x98>;
  4707. };
  4708.  
  4709. slv-message-ram {
  4710. cell-id = <0x274>;
  4711. label = "slv-message-ram";
  4712. qcom,buswidth = <0x4>;
  4713. qcom,agg-ports = <0x1>;
  4714. qcom,bus-dev = <0x7a>;
  4715. qcom,slv-rpm-id = <0x37>;
  4716. linux,phandle = <0x9c>;
  4717. phandle = <0x9c>;
  4718. };
  4719.  
  4720. slv-blsp-1 {
  4721. cell-id = <0x265>;
  4722. label = "slv-blsp-1";
  4723. qcom,buswidth = <0x4>;
  4724. qcom,agg-ports = <0x1>;
  4725. qcom,bus-dev = <0x7a>;
  4726. qcom,slv-rpm-id = <0x27>;
  4727. linux,phandle = <0x9a>;
  4728. phandle = <0x9a>;
  4729. };
  4730.  
  4731. slv-blsp-2 {
  4732. cell-id = <0x263>;
  4733. label = "slv-blsp-2";
  4734. qcom,buswidth = <0x4>;
  4735. qcom,agg-ports = <0x1>;
  4736. qcom,bus-dev = <0x7a>;
  4737. qcom,slv-rpm-id = <0x25>;
  4738. linux,phandle = <0x9b>;
  4739. phandle = <0x9b>;
  4740. };
  4741.  
  4742. slv-prng {
  4743. cell-id = <0x26a>;
  4744. label = "slv-prng";
  4745. qcom,buswidth = <0x4>;
  4746. qcom,agg-ports = <0x1>;
  4747. qcom,bus-dev = <0x7a>;
  4748. qcom,slv-rpm-id = <0x2c>;
  4749. linux,phandle = <0x99>;
  4750. phandle = <0x99>;
  4751. };
  4752.  
  4753. slv-camera-ss-cfg {
  4754. cell-id = <0x24d>;
  4755. label = "slv-camera-ss-cfg";
  4756. qcom,buswidth = <0x4>;
  4757. qcom,agg-ports = <0x1>;
  4758. qcom,ap-owned;
  4759. qcom,bus-dev = <0x7a>;
  4760. qcom,slv-rpm-id = <0x3>;
  4761. linux,phandle = <0x9d>;
  4762. phandle = <0x9d>;
  4763. };
  4764.  
  4765. slv-disp-ss-cfg {
  4766. cell-id = <0x24e>;
  4767. label = "slv-disp-ss-cfg";
  4768. qcom,buswidth = <0x4>;
  4769. qcom,agg-ports = <0x1>;
  4770. qcom,ap-owned;
  4771. qcom,bus-dev = <0x7a>;
  4772. qcom,slv-rpm-id = <0x4>;
  4773. linux,phandle = <0x9e>;
  4774. phandle = <0x9e>;
  4775. };
  4776.  
  4777. slv-venus-cfg {
  4778. cell-id = <0x254>;
  4779. label = "slv-venus-cfg";
  4780. qcom,buswidth = <0x4>;
  4781. qcom,agg-ports = <0x1>;
  4782. qcom,ap-owned;
  4783. qcom,bus-dev = <0x7a>;
  4784. qcom,slv-rpm-id = <0xa>;
  4785. linux,phandle = <0x9f>;
  4786. phandle = <0x9f>;
  4787. };
  4788.  
  4789. slv-gpu-cfg {
  4790. cell-id = <0x256>;
  4791. label = "slv-gpu-cfg";
  4792. qcom,buswidth = <0x8>;
  4793. qcom,agg-ports = <0x1>;
  4794. qcom,ap-owned;
  4795. qcom,bus-dev = <0x7a>;
  4796. qcom,slv-rpm-id = <0xb>;
  4797. linux,phandle = <0x92>;
  4798. phandle = <0x92>;
  4799. };
  4800.  
  4801. slv-sdcc-1 {
  4802. cell-id = <0x25e>;
  4803. label = "slv-sdcc-1";
  4804. qcom,buswidth = <0x4>;
  4805. qcom,agg-ports = <0x1>;
  4806. qcom,bus-dev = <0x7a>;
  4807. qcom,slv-rpm-id = <0x1f>;
  4808. linux,phandle = <0xa2>;
  4809. phandle = <0xa2>;
  4810. };
  4811.  
  4812. slv-sdcc-2 {
  4813. cell-id = <0x260>;
  4814. label = "slv-sdcc-2";
  4815. qcom,buswidth = <0x4>;
  4816. qcom,agg-ports = <0x1>;
  4817. qcom,bus-dev = <0x7a>;
  4818. qcom,slv-rpm-id = <0x21>;
  4819. linux,phandle = <0xa1>;
  4820. phandle = <0xa1>;
  4821. };
  4822.  
  4823. slv-crypto-0-cfg {
  4824. cell-id = <0x271>;
  4825. label = "slv-crypto-0-cfg";
  4826. qcom,buswidth = <0x4>;
  4827. qcom,agg-ports = <0x1>;
  4828. qcom,ap-owned;
  4829. qcom,bus-dev = <0x7a>;
  4830. qcom,slv-rpm-id = <0x34>;
  4831. linux,phandle = <0xa0>;
  4832. phandle = <0xa0>;
  4833. };
  4834.  
  4835. slv-pmic-arb {
  4836. cell-id = <0x278>;
  4837. label = "slv-pmic-arb";
  4838. qcom,buswidth = <0x4>;
  4839. qcom,agg-ports = <0x1>;
  4840. qcom,bus-dev = <0x7a>;
  4841. qcom,slv-rpm-id = <0x3b>;
  4842. linux,phandle = <0xa3>;
  4843. phandle = <0xa3>;
  4844. };
  4845.  
  4846. slv-usb3 {
  4847. cell-id = <0x247>;
  4848. label = "slv-usb3";
  4849. qcom,buswidth = <0x4>;
  4850. qcom,agg-ports = <0x1>;
  4851. qcom,ap-owned;
  4852. qcom,bus-dev = <0x7a>;
  4853. qcom,slv-rpm-id = <0x16>;
  4854. linux,phandle = <0xa4>;
  4855. phandle = <0xa4>;
  4856. };
  4857.  
  4858. slv-ipa-cfg {
  4859. cell-id = <0x2a4>;
  4860. label = "slv-ipa-cfg";
  4861. qcom,buswidth = <0x4>;
  4862. qcom,agg-ports = <0x1>;
  4863. qcom,ap-owned;
  4864. qcom,bus-dev = <0x7a>;
  4865. qcom,slv-rpm-id = <0xb7>;
  4866. linux,phandle = <0xa5>;
  4867. phandle = <0xa5>;
  4868. };
  4869.  
  4870. slv-tcu {
  4871. cell-id = <0x2a0>;
  4872. label = "slv-tcu";
  4873. qcom,buswidth = <0x8>;
  4874. qcom,agg-ports = <0x1>;
  4875. qcom,ap-owned;
  4876. qcom,bus-dev = <0x7a>;
  4877. qcom,slv-rpm-id = <0x85>;
  4878. linux,phandle = <0x91>;
  4879. phandle = <0x91>;
  4880. };
  4881.  
  4882. slv-pcnoc-snoc {
  4883. cell-id = <0x271b>;
  4884. label = "slv-pcnoc-snoc";
  4885. qcom,buswidth = <0x8>;
  4886. qcom,agg-ports = <0x1>;
  4887. qcom,bus-dev = <0x7a>;
  4888. qcom,connections = <0xae>;
  4889. qcom,slv-rpm-id = <0x2d>;
  4890. linux,phandle = <0x88>;
  4891. phandle = <0x88>;
  4892. };
  4893.  
  4894. slv-kpss-ahb {
  4895. cell-id = <0x2a1>;
  4896. label = "slv-kpss-ahb";
  4897. qcom,buswidth = <0x4>;
  4898. qcom,agg-ports = <0x1>;
  4899. qcom,ap-owned;
  4900. qcom,bus-dev = <0x7f>;
  4901. qcom,slv-rpm-id = <0x14>;
  4902. linux,phandle = <0xa8>;
  4903. phandle = <0xa8>;
  4904. };
  4905.  
  4906. slv-wcss {
  4907. cell-id = <0x248>;
  4908. label = "slv-wcss";
  4909. qcom,buswidth = <0x4>;
  4910. qcom,agg-ports = <0x1>;
  4911. qcom,ap-owned;
  4912. qcom,bus-dev = <0x7f>;
  4913. qcom,slv-rpm-id = <0x17>;
  4914. linux,phandle = <0xa7>;
  4915. phandle = <0xa7>;
  4916. };
  4917.  
  4918. slv-snoc-bimc-0 {
  4919. cell-id = <0x2729>;
  4920. label = "slv-snoc-bimc-0";
  4921. qcom,buswidth = <0x10>;
  4922. qcom,agg-ports = <0x1>;
  4923. qcom,ap-owned;
  4924. qcom,bus-dev = <0x84>;
  4925. qcom,connections = <0xaf>;
  4926. qcom,slv-rpm-id = <0x18>;
  4927. linux,phandle = <0x85>;
  4928. phandle = <0x85>;
  4929. };
  4930.  
  4931. slv-snoc-bimc-1 {
  4932. cell-id = <0x272a>;
  4933. label = "slv-snoc-bimc-1";
  4934. qcom,buswidth = <0x8>;
  4935. qcom,agg-ports = <0x1>;
  4936. qcom,bus-dev = <0x7f>;
  4937. qcom,connections = <0xb0>;
  4938. qcom,slv-rpm-id = <0x68>;
  4939. linux,phandle = <0x86>;
  4940. phandle = <0x86>;
  4941. };
  4942.  
  4943. slv-snoc-bimc-2 {
  4944. cell-id = <0x273e>;
  4945. label = "slv-snoc-bimc-2";
  4946. qcom,buswidth = <0x10>;
  4947. qcom,agg-ports = <0x1>;
  4948. qcom,ap-owned;
  4949. qcom,bus-dev = <0x84>;
  4950. qcom,connections = <0xb1>;
  4951. qcom,slv-rpm-id = <0x89>;
  4952. linux,phandle = <0x83>;
  4953. phandle = <0x83>;
  4954. };
  4955.  
  4956. slv-imem {
  4957. cell-id = <0x249>;
  4958. label = "slv-imem";
  4959. qcom,buswidth = <0x8>;
  4960. qcom,agg-ports = <0x1>;
  4961. qcom,bus-dev = <0x7f>;
  4962. qcom,slv-rpm-id = <0x1a>;
  4963. linux,phandle = <0xaa>;
  4964. phandle = <0xaa>;
  4965. };
  4966.  
  4967. slv-snoc-pcnoc {
  4968. cell-id = <0x273a>;
  4969. label = "slv-snoc-pcnoc";
  4970. qcom,buswidth = <0x8>;
  4971. qcom,agg-ports = <0x1>;
  4972. qcom,bus-dev = <0x7f>;
  4973. qcom,connections = <0xb2>;
  4974. qcom,slv-rpm-id = <0x1c>;
  4975. linux,phandle = <0x87>;
  4976. phandle = <0x87>;
  4977. };
  4978.  
  4979. slv-qdss-stm {
  4980. cell-id = <0x24c>;
  4981. label = "slv-qdss-stm";
  4982. qcom,buswidth = <0x4>;
  4983. qcom,agg-ports = <0x1>;
  4984. qcom,bus-dev = <0x7f>;
  4985. qcom,slv-rpm-id = <0x1e>;
  4986. linux,phandle = <0xa9>;
  4987. phandle = <0xa9>;
  4988. };
  4989.  
  4990. slv-cats-0 {
  4991. cell-id = <0x297>;
  4992. label = "slv-cats-0";
  4993. qcom,buswidth = <0x10>;
  4994. qcom,agg-ports = <0x1>;
  4995. qcom,ap-owned;
  4996. qcom,bus-dev = <0x84>;
  4997. qcom,slv-rpm-id = <0x6a>;
  4998. linux,phandle = <0xab>;
  4999. phandle = <0xab>;
  5000. };
  5001.  
  5002. slv-cats-1 {
  5003. cell-id = <0x298>;
  5004. label = "slv-cats-1";
  5005. qcom,buswidth = <0x8>;
  5006. qcom,agg-ports = <0x1>;
  5007. qcom,ap-owned;
  5008. qcom,bus-dev = <0x7f>;
  5009. qcom,slv-rpm-id = <0x6b>;
  5010. linux,phandle = <0xac>;
  5011. phandle = <0xac>;
  5012. };
  5013.  
  5014. slv-lpass {
  5015. cell-id = <0x20a>;
  5016. label = "slv-lpass";
  5017. qcom,buswidth = <0x4>;
  5018. qcom,agg-ports = <0x1>;
  5019. qcom,ap-owned;
  5020. qcom,bus-dev = <0x7f>;
  5021. qcom,slv-rpm-id = <0x15>;
  5022. linux,phandle = <0xa6>;
  5023. phandle = <0xa6>;
  5024. };
  5025. };
  5026.  
  5027. devfreq_spdm_cpu {
  5028. compatible = "qcom,devfreq_spdm";
  5029. qcom,msm-bus,name = "devfreq_spdm";
  5030. qcom,msm-bus,num-cases = <0x2>;
  5031. qcom,msm-bus,num-paths = <0x1>;
  5032. qcom,msm-bus,vectors-KBps = <0x1 0x200 0x0 0x0 0x1 0x200 0x0 0x0>;
  5033. qcom,msm-bus,active-only;
  5034. qcom,spdm-client = <0x0>;
  5035. clock-names = "cci_clk";
  5036. clocks = <0xb3 0x96854074>;
  5037. qcom,bw-upstep = <0x190>;
  5038. qcom,bw-dwnstep = <0x1068>;
  5039. qcom,max-vote = <0x1068>;
  5040. qcom,up-step-multp = <0x2>;
  5041. qcom,spdm-interval = <0x1e>;
  5042. qcom,ports = <0xb>;
  5043. qcom,alpha-up = <0x8>;
  5044. qcom,alpha-down = <0xf>;
  5045. qcom,bucket-size = <0x8>;
  5046. qcom,pl-freqs = <0x38270 0xbbfd0>;
  5047. qcom,reject-rate = <0x1388 0x1388 0x1388 0x1388 0x1388 0x1388>;
  5048. qcom,response-time-us = <0x1770 0x1770 0xfa0 0xfa0 0x7d0 0x7d0>;
  5049. qcom,cci-response-time-us = <0xfa0 0xfa0 0xbb8 0xbb8 0x7d0 0x7d0>;
  5050. qcom,max-cci-freq = <0xd4670>;
  5051. };
  5052.  
  5053. devfreq_spdm_gov {
  5054. compatible = "qcom,gov_spdm_hyp";
  5055. interrupt-names = "spdm-irq";
  5056. interrupts = <0x0 0xc0 0x0>;
  5057. };
  5058.  
  5059. qcom,iommu-domains {
  5060. compatible = "qcom,iommu-domains";
  5061.  
  5062. qcom,iommu-domain2 {
  5063. label = "venus_ns";
  5064. qcom,iommu-contexts = <0xb4>;
  5065. qcom,virtual-addr-pool = <0x5dc00000 0x7f000000 0xdcc00000 0x1000000>;
  5066. linux,phandle = <0xba>;
  5067. phandle = <0xba>;
  5068. };
  5069.  
  5070. qcom,iommu-domain3 {
  5071. label = "venus_sec_bitstream";
  5072. qcom,iommu-contexts = <0xb5>;
  5073. qcom,virtual-addr-pool = <0x4b000000 0x12c00000>;
  5074. qcom,secure-domain;
  5075. linux,phandle = <0xbb>;
  5076. phandle = <0xbb>;
  5077. };
  5078.  
  5079. qcom,iommu-domain4 {
  5080. label = "venus_sec_pixel";
  5081. qcom,iommu-contexts = <0xb6>;
  5082. qcom,virtual-addr-pool = <0x25800000 0x25800000>;
  5083. qcom,secure-domain;
  5084. linux,phandle = <0xbc>;
  5085. phandle = <0xbc>;
  5086. };
  5087.  
  5088. qcom,iommu-domain5 {
  5089. label = "venus_sec_non_pixel";
  5090. qcom,iommu-contexts = <0xb7>;
  5091. qcom,virtual-addr-pool = <0x1000000 0x24800000>;
  5092. qcom,secure-domain;
  5093. linux,phandle = <0xbd>;
  5094. phandle = <0xbd>;
  5095. };
  5096. };
  5097.  
  5098. qcom,vidc@1d00000 {
  5099. compatible = "qcom,msm-vidc";
  5100. reg = <0x1d00000 0xff000 0xa4124 0x4>;
  5101. reg-names = "vidc", "efuse";
  5102. qcom,platform-version = <0x180000 0x13>;
  5103. interrupts = <0x0 0x2c 0x0>;
  5104. venus-supply = <0xb8>;
  5105. venus-core0-supply = <0xb9>;
  5106. clocks = <0x37 0xf76a02bb 0x37 0x83a7f549 0x37 0x8d778c6 0x37 0xcdf4c8f6>;
  5107. clock-names = "core_clk", "core0_clk", "iface_clk", "bus_clk";
  5108. qcom,clock-configs = <0x1 0x0 0x0 0x0 0x0>;
  5109. qcom,hfi = "venus";
  5110. qcom,hfi-version = "3xx";
  5111. qcom,reg-presets = <0xe0020 0x5555556 0xe0024 0x5555556 0x80124 0x3>;
  5112. qcom,qdss-presets = <0x825000 0x1000 0x826000 0x1000 0x821000 0x1000 0x802000 0x1000 0x9180000 0x1000 0x9181000 0x1000>;
  5113. qcom,max-hw-load = <0xff000>;
  5114. qcom,slave-side-cp;
  5115. qcom,sw-power-collapse;
  5116. qcom,firmware-name = "venus";
  5117. qcom,pm-qos-latency-us = <0xd5>;
  5118. qcom,dcvs-tbl = <0xc7380 0xc7380 0xef100 0x3f00000c 0xdb240 0xc876c 0xef100 0x4000004 0xc7380 0xafc80 0xcc000 0x4000004>;
  5119. qcom,dcvs-limit = <0x7e90 0x18 0x7e90 0x18>;
  5120. qcom,allowed-clock-rates = <0x1bb75640 0x17d78400 0x15752a00 0x127a3980 0xd9fb390 0x6cfed50>;
  5121.  
  5122. qcom,clock-freq-tbl {
  5123.  
  5124. qcom,profile-enc {
  5125. qcom,codec-mask = <0x55555555>;
  5126. qcom,cycles-per-mb = <0x35f>;
  5127. qcom,low-power-mode-factor = <0x8b20>;
  5128. };
  5129.  
  5130. qcom,profile-dec {
  5131. qcom,codec-mask = <0xf3ffffff>;
  5132. qcom,cycles-per-mb = <0x163>;
  5133. };
  5134.  
  5135. qcom,profile-hevcdec {
  5136. qcom,codec-mask = <0xc000000>;
  5137. qcom,cycles-per-mb = <0x190>;
  5138. };
  5139. };
  5140.  
  5141. qcom,vidc-iommu-domains {
  5142.  
  5143. qcom,domain-ns {
  5144. qcom,vidc-domain-phandle = <0xba>;
  5145. qcom,vidc-buffer-types = <0xfff>;
  5146. };
  5147.  
  5148. qcom,domain-sec-bs {
  5149. qcom,vidc-domain-phandle = <0xbb>;
  5150. qcom,vidc-buffer-types = <0x241>;
  5151. };
  5152.  
  5153. qcom,domain-sec-px {
  5154. qcom,vidc-domain-phandle = <0xbc>;
  5155. qcom,vidc-buffer-types = <0x106>;
  5156. };
  5157.  
  5158. qcom,domain-sec-np {
  5159. qcom,vidc-domain-phandle = <0xbd>;
  5160. qcom,vidc-buffer-types = <0x480>;
  5161. };
  5162. };
  5163.  
  5164. venus_bus_ddr {
  5165. compatible = "qcom,msm-vidc,bus";
  5166. label = "venus-ddr";
  5167. qcom,bus-master = <0x3f>;
  5168. qcom,bus-slave = <0x200>;
  5169. qcom,bus-governor = "venus-ddr-gov";
  5170. qcom,bus-range-kbps = <0x3e8 0x241648>;
  5171. };
  5172.  
  5173. arm9_bus_ddr {
  5174. compatible = "qcom,msm-vidc,bus";
  5175. label = "venus-arm9-ddr";
  5176. qcom,bus-master = <0x3f>;
  5177. qcom,bus-slave = <0x200>;
  5178. qcom,bus-governor = "performance";
  5179. qcom,bus-range-kbps = <0x1 0x1>;
  5180. };
  5181. };
  5182.  
  5183. venus-ddr-gov {
  5184. compatible = "qcom,msm-vidc,governor,table";
  5185. status = "ok";
  5186.  
  5187. qcom,bus-freq-table {
  5188.  
  5189. qcom,profile-enc {
  5190. qcom,codec-mask = <0x55555555>;
  5191. qcom,load-busfreq-tbl = <0xef100 0xfee20 0xd2f00 0xd88d8 0x77880 0xa2990 0x69780 0x8d1d0 0x3bc40 0x54790 0x34bc0 0x47888 0x1a5e0 0x24dd8 0x0 0x0>;
  5192. };
  5193.  
  5194. qcom,profile-dec {
  5195. qcom,codec-mask = <0xffffffff>;
  5196. qcom,load-busfreq-tbl = <0xef100 0x241648 0xd2f00 0x1e2e90 0x77880 0x1149c8 0x69780 0xf2ad0 0x3bc40 0x8d9a0 0x34bc0 0x7a508 0x1a5e0 0x3e418 0x0 0x0>;
  5197. };
  5198.  
  5199. qcom,profile-dec-ubwc {
  5200. qcom,codec-mask = <0xffffffff>;
  5201. qcom,ubwc-mode;
  5202. qcom,load-busfreq-tbl = <0xef100 0x1cdea0 0xd2f00 0x17b650 0x77880 0xda818 0x69780 0xbeac8 0x3bc40 0x704e0 0x34bc0 0x497c8 0x1a5e0 0x31510 0x0 0x0>;
  5203. };
  5204. };
  5205. };
  5206.  
  5207. qcom,spm@b1d2000 {
  5208. compatible = "qcom,spm-v2";
  5209. #address-cells = <0x1>;
  5210. #size-cells = <0x1>;
  5211. reg = <0xb1d2000 0x1000>;
  5212. reg-names = "saw-base";
  5213. qcom,name = "system-cci";
  5214. qcom,saw2-ver-reg = <0xfd0>;
  5215. qcom,saw2-cfg = <0x14>;
  5216. qcom,saw2-spm-dly = <0x3c102800>;
  5217. qcom,saw2-spm-ctl = <0xe>;
  5218. qcom,saw2-avs-ctl = <0x10>;
  5219. qcom,cpu-vctl-list = <0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9>;
  5220. qcom,vctl-timeout-us = <0x32>;
  5221. qcom,vctl-port = <0x0>;
  5222. qcom,phase-port = <0x1>;
  5223. qcom,pfm-port = <0x2>;
  5224. };
  5225.  
  5226. qcom,lpm-levels {
  5227. compatible = "qcom,lpm-levels";
  5228. qcom,use-psci;
  5229. #address-cells = <0x1>;
  5230. #size-cells = <0x0>;
  5231.  
  5232. qcom,pm-cluster@0 {
  5233. reg = <0x0>;
  5234. #address-cells = <0x1>;
  5235. #size-cells = <0x0>;
  5236. label = "system";
  5237. qcom,spm-device-names = "cci";
  5238. qcom,default-level = <0x0>;
  5239. qcom,psci-mode-shift = <0x8>;
  5240. qcom,psci-mode-mask = <0xf>;
  5241.  
  5242. qcom,pm-cluster-level@0 {
  5243. reg = <0x0>;
  5244. label = "system-active";
  5245. qcom,psci-mode = <0x0>;
  5246. qcom,latency-us = <0x1a7>;
  5247. qcom,ss-power = <0x15d>;
  5248. qcom,energy-overhead = <0x49066>;
  5249. qcom,time-overhead = <0x2cf>;
  5250. };
  5251.  
  5252. qcom,pm-cluster-level@1 {
  5253. reg = <0x1>;
  5254. label = "system-wfi";
  5255. qcom,psci-mode = <0x1>;
  5256. qcom,latency-us = <0x1e0>;
  5257. qcom,ss-power = <0x15c>;
  5258. qcom,energy-overhead = <0x4ca85>;
  5259. qcom,time-overhead = <0x2f1>;
  5260. qcom,min-child-idx = <0x3>;
  5261. };
  5262.  
  5263. qcom,pm-cluster-level@2 {
  5264. reg = <0x2>;
  5265. label = "system-pc";
  5266. qcom,psci-mode = <0x3>;
  5267. qcom,latency-us = <0x2b13>;
  5268. qcom,ss-power = <0x154>;
  5269. qcom,energy-overhead = <0x96663>;
  5270. qcom,time-overhead = <0x5d7>;
  5271. qcom,min-child-idx = <0x3>;
  5272. qcom,notify-rpm;
  5273. qcom,is-reset;
  5274. qcom,reset-level = <0x3>;
  5275. };
  5276.  
  5277. qcom,pm-cluster@0 {
  5278. reg = <0x0>;
  5279. #address-cells = <0x1>;
  5280. #size-cells = <0x0>;
  5281. label = "pwr";
  5282. qcom,spm-device-names = "l2";
  5283. qcom,default-level = <0x0>;
  5284. qcom,cpu = <0x2 0x3 0x4 0x5>;
  5285. qcom,psci-mode-shift = <0x4>;
  5286. qcom,psci-mode-mask = <0xf>;
  5287.  
  5288. qcom,pm-cluster-level@0 {
  5289. reg = <0x0>;
  5290. label = "pwr-l2-wfi";
  5291. qcom,psci-mode = <0x1>;
  5292. qcom,latency-us = <0xb4>;
  5293. qcom,ss-power = <0x169>;
  5294. qcom,energy-overhead = <0x1ba3f>;
  5295. qcom,time-overhead = <0x10e>;
  5296. };
  5297.  
  5298. qcom,pm-cluster-level@1 {
  5299. reg = <0x1>;
  5300. label = "pwr-l2-retention";
  5301. qcom,psci-mode = <0x3>;
  5302. qcom,latency-us = <0xbc>;
  5303. qcom,ss-power = <0x168>;
  5304. qcom,energy-overhead = <0x1d9b7>;
  5305. qcom,time-overhead = <0x133>;
  5306. qcom,min-child-idx = <0x1>;
  5307. qcom,reset-level = <0x1>;
  5308. };
  5309.  
  5310. qcom,pm-cluster-level@2 {
  5311. reg = <0x2>;
  5312. label = "pwr-l2-gdhs";
  5313. qcom,psci-mode = <0x4>;
  5314. qcom,latency-us = <0xd4>;
  5315. qcom,ss-power = <0x162>;
  5316. qcom,energy-overhead = <0x24cdc>;
  5317. qcom,time-overhead = <0x16b>;
  5318. qcom,min-child-idx = <0x1>;
  5319. qcom,reset-level = <0x2>;
  5320. };
  5321.  
  5322. qcom,pm-cluster-level@3 {
  5323. reg = <0x3>;
  5324. label = "pwr-l2-pc";
  5325. qcom,psci-mode = <0x5>;
  5326. qcom,latency-us = <0x1a5>;
  5327. qcom,ss-power = <0x15e>;
  5328. qcom,energy-overhead = <0x43be7>;
  5329. qcom,time-overhead = <0x2b2>;
  5330. qcom,min-child-idx = <0x1>;
  5331. qcom,is-reset;
  5332. qcom,reset-level = <0x3>;
  5333. };
  5334.  
  5335. qcom,pm-cpu {
  5336. #address-cells = <0x1>;
  5337. #size-cells = <0x0>;
  5338. qcom,psci-mode-shift = <0x0>;
  5339. qcom,psci-mode-mask = <0xf>;
  5340.  
  5341. qcom,pm-cpu-level@0 {
  5342. reg = <0x0>;
  5343. qcom,spm-cpu-mode = "wfi";
  5344. qcom,psci-cpu-mode = <0x1>;
  5345. qcom,latency-us = <0x1>;
  5346. qcom,ss-power = <0x18b>;
  5347. qcom,energy-overhead = <0x76d8>;
  5348. qcom,time-overhead = <0x3d>;
  5349. };
  5350.  
  5351. qcom,pm-cpu-level@1 {
  5352. reg = <0x1>;
  5353. qcom,spm-cpu-mode = "pc";
  5354. qcom,psci-cpu-mode = <0x3>;
  5355. qcom,latency-us = <0xb4>;
  5356. qcom,ss-power = <0x169>;
  5357. qcom,energy-overhead = <0x1ba3f>;
  5358. qcom,time-overhead = <0x10e>;
  5359. qcom,use-broadcast-timer;
  5360. qcom,is-reset;
  5361. qcom,reset-level = <0x3>;
  5362. };
  5363. };
  5364. };
  5365.  
  5366. qcom,pm-cluster@1 {
  5367. reg = <0x1>;
  5368. #address-cells = <0x1>;
  5369. #size-cells = <0x0>;
  5370. label = "perf";
  5371. qcom,spm-device-names = "l2";
  5372. qcom,default-level = <0x0>;
  5373. qcom,cpu = <0x6 0x7 0x8 0x9>;
  5374. qcom,psci-mode-shift = <0x4>;
  5375. qcom,psci-mode-mask = <0xf>;
  5376.  
  5377. qcom,pm-cluster-level@0 {
  5378. reg = <0x0>;
  5379. label = "perf-l2-wfi";
  5380. qcom,psci-mode = <0x1>;
  5381. qcom,latency-us = <0xb3>;
  5382. qcom,ss-power = <0x16a>;
  5383. qcom,energy-overhead = <0x1ba5a>;
  5384. qcom,time-overhead = <0x10c>;
  5385. };
  5386.  
  5387. qcom,pm-cluster-level@1 {
  5388. reg = <0x1>;
  5389. label = "perf-l2-retention";
  5390. qcom,psci-mode = <0x3>;
  5391. qcom,latency-us = <0xba>;
  5392. qcom,ss-power = <0x16a>;
  5393. qcom,energy-overhead = <0x1e5b6>;
  5394. qcom,time-overhead = <0x132>;
  5395. qcom,min-child-idx = <0x1>;
  5396. qcom,reset-level = <0x1>;
  5397. };
  5398.  
  5399. qcom,pm-cluster-level@2 {
  5400. reg = <0x2>;
  5401. label = "perf-l2-gdhs";
  5402. qcom,psci-mode = <0x4>;
  5403. qcom,latency-us = <0xd2>;
  5404. qcom,ss-power = <0x163>;
  5405. qcom,energy-overhead = <0x26050>;
  5406. qcom,time-overhead = <0x169>;
  5407. qcom,min-child-idx = <0x1>;
  5408. qcom,reset-level = <0x2>;
  5409. };
  5410.  
  5411. qcom,pm-cluster-level@3 {
  5412. reg = <0x3>;
  5413. label = "perf-l2-pc";
  5414. qcom,psci-mode = <0x5>;
  5415. qcom,latency-us = <0x1a7>;
  5416. qcom,ss-power = <0x15d>;
  5417. qcom,energy-overhead = <0x49066>;
  5418. qcom,time-overhead = <0x2cf>;
  5419. qcom,min-child-idx = <0x1>;
  5420. qcom,is-reset;
  5421. qcom,reset-level = <0x3>;
  5422. };
  5423.  
  5424. qcom,pm-cpu {
  5425. #address-cells = <0x1>;
  5426. #size-cells = <0x0>;
  5427. qcom,psci-mode-shift = <0x0>;
  5428. qcom,psci-mode-mask = <0xf>;
  5429.  
  5430. qcom,pm-cpu-level@0 {
  5431. reg = <0x0>;
  5432. qcom,spm-cpu-mode = "wfi";
  5433. qcom,psci-cpu-mode = <0x1>;
  5434. qcom,latency-us = <0x1>;
  5435. qcom,ss-power = <0x18d>;
  5436. qcom,energy-overhead = <0x76d8>;
  5437. qcom,time-overhead = <0x3d>;
  5438. };
  5439.  
  5440. qcom,pm-cpu-level@1 {
  5441. reg = <0x1>;
  5442. qcom,spm-cpu-mode = "pc";
  5443. qcom,psci-cpu-mode = <0x3>;
  5444. qcom,latency-us = <0xb3>;
  5445. qcom,ss-power = <0x16a>;
  5446. qcom,energy-overhead = <0x1ba5a>;
  5447. qcom,time-overhead = <0x10c>;
  5448. qcom,use-broadcast-timer;
  5449. qcom,is-reset;
  5450. qcom,reset-level = <0x3>;
  5451. };
  5452. };
  5453. };
  5454. };
  5455. };
  5456.  
  5457. qcom,mpm@601d4 {
  5458. compatible = "qcom,mpm-v2";
  5459. reg = <0x601d4 0x1000 0xb011008 0x4>;
  5460. reg-names = "vmpm", "ipc";
  5461. interrupts = <0x0 0xab 0x1>;
  5462. clocks = <0x37 0x2be48257>;
  5463. clock-names = "xo";
  5464. qcom,ipc-bit-offset = <0x1>;
  5465. qcom,gic-parent = <0x1>;
  5466. qcom,num-mpm-irqs = <0x60>;
  5467. qcom,gic-map = <0x2 0xd8 0x3a 0xa8 0x31 0xa6 0x25 0xfc 0x35 0x68 0x58 0xde 0xff 0x12 0xff 0x13 0xff 0x14 0xff 0x17 0xff 0x23 0xff 0x27 0xff 0x28 0xff 0x2f 0xff 0x36 0xff 0x38 0xff 0x39 0xff 0x3a 0xff 0x3b 0xff 0x3c 0xff 0x3d 0xff 0x41 0xff 0x45 0xff 0x49 0xff 0x4a 0xff 0x4b 0xff 0x4e 0xff 0x4f 0xff 0x55 0xff 0x56 0xff 0x5a 0xff 0x5c 0xff 0x5d 0xff 0x61 0xff 0x66 0xff 0x6c 0xff 0x6d 0xff 0x70 0xff 0x72 0xff 0x7e 0xff 0x80 0xff 0x83 0xff 0x88 0xff 0x89 0xff 0x8a 0xff 0x8b 0xff 0x8c 0xff 0x8d 0xff 0x8e 0xff 0x8f 0xff 0x90 0xff 0x91 0xff 0x92 0xff 0x93 0xff 0x94 0xff 0x95 0xff 0x96 0xff 0x97 0xff 0x98 0xff 0x99 0xff 0x9b 0xff 0x9d 0xff 0xa7 0xff 0xaa 0xff 0xac 0xff 0xad 0xff 0xae 0xff 0xaf 0xff 0xb0 0xff 0xb1 0xff 0xb2 0xff 0xb3 0xff 0xb5 0xff 0xbc 0xff 0xbd 0xff 0xbe 0xff 0xbf 0xff 0xc0 0xff 0xc1 0xff 0xc2 0xff 0xc3 0xff 0xc4 0xff 0xc5 0xff 0xc6 0xff 0xc8 0xff 0xc9 0xff 0xca 0xff 0xcb 0xff 0xcc 0xff 0xcd 0xff 0xce 0xff 0xcf 0xff 0xd4 0xff 0xd7 0xff 0xe0 0xff 0xe7 0xff 0xef 0xff 0xf0 0xff 0xfd 0xff 0x101 0xff 0x104 0xff 0x106 0xff 0x107 0xff 0x108 0xff 0x10d 0xff 0x10e 0xff 0x111 0xff 0x112 0xff 0x113 0xff 0x114 0xff 0x11d 0xff 0x11e 0xff 0x11f 0xff 0x131 0xff 0x132 0xff 0x133 0xff 0x134 0xff 0x13a 0xff 0x141 0xff 0x142 0xff 0x143 0xff 0x145 0xff 0x158 0xff 0x15a>;
  5468. qcom,gpio-parent = <0xbe>;
  5469. qcom,gpio-map = <0x3 0x26 0x4 0x1 0x5 0x5 0x6 0x9 0x8 0x25 0x9 0x24 0xa 0xd 0xb 0x23 0xc 0x11 0xd 0x15 0xe 0x36 0xf 0x22 0x10 0x1f 0x11 0x3a 0x12 0x1c 0x13 0x2a 0x14 0x19 0x15 0xc 0x16 0x2b 0x17 0x2c 0x18 0x2d 0x19 0x2e 0x1a 0x30 0x1b 0x41 0x1c 0x5d 0x1d 0x61 0x1e 0x3f 0x1f 0x46 0x20 0x47 0x21 0x48 0x22 0x51 0x23 0x55 0x24 0x5a 0x32 0x43 0x33 0x49 0x34 0x4a 0x35 0x3e 0x3b 0x3b 0x3c 0x3c 0x3d 0x3d 0x3e 0x56 0x3f 0x57 0x40 0x5b 0x41 0x81 0x42 0x82 0x43 0x83 0x44 0x84 0x45 0x85 0x46 0x89 0x47 0x8a 0x48 0x8b 0x49 0x8c 0x4a 0x8d 0xff 0x58>;
  5470. };
  5471.  
  5472. qcom,cpu-sleep-status {
  5473. compatible = "qcom,cpu-sleep-status";
  5474. };
  5475.  
  5476. qcom,rpm-log@29fc00 {
  5477. compatible = "qcom,rpm-log";
  5478. reg = <0x29fc00 0x4000>;
  5479. qcom,rpm-addr-phys = <0x200000>;
  5480. qcom,offset-version = <0x4>;
  5481. qcom,offset-page-buffer-addr = <0x24>;
  5482. qcom,offset-log-len = <0x28>;
  5483. qcom,offset-log-len-mask = <0x2c>;
  5484. qcom,offset-page-indices = <0x38>;
  5485. };
  5486.  
  5487. qcom,rpm-stats@200000 {
  5488. compatible = "qcom,rpm-stats";
  5489. reg = <0x200000 0x1000 0x290014 0x4 0x29001c 0x4>;
  5490. reg-names = "phys_addr_base", "offset_addr", "heap_phys_addrbase";
  5491. qcom,sleep-stats-version = <0x2>;
  5492. };
  5493.  
  5494. qcom,rpm-master-stats@60150 {
  5495. compatible = "qcom,rpm-master-stats";
  5496. reg = <0x60150 0x5000>;
  5497. qcom,masters = "APSS", "MPSS", "PRONTO", "TZ", "LPASS";
  5498. qcom,master-stats-version = <0x2>;
  5499. qcom,master-offset = <0x1000>;
  5500. };
  5501.  
  5502. apm@b111000 {
  5503. compatible = "qcom,msm8953-apm";
  5504. reg = <0xb111000 0x1000>;
  5505. reg-names = "pm-apcc-glb";
  5506. qcom,apm-post-halt-delay = <0x2>;
  5507. qcom,apm-halt-clk-delay = <0x11>;
  5508. qcom,apm-resume-clk-delay = <0x10>;
  5509. qcom,apm-sel-switch-delay = <0x1>;
  5510. linux,phandle = <0x12e>;
  5511. phandle = <0x12e>;
  5512. };
  5513.  
  5514. interrupt-controller@b000000 {
  5515. compatible = "qcom,msm-qgic2";
  5516. interrupt-controller;
  5517. #interrupt-cells = <0x3>;
  5518. reg = <0xb000000 0x1000 0xb002000 0x1000>;
  5519. linux,phandle = <0x1>;
  5520. phandle = <0x1>;
  5521. };
  5522.  
  5523. arm64-cpu-erp {
  5524. compatible = "arm,arm64-cpu-erp";
  5525. interrupts = <0x0 0x113 0x0 0x0 0x114 0x0 0x0 0x111 0x0 0x0 0x112 0x0>;
  5526. interrupt-names = "pri-dbe-irq", "sec-dbe-irq", "pri-ext-irq", "sec-ext-irq";
  5527. poll-delay-ms = <0x1388>;
  5528. };
  5529.  
  5530. qcom,msm-gladiator@b1c0000 {
  5531. compatible = "qcom,msm-gladiator";
  5532. reg = <0xb1c0000 0x4000>;
  5533. reg-names = "gladiator_base";
  5534. interrupts = <0x0 0x16 0x0>;
  5535. };
  5536.  
  5537. timer {
  5538. compatible = "arm,armv8-timer";
  5539. interrupts = <0x1 0x2 0xff08 0x1 0x3 0xff08 0x1 0x4 0xff08 0x1 0x1 0xff08>;
  5540. clock-frequency = <0x124f800>;
  5541. };
  5542.  
  5543. timer@b120000 {
  5544. #address-cells = <0x1>;
  5545. #size-cells = <0x1>;
  5546. ranges;
  5547. compatible = "arm,armv7-timer-mem";
  5548. reg = <0xb120000 0x1000>;
  5549. clock-frequency = <0x124f800>;
  5550.  
  5551. frame@b121000 {
  5552. frame-number = <0x0>;
  5553. interrupts = <0x0 0x8 0x4 0x0 0x7 0x4>;
  5554. reg = <0xb121000 0x1000 0xb122000 0x1000>;
  5555. };
  5556.  
  5557. frame@b123000 {
  5558. frame-number = <0x1>;
  5559. interrupts = <0x0 0x9 0x4>;
  5560. reg = <0xb123000 0x1000>;
  5561. status = "disabled";
  5562. };
  5563.  
  5564. frame@b124000 {
  5565. frame-number = <0x2>;
  5566. interrupts = <0x0 0xa 0x4>;
  5567. reg = <0xb124000 0x1000>;
  5568. status = "disabled";
  5569. };
  5570.  
  5571. frame@b125000 {
  5572. frame-number = <0x3>;
  5573. interrupts = <0x0 0xb 0x4>;
  5574. reg = <0xb125000 0x1000>;
  5575. status = "disabled";
  5576. };
  5577.  
  5578. frame@b126000 {
  5579. frame-number = <0x4>;
  5580. interrupts = <0x0 0xc 0x4>;
  5581. reg = <0xb126000 0x1000>;
  5582. status = "disabled";
  5583. };
  5584.  
  5585. frame@b127000 {
  5586. frame-number = <0x5>;
  5587. interrupts = <0x0 0xd 0x4>;
  5588. reg = <0xb127000 0x1000>;
  5589. status = "disabled";
  5590. };
  5591.  
  5592. frame@b128000 {
  5593. frame-number = <0x6>;
  5594. interrupts = <0x0 0xe 0x4>;
  5595. reg = <0xb128000 0x1000>;
  5596. status = "disabled";
  5597. };
  5598. };
  5599.  
  5600. qcom,rmtfs_sharedmem@00000000 {
  5601. compatible = "qcom,sharedmem-uio";
  5602. reg = <0x0 0x180000>;
  5603. reg-names = "rmtfs";
  5604. qcom,client-id = <0x1>;
  5605. };
  5606.  
  5607. restart@4ab000 {
  5608. compatible = "qcom,pshold";
  5609. reg = <0x4ab000 0x4 0x193d100 0x4>;
  5610. reg-names = "pshold-base", "tcsr-boot-misc-detect";
  5611. };
  5612.  
  5613. qcom,mpm2-sleep-counter@4a3000 {
  5614. compatible = "qcom,mpm2-sleep-counter";
  5615. reg = <0x4a3000 0x1000>;
  5616. clock-frequency = <0x8000>;
  5617. };
  5618.  
  5619. cpu-pmu {
  5620. compatible = "arm,armv8-pmuv3";
  5621. interrupts = <0x1 0x7 0xff00>;
  5622. };
  5623.  
  5624. qcom,sps {
  5625. compatible = "qcom,msm_sps_4k";
  5626. qcom,pipe-attr-ee;
  5627. };
  5628.  
  5629. tsens@4a8000 {
  5630. compatible = "qcom,msm8953-tsens";
  5631. reg = <0x4a8000 0x2000 0xa4000 0x1000>;
  5632. reg-names = "tsens_physical", "tsens_eeprom_physical";
  5633. interrupts = <0x0 0xb8 0x0 0x0 0x13a 0x0>;
  5634. interrupt-names = "tsens-upper-lower", "tsens-critical";
  5635. qcom,sensors = <0x10>;
  5636. qcom,slope = <0xc80 0xc80 0xc80 0xc80 0xc80 0xc80 0xc80 0xc80 0xc80 0xc80 0xc80 0xc80 0xc80 0xc80 0xc80 0xc80>;
  5637. qcom,valid-status-check;
  5638. };
  5639.  
  5640. qcom,sensor-information {
  5641. compatible = "qcom,sensor-information";
  5642.  
  5643. qcom,sensor-information-0 {
  5644. qcom,sensor-type = "tsens";
  5645. qcom,sensor-name = "tsens_tz_sensor0";
  5646. qcom,scaling-factor = <0xa>;
  5647. };
  5648.  
  5649. qcom,sensor-information-1 {
  5650. qcom,sensor-type = "tsens";
  5651. qcom,sensor-name = "tsens_tz_sensor1";
  5652. qcom,scaling-factor = <0xa>;
  5653. };
  5654.  
  5655. qcom,sensor-information-2 {
  5656. qcom,sensor-type = "tsens";
  5657. qcom,sensor-name = "tsens_tz_sensor2";
  5658. qcom,alias-name = "pop_mem";
  5659. qcom,scaling-factor = <0xa>;
  5660. };
  5661.  
  5662. qcom,sensor-information-3 {
  5663. qcom,sensor-type = "tsens";
  5664. qcom,sensor-name = "tsens_tz_sensor3";
  5665. qcom,scaling-factor = <0xa>;
  5666. };
  5667.  
  5668. qcom,sensor-information-4 {
  5669. qcom,sensor-type = "tsens";
  5670. qcom,sensor-name = "tsens_tz_sensor4";
  5671. qcom,scaling-factor = <0xa>;
  5672. linux,phandle = <0xc3>;
  5673. phandle = <0xc3>;
  5674. };
  5675.  
  5676. qcom,sensor-information-5 {
  5677. qcom,sensor-type = "tsens";
  5678. qcom,sensor-name = "tsens_tz_sensor5";
  5679. qcom,scaling-factor = <0xa>;
  5680. linux,phandle = <0xc4>;
  5681. phandle = <0xc4>;
  5682. };
  5683.  
  5684. qcom,sensor-information-6 {
  5685. qcom,sensor-type = "tsens";
  5686. qcom,sensor-name = "tsens_tz_sensor6";
  5687. qcom,scaling-factor = <0xa>;
  5688. linux,phandle = <0xc5>;
  5689. phandle = <0xc5>;
  5690. };
  5691.  
  5692. qcom,sensor-information-7 {
  5693. qcom,sensor-type = "tsens";
  5694. qcom,sensor-name = "tsens_tz_sensor7";
  5695. qcom,scaling-factor = <0xa>;
  5696. linux,phandle = <0xc6>;
  5697. phandle = <0xc6>;
  5698. };
  5699.  
  5700. qcom,sensor-information-8 {
  5701. qcom,sensor-type = "tsens";
  5702. qcom,sensor-name = "tsens_tz_sensor8";
  5703. qcom,scaling-factor = <0xa>;
  5704. qcom,alias-name = "L2_cache_1";
  5705. };
  5706.  
  5707. qcom,sensor-information-9 {
  5708. qcom,sensor-type = "tsens";
  5709. qcom,sensor-name = "tsens_tz_sensor9";
  5710. qcom,scaling-factor = <0xa>;
  5711. linux,phandle = <0xbf>;
  5712. phandle = <0xbf>;
  5713. };
  5714.  
  5715. qcom,sensor-information-10 {
  5716. qcom,sensor-type = "tsens";
  5717. qcom,sensor-name = "tsens_tz_sensor10";
  5718. qcom,scaling-factor = <0xa>;
  5719. linux,phandle = <0xc0>;
  5720. phandle = <0xc0>;
  5721. };
  5722.  
  5723. qcom,sensor-information-11 {
  5724. qcom,sensor-type = "tsens";
  5725. qcom,sensor-name = "tsens_tz_sensor11";
  5726. qcom,scaling-factor = <0xa>;
  5727. linux,phandle = <0xc1>;
  5728. phandle = <0xc1>;
  5729. };
  5730.  
  5731. qcom,sensor-information-12 {
  5732. qcom,sensor-type = "tsens";
  5733. qcom,sensor-name = "tsens_tz_sensor12";
  5734. qcom,scaling-factor = <0xa>;
  5735. linux,phandle = <0xc2>;
  5736. phandle = <0xc2>;
  5737. };
  5738.  
  5739. qcom,sensor-information-13 {
  5740. qcom,sensor-type = "tsens";
  5741. qcom,sensor-name = "tsens_tz_sensor13";
  5742. qcom,scaling-factor = <0xa>;
  5743. qcom,alias-name = "L2_cache_0";
  5744. };
  5745.  
  5746. qcom,sensor-information-14 {
  5747. qcom,sensor-type = "tsens";
  5748. qcom,sensor-name = "tsens_tz_sensor14";
  5749. qcom,scaling-factor = <0xa>;
  5750. };
  5751.  
  5752. qcom,sensor-information-15 {
  5753. qcom,sensor-type = "tsens";
  5754. qcom,sensor-name = "tsens_tz_sensor15";
  5755. qcom,alias-name = "gpu";
  5756. qcom,scaling-factor = <0xa>;
  5757. };
  5758.  
  5759. qcom,sensor-information-16 {
  5760. qcom,sensor-type = "alarm";
  5761. qcom,sensor-name = "pm8953_tz";
  5762. qcom,scaling-factor = <0x3e8>;
  5763. };
  5764.  
  5765. qcom,sensor-information-17 {
  5766. qcom,sensor-type = "adc";
  5767. qcom,sensor-name = "pa_therm0";
  5768. };
  5769.  
  5770. qcom,sensor-information-18 {
  5771. qcom,sensor-type = "adc";
  5772. qcom,sensor-name = "pa_therm1";
  5773. };
  5774.  
  5775. qcom,sensor-information-19 {
  5776. qcom,sensor-type = "adc";
  5777. qcom,sensor-name = "xo_therm";
  5778. };
  5779.  
  5780. qcom,sensor-information-20 {
  5781. qcom,sensor-type = "adc";
  5782. qcom,sensor-name = "xo_therm_buf";
  5783. };
  5784.  
  5785. qcom,sensor-information-21 {
  5786. qcom,sensor-type = "adc";
  5787. qcom,sensor-name = "case_therm";
  5788. };
  5789. };
  5790.  
  5791. qcom,limit_info-0 {
  5792. qcom,temperature-sensor = <0xbf>;
  5793. qcom,boot-frequency-mitigate;
  5794. qcom,hotplug-mitigation-enable;
  5795. qcom,emergency-frequency-mitigate;
  5796. linux,phandle = <0xb>;
  5797. phandle = <0xb>;
  5798. };
  5799.  
  5800. qcom,limit_info-1 {
  5801. qcom,temperature-sensor = <0xc0>;
  5802. qcom,boot-frequency-mitigate;
  5803. qcom,hotplug-mitigation-enable;
  5804. qcom,emergency-frequency-mitigate;
  5805. linux,phandle = <0x10>;
  5806. phandle = <0x10>;
  5807. };
  5808.  
  5809. qcom,limit_info-2 {
  5810. qcom,temperature-sensor = <0xc1>;
  5811. qcom,boot-frequency-mitigate;
  5812. qcom,hotplug-mitigation-enable;
  5813. qcom,emergency-frequency-mitigate;
  5814. linux,phandle = <0x13>;
  5815. phandle = <0x13>;
  5816. };
  5817.  
  5818. qcom,limit_info-3 {
  5819. qcom,temperature-sensor = <0xc2>;
  5820. qcom,boot-frequency-mitigate;
  5821. qcom,hotplug-mitigation-enable;
  5822. qcom,emergency-frequency-mitigate;
  5823. linux,phandle = <0x16>;
  5824. phandle = <0x16>;
  5825. };
  5826.  
  5827. qcom,limit_info-4 {
  5828. qcom,temperature-sensor = <0xc3>;
  5829. qcom,boot-frequency-mitigate;
  5830. qcom,hotplug-mitigation-enable;
  5831. qcom,emergency-frequency-mitigate;
  5832. linux,phandle = <0x19>;
  5833. phandle = <0x19>;
  5834. };
  5835.  
  5836. qcom,limit_info-5 {
  5837. qcom,temperature-sensor = <0xc4>;
  5838. qcom,boot-frequency-mitigate;
  5839. qcom,hotplug-mitigation-enable;
  5840. qcom,emergency-frequency-mitigate;
  5841. linux,phandle = <0x1e>;
  5842. phandle = <0x1e>;
  5843. };
  5844.  
  5845. qcom,limit_info-6 {
  5846. qcom,temperature-sensor = <0xc5>;
  5847. qcom,boot-frequency-mitigate;
  5848. qcom,hotplug-mitigation-enable;
  5849. qcom,emergency-frequency-mitigate;
  5850. linux,phandle = <0x21>;
  5851. phandle = <0x21>;
  5852. };
  5853.  
  5854. qcom,limit_info-7 {
  5855. qcom,temperature-sensor = <0xc6>;
  5856. qcom,boot-frequency-mitigate;
  5857. qcom,hotplug-mitigation-enable;
  5858. qcom,emergency-frequency-mitigate;
  5859. linux,phandle = <0x24>;
  5860. phandle = <0x24>;
  5861. };
  5862.  
  5863. qcom,msm-thermal {
  5864. compatible = "qcom,msm-thermal";
  5865. qcom,sensor-id = <0x9>;
  5866. qcom,poll-ms = <0xfa>;
  5867. qcom,limit-temp = <0x3c>;
  5868. qcom,temp-hysteresis = <0xa>;
  5869. qcom,freq-step = <0x2>;
  5870. qcom,core-limit-temp = <0x50>;
  5871. qcom,core-temp-hysteresis = <0xa>;
  5872. qcom,hotplug-temp = <0x69>;
  5873. qcom,hotplug-temp-hysteresis = <0xf>;
  5874. qcom,freq-mitigation-temp = <0x69>;
  5875. qcom,freq-mitigation-temp-hysteresis = <0xf>;
  5876. qcom,freq-mitigation-value = <0xfd200>;
  5877. qcom,therm-reset-temp = <0x73>;
  5878. qcom,online-hotplug-core;
  5879. qcom,synchronous-cluster-id = <0x0 0x1>;
  5880. qcom,synchronous-cluster-map = <0x0 0x4 0x2 0x3 0x4 0x5 0x1 0x4 0x6 0x7 0x8 0x9>;
  5881. qcom,disable-cx-phase-ctrl;
  5882. qcom,disable-gfx-phase-ctrl;
  5883. qcom,disable-vdd-mx;
  5884. qcom,disable-psm;
  5885. qcom,disable-ocr;
  5886. qcom,vdd-restriction-temp = <0x5>;
  5887. qcom,vdd-restriction-temp-hysteresis = <0xa>;
  5888. vdd-dig-supply = <0xc7>;
  5889. vdd-gfx-supply = <0xc8>;
  5890.  
  5891. qcom,vdd-dig-rstr {
  5892. qcom,vdd-rstr-reg = "vdd-dig";
  5893. qcom,levels = <0x100 0x200 0x200>;
  5894. qcom,min-level = <0x0>;
  5895. };
  5896.  
  5897. qcom,vdd-gfx-rstr {
  5898. qcom,vdd-rstr-reg = "vdd-gfx";
  5899. qcom,levels = <0x5 0x7 0x7>;
  5900. qcom,min-level = <0x1>;
  5901. };
  5902.  
  5903. qcom,vdd-apps-rstr {
  5904. qcom,vdd-rstr-reg = "vdd-apps";
  5905. qcom,levels = <0x19c800>;
  5906. qcom,freq-req;
  5907. linux,phandle = <0xc9>;
  5908. phandle = <0xc9>;
  5909. };
  5910. };
  5911.  
  5912. qcom,bcl {
  5913. compatible = "qcom,bcl";
  5914. qcom,bcl-enable;
  5915. qcom,bcl-framework-interface;
  5916. qcom,bcl-freq-control-list = <0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9>;
  5917. qcom,bcl-hotplug-list = <0x8 0x9>;
  5918. qcom,bcl-soc-hotplug-list = <0x6 0x7 0x8 0x9>;
  5919.  
  5920. qcom,ibat-monitor {
  5921. qcom,low-threshold-uamp = <0x33e140>;
  5922. qcom,high-threshold-uamp = <0x401640>;
  5923. qcom,mitigation-freq-khz = <0x19c800>;
  5924. qcom,vph-high-threshold-uv = <0x3567e0>;
  5925. qcom,vph-low-threshold-uv = <0x30d400>;
  5926. qcom,soc-low-threshold = <0xa>;
  5927. qcom,thermal-handle = <0xc9>;
  5928. };
  5929. };
  5930.  
  5931. qcom,msm-core@a0000 {
  5932. compatible = "qcom,apss-core-ea";
  5933. reg = <0xa0000 0x1000>;
  5934. qcom,low-hyst-temp = <0xa>;
  5935. qcom,high-hyst-temp = <0x5>;
  5936.  
  5937. ea0 {
  5938. sensor = <0xbf>;
  5939. linux,phandle = <0xc>;
  5940. phandle = <0xc>;
  5941. };
  5942.  
  5943. ea1 {
  5944. sensor = <0xc0>;
  5945. linux,phandle = <0x11>;
  5946. phandle = <0x11>;
  5947. };
  5948.  
  5949. ea2 {
  5950. sensor = <0xc1>;
  5951. linux,phandle = <0x14>;
  5952. phandle = <0x14>;
  5953. };
  5954.  
  5955. ea3 {
  5956. sensor = <0xc2>;
  5957. linux,phandle = <0x17>;
  5958. phandle = <0x17>;
  5959. };
  5960.  
  5961. ea4 {
  5962. sensor = <0xc3>;
  5963. linux,phandle = <0x1a>;
  5964. phandle = <0x1a>;
  5965. };
  5966.  
  5967. ea5 {
  5968. sensor = <0xc4>;
  5969. linux,phandle = <0x1f>;
  5970. phandle = <0x1f>;
  5971. };
  5972.  
  5973. ea6 {
  5974. sensor = <0xc5>;
  5975. linux,phandle = <0x22>;
  5976. phandle = <0x22>;
  5977. };
  5978.  
  5979. ea7 {
  5980. sensor = <0xc6>;
  5981. linux,phandle = <0x25>;
  5982. phandle = <0x25>;
  5983. };
  5984. };
  5985.  
  5986. serial@78af000 {
  5987. compatible = "qcom,msm-lsuart-v14";
  5988. reg = <0x78af000 0x200>;
  5989. interrupts = <0x0 0x6b 0x0>;
  5990. status = "ok";
  5991. clocks = <0x37 0xc7c62f90 0x37 0x8caa5b4f>;
  5992. clock-names = "core_clk", "iface_clk";
  5993. pinctrl-names = "default";
  5994. pinctrl-0 = <0xca>;
  5995. };
  5996.  
  5997. uart@78b0000 {
  5998. compatible = "qcom,msm-hsuart-v14";
  5999. reg = <0x78b0000 0x200 0x7884000 0x1f000>;
  6000. reg-names = "core_mem", "bam_mem";
  6001. interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
  6002. #address-cells = <0x0>;
  6003. interrupt-parent = <0xcb>;
  6004. interrupts = <0x0 0x1 0x2>;
  6005. #interrupt-cells = <0x1>;
  6006. interrupt-map-mask = <0xffffffff>;
  6007. interrupt-map = <0x0 0x1 0x0 0x6c 0x0 0x1 0x1 0x0 0xee 0x0 0x2 0xbe 0xd 0x0>;
  6008. qcom,inject-rx-on-wakeup;
  6009. qcom,rx-char-to-inject = <0xfd>;
  6010. qcom,master-id = <0x56>;
  6011. clock-names = "core_clk", "iface_clk";
  6012. clocks = <0x37 0xf8a61c96 0x37 0x8caa5b4f>;
  6013. pinctrl-names = "sleep", "default";
  6014. pinctrl-0 = <0xcc>;
  6015. pinctrl-1 = <0xcd>;
  6016. qcom,bam-tx-ep-pipe-index = <0x2>;
  6017. qcom,bam-rx-ep-pipe-index = <0x3>;
  6018. qcom,msm-bus,name = "blsp1_uart1";
  6019. qcom,msm-bus,num-cases = <0x2>;
  6020. qcom,msm-bus,num-paths = <0x1>;
  6021. qcom,msm-bus,vectors-KBps = <0x56 0x200 0x0 0x0 0x56 0x200 0x1f4 0x320>;
  6022. status = "disabled";
  6023. linux,phandle = <0xcb>;
  6024. phandle = <0xcb>;
  6025. };
  6026.  
  6027. qcom,sps-dma@7884000 {
  6028. #dma-cells = <0x4>;
  6029. compatible = "qcom,sps-dma";
  6030. reg = <0x7884000 0x1f000>;
  6031. interrupts = <0x0 0xee 0x0>;
  6032. qcom,summing-threshold = <0xa>;
  6033. linux,phandle = <0xd4>;
  6034. phandle = <0xd4>;
  6035. };
  6036.  
  6037. qcom,sps-dma@7ac4000 {
  6038. #dma-cells = <0x4>;
  6039. compatible = "qcom,sps-dma";
  6040. reg = <0x7ac4000 0x1f000>;
  6041. interrupts = <0x0 0xef 0x0>;
  6042. qcom,summing-threshold = <0xa>;
  6043. linux,phandle = <0xe9>;
  6044. phandle = <0xe9>;
  6045. };
  6046.  
  6047. spi@78b7000 {
  6048. compatible = "qcom,spi-qup-v2";
  6049. #address-cells = <0x1>;
  6050. #size-cells = <0x0>;
  6051. reg-names = "spi_physical", "spi_bam_physical";
  6052. reg = <0x78b7000 0x600 0x7884000 0x1f000>;
  6053. interrupt-names = "spi_irq", "spi_bam_irq";
  6054. interrupts = <0x0 0x61 0x0 0x0 0xee 0x0>;
  6055. spi-max-frequency = <0x124f800>;
  6056. pinctrl-names = "spi_default", "spi_sleep";
  6057. pinctrl-0 = <0xce 0xcf>;
  6058. pinctrl-1 = <0xd0 0xd1>;
  6059. clocks = <0x37 0x8caa5b4f 0x37 0xfb978880>;
  6060. clock-names = "iface_clk", "core_clk";
  6061. qcom,infinite-mode = <0x0>;
  6062. qcom,use-bam;
  6063. qcom,use-pinctrl;
  6064. qcom,ver-reg-exists;
  6065. qcom,bam-consumer-pipe-index = <0x8>;
  6066. qcom,bam-producer-pipe-index = <0x9>;
  6067. qcom,master-id = <0x56>;
  6068. };
  6069.  
  6070. i2c@78b6000 {
  6071. compatible = "qcom,i2c-msm-v2";
  6072. #address-cells = <0x1>;
  6073. #size-cells = <0x0>;
  6074. reg-names = "qup_phys_addr";
  6075. reg = <0x78b6000 0x600>;
  6076. interrupt-names = "qup_irq";
  6077. interrupts = <0x0 0x60 0x0>;
  6078. qcom,clk-freq-out = <0x61a80>;
  6079. qcom,clk-freq-in = <0x124f800>;
  6080. clock-names = "iface_clk", "core_clk";
  6081. clocks = <0x37 0x8caa5b4f 0x37 0x1076f220>;
  6082. pinctrl-names = "i2c_active", "i2c_sleep";
  6083. pinctrl-0 = <0xd2>;
  6084. pinctrl-1 = <0xd3>;
  6085. qcom,noise-rjct-scl = <0x0>;
  6086. qcom,noise-rjct-sda = <0x0>;
  6087. qcom,master-id = <0x56>;
  6088. dmas = <0xd4 0x6 0x40 0x20000020 0x20 0xd4 0x7 0x20 0x20000020 0x20>;
  6089. dma-names = "tx", "rx";
  6090.  
  6091. adv7533@39 {
  6092. compatible = "adv7533";
  6093. reg = <0x39>;
  6094. instance_id = <0x0>;
  6095. adi,video-mode = <0x3>;
  6096. adi,main-addr = <0x39>;
  6097. adi,cec-dsi-addr = <0x3c>;
  6098. adi,enable-audio;
  6099. pinctrl-names = "pmx_adv7533_active", "pmx_adv7533_suspend";
  6100. pinctrl-0 = <0xd5>;
  6101. pinctrl-1 = <0xd6>;
  6102. adi,irq-gpio = <0xbe 0x5a 0x2002>;
  6103. hpd-5v-en-supply = <0xd7>;
  6104. qcom,supply-names = "hpd-5v-en";
  6105. qcom,min-voltage-level = <0x0>;
  6106. qcom,max-voltage-level = <0x0>;
  6107. qcom,enable-load = <0x0>;
  6108. qcom,disable-load = <0x0>;
  6109. };
  6110.  
  6111. wsa881x-i2c-codec@e {
  6112. status = "disabled";
  6113. compatible = "qcom,wsa881x-i2c-codec";
  6114. reg = <0xe>;
  6115. qcom,msm-gpios = "wsa_clk", "wsa_reset", "wsa_vi";
  6116. qcom,pinctrl-names = "all_off", "wsa_clk", "wsa_active", "wsa_clk_active", "wsa_vi", "wsa_clk_vi", "wsa_active_vi", "wsa_all";
  6117. pinctrl-names = "all_off", "wsa_clk", "wsa_active", "wsa_clk_active", "wsa_vi", "wsa_clk_vi", "wsa_active_vi", "wsa_all";
  6118. pinctrl-0 = <0xd8 0xd9 0xda>;
  6119. pinctrl-1 = <0xdb 0xd9 0xda>;
  6120. pinctrl-2 = <0xd8 0xdc 0xda>;
  6121. pinctrl-3 = <0xdb 0xdc 0xda>;
  6122. pinctrl-4 = <0xd8 0xd9 0xdd>;
  6123. pinctrl-5 = <0xdb 0xd9 0xdd>;
  6124. pinctrl-6 = <0xd8 0xdc 0xdd>;
  6125. pinctrl-7 = <0xdb 0xdc 0xdd>;
  6126. };
  6127.  
  6128. wsa881x-i2c-codec@44 {
  6129. status = "disabled";
  6130. compatible = "qcom,wsa881x-i2c-codec";
  6131. reg = <0x44>;
  6132. };
  6133.  
  6134. wsa881x-i2c-codec@f {
  6135. status = "disabled";
  6136. compatible = "qcom,wsa881x-i2c-codec";
  6137. reg = <0xf>;
  6138. qcom,msm-gpios = "wsa_clk", "wsa_reset", "wsa_vi";
  6139. qcom,pinctrl-names = "all_off", "wsa_clk", "wsa_active", "wsa_clk_active", "wsa_vi", "wsa_clk_vi", "wsa_active_vi", "wsa_all";
  6140. pinctrl-names = "all_off", "wsa_clk", "wsa_active", "wsa_clk_active", "wsa_vi", "wsa_clk_vi", "wsa_active_vi", "wsa_all";
  6141. pinctrl-0 = <0xd8 0xd9 0xda>;
  6142. pinctrl-1 = <0xdb 0xd9 0xda>;
  6143. pinctrl-2 = <0xd8 0xdc 0xda>;
  6144. pinctrl-3 = <0xdb 0xdc 0xda>;
  6145. pinctrl-4 = <0xd8 0xd9 0xdd>;
  6146. pinctrl-5 = <0xdb 0xd9 0xdd>;
  6147. pinctrl-6 = <0xd8 0xdc 0xdd>;
  6148. pinctrl-7 = <0xdb 0xdc 0xdd>;
  6149. };
  6150.  
  6151. wsa881x-i2c-codec@45 {
  6152. status = "disabled";
  6153. compatible = "qcom,wsa881x-i2c-codec";
  6154. reg = <0x45>;
  6155. };
  6156.  
  6157. aw2013@45 {
  6158. compatible = "awinc,aw2013";
  6159. reg = <0x45>;
  6160. rgb_led-supply = <0xde>;
  6161.  
  6162. red {
  6163. label = "red";
  6164. linux,default-trigger = "battery-red";
  6165. default-state = "off";
  6166. retain-state-suspended;
  6167. };
  6168.  
  6169. green {
  6170. label = "green";
  6171. linux,default-trigger = "battery-green";
  6172. default-state = "off";
  6173. retain-state-suspended;
  6174. };
  6175.  
  6176. blue {
  6177. label = "blue";
  6178. linux,default-trigger = "battery-blue";
  6179. default-state = "off";
  6180. retain-state-suspended;
  6181. };
  6182.  
  6183. white {
  6184. label = "white";
  6185. linux,default-trigger = "none";
  6186. default-state = "off";
  6187. retain-state-suspended;
  6188. };
  6189.  
  6190. yellow {
  6191. label = "yellow";
  6192. linux,default-trigger = "none";
  6193. default-state = "off";
  6194. retain-state-suspended;
  6195. };
  6196.  
  6197. cyan {
  6198. label = "cyan";
  6199. linux,default-trigger = "none";
  6200. default-state = "off";
  6201. retain-state-suspended;
  6202. };
  6203.  
  6204. purple {
  6205. label = "purple";
  6206. linux,default-trigger = "none";
  6207. default-state = "off";
  6208. retain-state-suspended;
  6209. };
  6210. };
  6211.  
  6212. pericom-type-c@1d {
  6213. status = "disabled";
  6214. };
  6215. };
  6216.  
  6217. i2c@78b7000 {
  6218. compatible = "qcom,i2c-msm-v2";
  6219. #address-cells = <0x1>;
  6220. #size-cells = <0x0>;
  6221. reg-names = "qup_phys_addr";
  6222. reg = <0x78b7000 0x600>;
  6223. interrupt-names = "qup_irq";
  6224. interrupts = <0x0 0x61 0x0>;
  6225. qcom,clk-freq-out = <0x61a80>;
  6226. qcom,clk-freq-in = <0x124f800>;
  6227. clock-names = "iface_clk", "core_clk";
  6228. clocks = <0x37 0x8caa5b4f 0x37 0x9e25ac82>;
  6229. pinctrl-names = "i2c_active", "i2c_sleep";
  6230. pinctrl-0 = <0xdf>;
  6231. pinctrl-1 = <0xe0>;
  6232. qcom,noise-rjct-scl = <0x0>;
  6233. qcom,noise-rjct-sda = <0x0>;
  6234. qcom,master-id = <0x56>;
  6235. dmas = <0xd4 0x8 0x40 0x20000020 0x20 0xd4 0x9 0x20 0x20000020 0x20>;
  6236. dma-names = "tx", "rx";
  6237. status = "ok";
  6238.  
  6239. ftech@38 {
  6240. compatible = "focaltech,5336";
  6241. reg = <0x38>;
  6242. interrupt-parent = <0xbe>;
  6243. interrupts = <0x41 0x2008>;
  6244. vdd-supply = <0xde>;
  6245. vcc_i2c-supply = <0xe1>;
  6246. pinctrl-names = "pmx_ts_active", "pmx_ts_suspend", "pmx_ts_release";
  6247. pinctrl-0 = <0xe2 0xe3>;
  6248. pinctrl-1 = <0xe4 0xe5>;
  6249. pinctrl-2 = <0xe6>;
  6250. ftech,name = "ft5336";
  6251. ftech,family-id = <0x36>;
  6252. ftech,reset-gpio = <0xbe 0x40 0x0>;
  6253. ftech,irq-gpio = <0xbe 0x41 0x2008>;
  6254. ftech,display-coords = <0x0 0x0 0x438 0x780>;
  6255. ftech,panel-coords = <0x0 0x0 0x438 0x780>;
  6256. ftech,virtual-key1 = <0x8b 0xb4 0x7d0>;
  6257. ftech,virtual-key2 = <0xac 0x21c 0x7d0>;
  6258. ftech,virtual-key3 = <0x9e 0x384 0x7d0>;
  6259. ftech,no-force-update;
  6260. ftech,i2c-pull-up;
  6261. ftech,group-id = <0x1>;
  6262. ftech,hard-reset-delay-ms = <0x14>;
  6263. ftech,soft-reset-delay-ms = <0xc8>;
  6264. ftech,num-max-touches = <0xa>;
  6265. ftech,fw-delay-aa-ms = <0x1e>;
  6266. ftech,fw-delay-55-ms = <0x1e>;
  6267. ftech,fw-upgrade-id1 = <0x79>;
  6268. ftech,fw-upgrade-id2 = <0x18>;
  6269. ftech,fw-delay-readid-ms = <0xa>;
  6270. ftech,fw-delay-era-flsh-ms = <0x7d0>;
  6271. ftech,fw-auto-cal;
  6272. ftech,ignore-id-check;
  6273. };
  6274.  
  6275. atmel_mxt_ts@4a {
  6276. compatible = "atmel,mxt-ts";
  6277. reg = <0x4a>;
  6278. interrupt-parent = <0xbe>;
  6279. interrupts = <0x41 0x2008>;
  6280. vdd-supply = <0xde>;
  6281. vcc_i2c-supply = <0xe1>;
  6282. pinctrl-names = "pmx_ts_active", "pmx_ts_suspend", "pmx_ts_release";
  6283. pinctrl-0 = <0xe2 0xe3>;
  6284. pinctrl-1 = <0xe4 0xe5>;
  6285. pinctrl-2 = <0xe6>;
  6286. atmel,reset-gpio = <0xbe 0x40 0x0>;
  6287. atmel,irq-gpio = <0xbe 0x41 0x2008>;
  6288. atmel,mxt-fw-name = "mxt_308u.fw";
  6289. atmel,config-array-size = <0x1>;
  6290. atmel,default-config = <0x0>;
  6291. atmel,irqflags = <0x2008>;
  6292. atmel,vendor-id-byte = [00 03];
  6293.  
  6294. atmel,cfg_1 {
  6295. atmel,family-id = <0xa6>;
  6296. atmel,variant-id = <0x7>;
  6297. atmel,version = <0x10>;
  6298. atmel,build = <0xab>;
  6299. atmel,rev-id = <0x2>;
  6300. atmel,panel-id = <0x31>;
  6301. atmel,mxt-cfg-name = "mxt_308u_b5_f.raw";
  6302. atmel,vendor-id = [31 31];
  6303. atmel,key-codes = <0x8b 0xac 0x9e>;
  6304. atmel,selfintthr-stylus = <0x0>;
  6305. atmel,t71-tchthr-pos = <0x16>;
  6306. atmel,self-chgtime-min = <0x0>;
  6307. atmel,self-chgtime-max = <0x0>;
  6308. atmel,mult-intthr-sensitive = <0xc>;
  6309. atmel,mult-intthr-not-sensitive = <0x11>;
  6310. atmel,atchthr-sensitive = <0x6>;
  6311. atmel,mult-tchthr-sensitive = <0x0>;
  6312. atmel,mult-tchthr-not-sensitive = <0x0>;
  6313. atmel,wake-up-self-adcx = <0x10>;
  6314. atmel,support-wakeup-gesture;
  6315. };
  6316. };
  6317. };
  6318.  
  6319. i2c@7af5000 {
  6320. compatible = "qcom,i2c-msm-v2";
  6321. #address-cells = <0x1>;
  6322. #size-cells = <0x0>;
  6323. reg-names = "qup_phys_addr";
  6324. reg = <0x7af5000 0x600>;
  6325. interrupt-names = "qup_irq";
  6326. interrupts = <0x0 0x12b 0x0>;
  6327. qcom,clk-freq-out = <0x61a80>;
  6328. qcom,clk-freq-in = <0x124f800>;
  6329. clock-names = "iface_clk", "core_clk";
  6330. clocks = <0x37 0x8f283c1d 0x37 0x9ace11dd>;
  6331. pinctrl-names = "i2c_active", "i2c_sleep";
  6332. pinctrl-0 = <0xe7>;
  6333. pinctrl-1 = <0xe8>;
  6334. qcom,noise-rjct-scl = <0x0>;
  6335. qcom,noise-rjct-sda = <0x0>;
  6336. qcom,master-id = <0x54>;
  6337. dmas = <0xe9 0x4 0x40 0x20000020 0x20 0xe9 0x5 0x20 0x20000020 0x20>;
  6338. dma-names = "tx", "rx";
  6339.  
  6340. nq@28 {
  6341. compatible = "qcom,nq-nci";
  6342. reg = <0x28>;
  6343. qcom,nq-irq = <0xbe 0x11 0x0>;
  6344. qcom,nq-ven = <0xbe 0x10 0x0>;
  6345. qcom,nq-firm = <0xbe 0x3e 0x0>;
  6346. qcom,nq-clkreq = <0xea 0x2 0x0>;
  6347. interrupt-parent = <0xbe>;
  6348. qcom,clk-src = "BBCLK2";
  6349. interrupts = <0x11 0x0>;
  6350. interrupt-names = "nfc_irq";
  6351. pinctrl-names = "nfc_active", "nfc_suspend";
  6352. pinctrl-0 = <0xeb 0xec>;
  6353. pinctrl-1 = <0xed 0xee>;
  6354. clocks = <0x37 0x498938e5>;
  6355. clock-names = "ref_clk";
  6356. };
  6357. };
  6358.  
  6359. slim@c140000 {
  6360. cell-index = <0x1>;
  6361. compatible = "qcom,slim-ngd";
  6362. reg = <0xc140000 0x2c000 0xc104000 0x2a000>;
  6363. reg-names = "slimbus_physical", "slimbus_bam_physical";
  6364. interrupts = <0x0 0xa3 0x0 0x0 0xb4 0x0>;
  6365. interrupt-names = "slimbus_irq", "slimbus_bam_irq";
  6366. qcom,apps-ch-pipes = <0x600000>;
  6367. qcom,ea-pc = <0x200>;
  6368. status = "disabled";
  6369.  
  6370. msm_dai_slim {
  6371. status = "disabled";
  6372. compatible = "qcom,msm-dai-slim";
  6373. elemental-addr = [ff ff ff fe 17 02];
  6374. };
  6375.  
  6376. tasha_codec {
  6377. status = "disabled";
  6378. compatible = "qcom,tasha-slim-pgd";
  6379. elemental-addr = [00 01 a0 01 17 02];
  6380. interrupt-parent = <0xef>;
  6381. interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e>;
  6382. qcom,wcd-rst-gpio-node = <0xf0>;
  6383. clock-names = "wcd_clk", "wcd_native_clk";
  6384. clocks = <0xf1 0xb7ba2274 0xf1 0xf0fbaf5b>;
  6385. qcom,cdc-static-supplies = "cdc-vdd-buck", "cdc-buck-sido", "cdc-vdd-tx-h", "cdc-vdd-rx-h", "cdc-vdd-px";
  6386. qcom,cdc-on-demand-supplies = "cdc-vdd-mic-bias";
  6387. qcom,cdc-micbias1-mv = <0x708>;
  6388. qcom,cdc-micbias2-mv = <0x708>;
  6389. qcom,cdc-micbias3-mv = <0x708>;
  6390. qcom,cdc-micbias4-mv = <0x708>;
  6391. qcom,cdc-mclk-clk-rate = <0x927c00>;
  6392. qcom,cdc-slim-ifd = "tasha-slim-ifd";
  6393. qcom,cdc-slim-ifd-elemental-addr = [00 00 a0 01 17 02];
  6394. qcom,cdc-dmic-sample-rate = <0x249f00>;
  6395. qcom,cdc-reset-gpio = <0xbe 0x43 0x0>;
  6396. cdc-vdd-buck-supply = <0xf2>;
  6397. qcom,cdc-vdd-buck-voltage = <0x1b7740 0x1b7740>;
  6398. qcom,cdc-vdd-buck-current = <0x9eb10>;
  6399. cdc-buck-sido-supply = <0xf2>;
  6400. qcom,cdc-buck-sido-voltage = <0x1b7740 0x1b7740>;
  6401. qcom,cdc-buck-sido-current = <0x249f0>;
  6402. cdc-vdd-tx-h-supply = <0xf2>;
  6403. qcom,cdc-vdd-tx-h-voltage = <0x1b7740 0x1b7740>;
  6404. qcom,cdc-vdd-tx-h-current = <0x61a8>;
  6405. cdc-vdd-rx-h-supply = <0xf2>;
  6406. qcom,cdc-vdd-rx-h-voltage = <0x1b7740 0x1b7740>;
  6407. qcom,cdc-vdd-rx-h-current = <0x61a8>;
  6408. cdc-vdd-px-supply = <0xf2>;
  6409. qcom,cdc-vdd-px-voltage = <0x1b7740 0x1b7740>;
  6410. qcom,cdc-vdd-px-current = <0x2710>;
  6411. cdc-vdd-mic-bias-supply = <0xf3>;
  6412. qcom,cdc-vdd-mic-bias-voltage = <0x2faf08 0x2faf08>;
  6413. qcom,cdc-vdd-mic-bias-current = <0x3a98>;
  6414.  
  6415. swr_master {
  6416. compatible = "qcom,swr-wcd";
  6417. #address-cells = <0x2>;
  6418. #size-cells = <0x0>;
  6419.  
  6420. wsa881x@20170211 {
  6421. compatible = "qcom,wsa881x";
  6422. reg = <0x0 0x20170211>;
  6423. qcom,spkr-sd-n-gpio = <0xbe 0x60 0x0>;
  6424. linux,phandle = <0x16f>;
  6425. phandle = <0x16f>;
  6426. };
  6427.  
  6428. wsa881x@20170212 {
  6429. compatible = "qcom,wsa881x";
  6430. reg = <0x0 0x20170212>;
  6431. qcom,spkr-sd-n-gpio = <0xbe 0x60 0x0>;
  6432. linux,phandle = <0x170>;
  6433. phandle = <0x170>;
  6434. };
  6435.  
  6436. wsa881x@21170213 {
  6437. compatible = "qcom,wsa881x";
  6438. reg = <0x0 0x21170213>;
  6439. qcom,spkr-sd-n-gpio = <0xbe 0x60 0x0>;
  6440. linux,phandle = <0x171>;
  6441. phandle = <0x171>;
  6442. };
  6443.  
  6444. wsa881x@21170214 {
  6445. compatible = "qcom,wsa881x";
  6446. reg = <0x0 0x21170214>;
  6447. qcom,spkr-sd-n-gpio = <0xbe 0x60 0x0>;
  6448. linux,phandle = <0x172>;
  6449. phandle = <0x172>;
  6450. };
  6451. };
  6452. };
  6453. };
  6454.  
  6455. dcc@b3000 {
  6456. compatible = "qcom,dcc";
  6457. reg = <0xb3000 0x1000 0xb4000 0x800>;
  6458. reg-names = "dcc-base", "dcc-ram-base";
  6459. clocks = <0x37 0xd1000c50>;
  6460. clock-names = "dcc_clk";
  6461. qcom,save-reg;
  6462. };
  6463.  
  6464. qcom,gcc@1800000 {
  6465. compatible = "qcom,gcc-8953";
  6466. reg = <0x1800000 0x80000>;
  6467. reg-names = "cc_base";
  6468. vdd_dig-supply = <0xf4>;
  6469. #clock-cells = <0x1>;
  6470. linux,phandle = <0x37>;
  6471. phandle = <0x37>;
  6472. };
  6473.  
  6474. qcom,gcc-mdss@1800000 {
  6475. compatible = "qcom,gcc-mdss-8953";
  6476. reg = <0x1800000 0x80000>;
  6477. reg-names = "cc_base";
  6478. clock-names = "pclk0_src", "pclk1_src", "byte0_src", "byte1_src";
  6479. clocks = <0xf5 0x792379e1 0xf6 0x36458019 0xf5 0x60e83f06 0xf6 0xb5a42b7b>;
  6480. #clock-cells = <0x1>;
  6481. linux,phandle = <0x195>;
  6482. phandle = <0x195>;
  6483. };
  6484.  
  6485. qcom,cc-debug@1874000 {
  6486. compatible = "qcom,cc-debug-8953";
  6487. reg = <0x1874000 0x4>;
  6488. reg-names = "cc_base";
  6489. clocks = <0xb3 0x61a2945f>;
  6490. clock-names = "debug_cpu_clk";
  6491. #clock-cells = <0x1>;
  6492. linux,phandle = <0x101>;
  6493. phandle = <0x101>;
  6494. };
  6495.  
  6496. qcom,gcc-gfx@1800000 {
  6497. compatible = "qcom,gcc-gfx-8953";
  6498. reg = <0x1800000 0x80000>;
  6499. reg-names = "cc_base";
  6500. vdd_gfx-supply = <0xc8>;
  6501. qcom,gfxfreq-corner = <0x0 0x0 0x7f27450 0x1 0xcdfe600 0x2 0x1312d000 0x3 0x17d78400 0x4 0x1e65fb80 0x5 0x2160ec00 0x6 0x26be3680 0x7>;
  6502. #clock-cells = <0x1>;
  6503. linux,phandle = <0x38>;
  6504. phandle = <0x38>;
  6505. };
  6506.  
  6507. qcom,cpu-clock-8953@b116000 {
  6508. compatible = "qcom,cpu-clock-8953";
  6509. reg = <0xb114000 0x68 0xb014000 0x68 0xb116000 0x400 0xb111050 0x8 0xb011050 0x8 0xb1d1050 0x8 0xa4124 0x8>;
  6510. reg-names = "rcgwr-c0-base", "rcgwr-c1-base", "c0-pll", "c0-mux", "c1-mux", "cci-mux", "efuse";
  6511. vdd-mx-supply = <0xf7>;
  6512. vdd-cl-supply = <0xf8>;
  6513. clocks = <0x37 0x2fdd2c7c>;
  6514. clock-names = "xo_a";
  6515. qcom,num-clusters = <0x2>;
  6516. qcom,speed0-bin-v0-cl = <0x0 0x0 0x26e8f000 0x1 0x3dcc5000 0x2 0x538ab800 0x3 0x64b54000 0x4 0x6ddd0000 0x5 0x74bad000 0x6 0x7829b800 0x7>;
  6517. qcom,speed0-bin-v0-cci = <0x0 0x0 0xf906000 0x1 0x18b82000 0x2 0x216ab000 0x3 0x28488000 0x4 0x2bf20000 0x5 0x2eb12000 0x6 0x3010b000 0x7>;
  6518. qcom,speed2-bin-v0-cl = <0x0 0x0 0x26e8f000 0x1 0x3dcc5000 0x2 0x538ab800 0x3 0x64b54000 0x4 0x6ddd0000 0x5 0x74bad000 0x6 0x7829b800 0x7>;
  6519. qcom,speed2-bin-v0-cci = <0x0 0x0 0xf906000 0x1 0x18b82000 0x2 0x216ab000 0x3 0x28488000 0x4 0x2bf20000 0x5 0x2eb12000 0x6 0x3010b000 0x7>;
  6520. qcom,speed7-bin-v0-cl = <0x0 0x0 0x26e8f000 0x1 0x3dcc5000 0x2 0x538ab800 0x3 0x64b54000 0x4 0x6ddd0000 0x5 0x74bad000 0x6 0x7829b800 0x7 0x802c8000 0x8 0x839b6800 0x9>;
  6521. qcom,speed7-bin-v0-cci = <0x0 0x0 0xf906000 0x1 0x18b82000 0x2 0x216ab000 0x3 0x28488000 0x4 0x2bf20000 0x5 0x2eb12000 0x6 0x3010b000 0x7 0x33450000 0x8 0x34a49000 0x9>;
  6522. #clock-cells = <0x1>;
  6523. linux,phandle = <0xb3>;
  6524. phandle = <0xb3>;
  6525. };
  6526.  
  6527. qcom,msm-cpufreq {
  6528. compatible = "qcom,msm-cpufreq";
  6529. clock-names = "l2_clk", "cpu0_clk", "cpu1_clk", "cpu2_clk", "cpu3_clk", "cpu4_clk", "cpu5_clk", "cpu6_clk", "cpu7_clk";
  6530. clocks = <0xb3 0x96854074 0xb3 0x2e6af930 0xb3 0x2e6af930 0xb3 0x2e6af930 0xb3 0x2e6af930 0xb3 0x2e6af930 0xb3 0x2e6af930 0xb3 0x2e6af930 0xb3 0x2e6af930>;
  6531. qcom,cpufreq-table = <0x9f600 0xfd200 0x156300 0x19c800 0x1c2000 0x1de200 0x1ec300 0x20d000 0x21b100>;
  6532. };
  6533.  
  6534. qcom,cpubw {
  6535. compatible = "qcom,devbw";
  6536. governor = "cpufreq";
  6537. qcom,src-dst-ports = <0x1 0x200>;
  6538. qcom,active-only;
  6539. qcom,bw-tbl = <0x301 0x64b 0x84c 0xb71 0xc95 0x1098 0x1406 0x16e3 0x1808 0x192d 0x1bc0>;
  6540. linux,phandle = <0xf9>;
  6541. phandle = <0xf9>;
  6542. };
  6543.  
  6544. qcom,mincpubw {
  6545. compatible = "qcom,devbw";
  6546. governor = "cpufreq";
  6547. qcom,src-dst-ports = <0x1 0x200>;
  6548. qcom,active-only;
  6549. qcom,bw-tbl = <0x301 0x64b 0x84c 0xb71 0xc95 0x1098 0x1406 0x16e3 0x1808 0x192d 0x1bc0>;
  6550. linux,phandle = <0xfa>;
  6551. phandle = <0xfa>;
  6552. };
  6553.  
  6554. qcom,cpu-bwmon {
  6555. compatible = "qcom,bimc-bwmon2";
  6556. reg = <0x408000 0x300 0x401000 0x200>;
  6557. reg-names = "base", "global_base";
  6558. interrupts = <0x0 0xb7 0x4>;
  6559. qcom,mport = <0x0>;
  6560. qcom,target-dev = <0xf9>;
  6561. };
  6562.  
  6563. devfreq-cpufreq {
  6564.  
  6565. cpubw-cpufreq {
  6566. target-dev = <0xf9>;
  6567. cpu-to-dev-map = <0x9f600 0x64b 0xfd200 0xc95 0x156300 0x16e3 0x19c800 0x192d 0x1c2000 0x1bc0 0x1de200 0x1bc0 0x21b100 0x1bc0>;
  6568. };
  6569.  
  6570. mincpubw-cpufreq {
  6571. target-dev = <0xfa>;
  6572. cpu-to-dev-map = <0x9f600 0x64b 0x156300 0xc95 0x21b100 0x16e3>;
  6573. };
  6574. };
  6575.  
  6576. qcom,rpm-smd {
  6577. compatible = "qcom,rpm-smd";
  6578. rpm-channel-name = "rpm_requests";
  6579. rpm-channel-type = <0xf>;
  6580.  
  6581. rpm-regulator-smpa1 {
  6582. compatible = "qcom,rpm-smd-regulator-resource";
  6583. qcom,resource-name = "smpa";
  6584. qcom,resource-id = <0x1>;
  6585. qcom,regulator-type = <0x1>;
  6586. qcom,hpm-min-load = <0x186a0>;
  6587. status = "okay";
  6588.  
  6589. regulator-s1 {
  6590. compatible = "qcom,rpm-smd-regulator";
  6591. regulator-name = "pm8953_s1";
  6592. qcom,set = <0x3>;
  6593. status = "okay";
  6594. regulator-min-microvolt = <0xd4670>;
  6595. regulator-max-microvolt = <0x11a3a0>;
  6596. qcom,init-voltage = <0xf4240>;
  6597. linux,phandle = <0x11e>;
  6598. phandle = <0x11e>;
  6599. };
  6600. };
  6601.  
  6602. rpm-regulator-smpa2 {
  6603. compatible = "qcom,rpm-smd-regulator-resource";
  6604. qcom,resource-name = "smpa";
  6605. qcom,resource-id = <0x2>;
  6606. qcom,regulator-type = <0x1>;
  6607. qcom,hpm-min-load = <0x186a0>;
  6608. status = "okay";
  6609.  
  6610. regulator-s2 {
  6611. compatible = "qcom,rpm-smd-regulator";
  6612. regulator-name = "pm8953_s2";
  6613. qcom,set = <0x3>;
  6614. status = "disabled";
  6615. };
  6616.  
  6617. regulator-s2-level {
  6618. compatible = "qcom,rpm-smd-regulator";
  6619. regulator-name = "pm8953_s2_level";
  6620. qcom,set = <0x3>;
  6621. regulator-min-microvolt = <0x10>;
  6622. regulator-max-microvolt = <0x180>;
  6623. qcom,use-voltage-level;
  6624. linux,phandle = <0xf4>;
  6625. phandle = <0xf4>;
  6626. };
  6627.  
  6628. regulator-s2-floor-level {
  6629. compatible = "qcom,rpm-smd-regulator";
  6630. regulator-name = "pm8953_s2_floor_level";
  6631. qcom,set = <0x3>;
  6632. regulator-min-microvolt = <0x10>;
  6633. regulator-max-microvolt = <0x180>;
  6634. qcom,use-voltage-floor-level;
  6635. qcom,always-send-voltage;
  6636. linux,phandle = <0xc7>;
  6637. phandle = <0xc7>;
  6638. };
  6639.  
  6640. regulator-s2-level-ao {
  6641. compatible = "qcom,rpm-smd-regulator";
  6642. regulator-name = "pm8953_s2_level_ao";
  6643. qcom,set = <0x1>;
  6644. regulator-min-microvolt = <0x10>;
  6645. regulator-max-microvolt = <0x180>;
  6646. qcom,use-voltage-level;
  6647. };
  6648. };
  6649.  
  6650. rpm-regulator-smpa3 {
  6651. compatible = "qcom,rpm-smd-regulator-resource";
  6652. qcom,resource-name = "smpa";
  6653. qcom,resource-id = <0x3>;
  6654. qcom,regulator-type = <0x1>;
  6655. qcom,hpm-min-load = <0x186a0>;
  6656. status = "okay";
  6657.  
  6658. regulator-s3 {
  6659. compatible = "qcom,rpm-smd-regulator";
  6660. regulator-name = "pm8953_s3";
  6661. qcom,set = <0x3>;
  6662. status = "okay";
  6663. regulator-min-microvolt = <0x12b128>;
  6664. regulator-max-microvolt = <0x12b128>;
  6665. qcom,init-voltage = <0x12b128>;
  6666. linux,phandle = <0x179>;
  6667. phandle = <0x179>;
  6668. };
  6669. };
  6670.  
  6671. rpm-regulator-smpa4 {
  6672. compatible = "qcom,rpm-smd-regulator-resource";
  6673. qcom,resource-name = "smpa";
  6674. qcom,resource-id = <0x4>;
  6675. qcom,regulator-type = <0x1>;
  6676. qcom,hpm-min-load = <0x186a0>;
  6677. status = "okay";
  6678.  
  6679. regulator-s4 {
  6680. compatible = "qcom,rpm-smd-regulator";
  6681. regulator-name = "pm8953_s4";
  6682. qcom,set = <0x3>;
  6683. status = "okay";
  6684. regulator-min-microvolt = <0x1cfde0>;
  6685. regulator-max-microvolt = <0x1f47d0>;
  6686. qcom,init-voltage = <0x1cfde0>;
  6687. linux,phandle = <0x11b>;
  6688. phandle = <0x11b>;
  6689. };
  6690. };
  6691.  
  6692. rpm-regulator-smpa7 {
  6693. compatible = "qcom,rpm-smd-regulator-resource";
  6694. qcom,resource-name = "smpa";
  6695. qcom,resource-id = <0x7>;
  6696. qcom,regulator-type = <0x1>;
  6697. qcom,hpm-min-load = <0x186a0>;
  6698. status = "okay";
  6699.  
  6700. regulator-s7 {
  6701. compatible = "qcom,rpm-smd-regulator";
  6702. regulator-name = "pm8953_s7";
  6703. qcom,set = <0x3>;
  6704. status = "disabled";
  6705. };
  6706.  
  6707. regulator-s7-level {
  6708. compatible = "qcom,rpm-smd-regulator";
  6709. regulator-name = "pm8953_s7_level";
  6710. qcom,set = <0x3>;
  6711. regulator-min-microvolt = <0x10>;
  6712. regulator-max-microvolt = <0x180>;
  6713. qcom,init-voltage-level = <0x10>;
  6714. qcom,use-voltage-level;
  6715. qcom,always-send-voltage;
  6716. };
  6717.  
  6718. regulator-s7-level-ao {
  6719. compatible = "qcom,rpm-smd-regulator";
  6720. regulator-name = "pm8953_s7_level_ao";
  6721. qcom,set = <0x1>;
  6722. regulator-min-microvolt = <0x10>;
  6723. regulator-max-microvolt = <0x180>;
  6724. qcom,use-voltage-level;
  6725. qcom,always-send-voltage;
  6726. linux,phandle = <0xf7>;
  6727. phandle = <0xf7>;
  6728. };
  6729.  
  6730. regulator-s7-level-so {
  6731. compatible = "qcom,rpm-smd-regulator";
  6732. regulator-name = "pm8953_s7_level_so";
  6733. qcom,set = <0x2>;
  6734. regulator-min-microvolt = <0x10>;
  6735. regulator-max-microvolt = <0x180>;
  6736. qcom,init-voltage-level = <0x10>;
  6737. qcom,use-voltage-level;
  6738. };
  6739. };
  6740.  
  6741. rpm-regulator-ldoa1 {
  6742. compatible = "qcom,rpm-smd-regulator-resource";
  6743. qcom,resource-name = "ldoa";
  6744. qcom,resource-id = <0x1>;
  6745. qcom,regulator-type = <0x0>;
  6746. qcom,hpm-min-load = <0x2710>;
  6747. status = "okay";
  6748.  
  6749. regulator-l1 {
  6750. compatible = "qcom,rpm-smd-regulator";
  6751. regulator-name = "pm8953_l1";
  6752. qcom,set = <0x3>;
  6753. status = "okay";
  6754. regulator-min-microvolt = <0xf4240>;
  6755. regulator-max-microvolt = <0xf4240>;
  6756. qcom,init-voltage = <0xf4240>;
  6757. };
  6758. };
  6759.  
  6760. rpm-regulator-ldoa2 {
  6761. compatible = "qcom,rpm-smd-regulator-resource";
  6762. qcom,resource-name = "ldoa";
  6763. qcom,resource-id = <0x2>;
  6764. qcom,regulator-type = <0x0>;
  6765. qcom,hpm-min-load = <0x2710>;
  6766. status = "okay";
  6767.  
  6768. regulator-l2 {
  6769. compatible = "qcom,rpm-smd-regulator";
  6770. regulator-name = "pm8953_l2";
  6771. qcom,set = <0x3>;
  6772. status = "okay";
  6773. regulator-min-microvolt = <0xee098>;
  6774. regulator-max-microvolt = <0x12b128>;
  6775. qcom,init-voltage = <0xee098>;
  6776. linux,phandle = <0x184>;
  6777. phandle = <0x184>;
  6778. };
  6779. };
  6780.  
  6781. rpm-regulator-ldoa3 {
  6782. compatible = "qcom,rpm-smd-regulator-resource";
  6783. qcom,resource-name = "ldoa";
  6784. qcom,resource-id = <0x3>;
  6785. qcom,regulator-type = <0x0>;
  6786. qcom,hpm-min-load = <0x2710>;
  6787. status = "okay";
  6788.  
  6789. regulator-l3 {
  6790. compatible = "qcom,rpm-smd-regulator";
  6791. regulator-name = "pm8953_l3";
  6792. qcom,set = <0x3>;
  6793. status = "okay";
  6794. regulator-min-microvolt = <0xe1d48>;
  6795. regulator-max-microvolt = <0xe1d48>;
  6796. qcom,init-voltage = <0xe1d48>;
  6797. linux,phandle = <0x12d>;
  6798. phandle = <0x12d>;
  6799. };
  6800. };
  6801.  
  6802. rpm-regulator-ldoa5 {
  6803. compatible = "qcom,rpm-smd-regulator-resource";
  6804. qcom,resource-name = "ldoa";
  6805. qcom,resource-id = <0x5>;
  6806. qcom,regulator-type = <0x0>;
  6807. qcom,hpm-min-load = <0x2710>;
  6808. status = "okay";
  6809.  
  6810. regulator-l5 {
  6811. compatible = "qcom,rpm-smd-regulator";
  6812. regulator-name = "pm8953_l5";
  6813. qcom,set = <0x3>;
  6814. status = "okay";
  6815. regulator-min-microvolt = <0x1b7740>;
  6816. regulator-max-microvolt = <0x1b7740>;
  6817. qcom,init-voltage = <0x1b7740>;
  6818. linux,phandle = <0xe1>;
  6819. phandle = <0xe1>;
  6820. };
  6821. };
  6822.  
  6823. rpm-regulator-ldoa6 {
  6824. compatible = "qcom,rpm-smd-regulator-resource";
  6825. qcom,resource-name = "ldoa";
  6826. qcom,resource-id = <0x6>;
  6827. qcom,regulator-type = <0x0>;
  6828. qcom,hpm-min-load = <0x2710>;
  6829. status = "okay";
  6830.  
  6831. regulator-l6 {
  6832. compatible = "qcom,rpm-smd-regulator";
  6833. regulator-name = "pm8953_l6";
  6834. qcom,set = <0x3>;
  6835. status = "okay";
  6836. regulator-min-microvolt = <0x1b7740>;
  6837. regulator-max-microvolt = <0x1b7740>;
  6838. qcom,init-voltage = <0x1b7740>;
  6839. regulator-always-on;
  6840. linux,phandle = <0x185>;
  6841. phandle = <0x185>;
  6842. };
  6843. };
  6844.  
  6845. rpm-regulator-ldoa7 {
  6846. compatible = "qcom,rpm-smd-regulator-resource";
  6847. qcom,resource-name = "ldoa";
  6848. qcom,resource-id = <0x7>;
  6849. qcom,regulator-type = <0x0>;
  6850. qcom,hpm-min-load = <0x2710>;
  6851. status = "okay";
  6852.  
  6853. regulator-l7 {
  6854. compatible = "qcom,rpm-smd-regulator";
  6855. regulator-name = "pm8953_l7";
  6856. qcom,set = <0x3>;
  6857. status = "okay";
  6858. regulator-min-microvolt = <0x1b7740>;
  6859. regulator-max-microvolt = <0x1cfde0>;
  6860. qcom,init-voltage = <0x1b7740>;
  6861. linux,phandle = <0xfb>;
  6862. phandle = <0xfb>;
  6863. };
  6864.  
  6865. regulator-l7-ao {
  6866. compatible = "qcom,rpm-smd-regulator";
  6867. regulator-name = "pm8953_l7_ao";
  6868. qcom,set = <0x1>;
  6869. regulator-min-microvolt = <0x1b7740>;
  6870. regulator-max-microvolt = <0x1cfde0>;
  6871. qcom,init-voltage = <0x1b7740>;
  6872. };
  6873. };
  6874.  
  6875. rpm-regulator-ldoa8 {
  6876. compatible = "qcom,rpm-smd-regulator-resource";
  6877. qcom,resource-name = "ldoa";
  6878. qcom,resource-id = <0x8>;
  6879. qcom,regulator-type = <0x0>;
  6880. qcom,hpm-min-load = <0x2710>;
  6881. status = "okay";
  6882.  
  6883. regulator-l8 {
  6884. compatible = "qcom,rpm-smd-regulator";
  6885. regulator-name = "pm8953_l8";
  6886. qcom,set = <0x3>;
  6887. status = "okay";
  6888. regulator-min-microvolt = <0x2c4020>;
  6889. regulator-max-microvolt = <0x2c4020>;
  6890. qcom,init-voltage = <0x2c4020>;
  6891. linux,phandle = <0x106>;
  6892. phandle = <0x106>;
  6893. };
  6894. };
  6895.  
  6896. rpm-regulator-ldoa9 {
  6897. compatible = "qcom,rpm-smd-regulator-resource";
  6898. qcom,resource-name = "ldoa";
  6899. qcom,resource-id = <0x9>;
  6900. qcom,regulator-type = <0x0>;
  6901. qcom,hpm-min-load = <0x2710>;
  6902. status = "okay";
  6903.  
  6904. regulator-l9 {
  6905. compatible = "qcom,rpm-smd-regulator";
  6906. regulator-name = "pm8953_l9";
  6907. qcom,set = <0x3>;
  6908. status = "okay";
  6909. regulator-min-microvolt = <0x2dc6c0>;
  6910. regulator-max-microvolt = <0x325aa0>;
  6911. qcom,init-voltage = <0x2dc6c0>;
  6912. linux,phandle = <0xfd>;
  6913. phandle = <0xfd>;
  6914. };
  6915. };
  6916.  
  6917. rpm-regulator-ldoa10 {
  6918. compatible = "qcom,rpm-smd-regulator-resource";
  6919. qcom,resource-name = "ldoa";
  6920. qcom,resource-id = <0xa>;
  6921. qcom,regulator-type = <0x0>;
  6922. qcom,hpm-min-load = <0x2710>;
  6923. status = "okay";
  6924.  
  6925. regulator-l10 {
  6926. compatible = "qcom,rpm-smd-regulator";
  6927. regulator-name = "pm8953_l10";
  6928. qcom,set = <0x3>;
  6929. status = "okay";
  6930. regulator-min-microvolt = <0x2b7cd0>;
  6931. regulator-max-microvolt = <0x2b7cd0>;
  6932. qcom,init-voltage = <0x2b7cd0>;
  6933. linux,phandle = <0xde>;
  6934. phandle = <0xde>;
  6935. };
  6936. };
  6937.  
  6938. rpm-regulator-ldoa11 {
  6939. compatible = "qcom,rpm-smd-regulator-resource";
  6940. qcom,resource-name = "ldoa";
  6941. qcom,resource-id = <0xb>;
  6942. qcom,regulator-type = <0x0>;
  6943. qcom,hpm-min-load = <0x2710>;
  6944. status = "okay";
  6945.  
  6946. regulator-l11 {
  6947. compatible = "qcom,rpm-smd-regulator";
  6948. regulator-name = "pm8953_l11";
  6949. qcom,set = <0x3>;
  6950. status = "okay";
  6951. regulator-min-microvolt = <0x2d0370>;
  6952. regulator-max-microvolt = <0x2d0370>;
  6953. qcom,init-voltage = <0x2d0370>;
  6954. linux,phandle = <0x6a>;
  6955. phandle = <0x6a>;
  6956. };
  6957. };
  6958.  
  6959. rpm-regulator-ldoa12 {
  6960. compatible = "qcom,rpm-smd-regulator-resource";
  6961. qcom,resource-name = "ldoa";
  6962. qcom,resource-id = <0xc>;
  6963. qcom,regulator-type = <0x0>;
  6964. qcom,hpm-min-load = <0x2710>;
  6965. status = "okay";
  6966.  
  6967. regulator-l12 {
  6968. compatible = "qcom,rpm-smd-regulator";
  6969. regulator-name = "pm8953_l12";
  6970. qcom,set = <0x3>;
  6971. status = "okay";
  6972. regulator-min-microvolt = <0x1b7740>;
  6973. regulator-max-microvolt = <0x2d0370>;
  6974. qcom,init-voltage = <0x1b7740>;
  6975. linux,phandle = <0x6b>;
  6976. phandle = <0x6b>;
  6977. };
  6978. };
  6979.  
  6980. rpm-regulator-ldoa13 {
  6981. compatible = "qcom,rpm-smd-regulator-resource";
  6982. qcom,resource-name = "ldoa";
  6983. qcom,resource-id = <0xd>;
  6984. qcom,regulator-type = <0x0>;
  6985. qcom,hpm-min-load = <0x1388>;
  6986. status = "okay";
  6987.  
  6988. regulator-l13 {
  6989. compatible = "qcom,rpm-smd-regulator";
  6990. regulator-name = "pm8953_l13";
  6991. qcom,set = <0x3>;
  6992. status = "okay";
  6993. regulator-min-microvolt = <0x2faf08>;
  6994. regulator-max-microvolt = <0x2faf08>;
  6995. qcom,init-voltage = <0x2faf08>;
  6996. linux,phandle = <0xf3>;
  6997. phandle = <0xf3>;
  6998. };
  6999. };
  7000.  
  7001. rpm-regulator-ldoa16 {
  7002. compatible = "qcom,rpm-smd-regulator-resource";
  7003. qcom,resource-name = "ldoa";
  7004. qcom,resource-id = <0x10>;
  7005. qcom,regulator-type = <0x0>;
  7006. qcom,hpm-min-load = <0x1388>;
  7007. status = "okay";
  7008.  
  7009. regulator-l16 {
  7010. compatible = "qcom,rpm-smd-regulator";
  7011. regulator-name = "pm8953_l16";
  7012. qcom,set = <0x3>;
  7013. status = "okay";
  7014. regulator-min-microvolt = <0x1b7740>;
  7015. regulator-max-microvolt = <0x1b7740>;
  7016. qcom,init-voltage = <0x1b7740>;
  7017. };
  7018. };
  7019.  
  7020. rpm-regulator-ldoa17 {
  7021. compatible = "qcom,rpm-smd-regulator-resource";
  7022. qcom,resource-name = "ldoa";
  7023. qcom,resource-id = <0x11>;
  7024. qcom,regulator-type = <0x0>;
  7025. qcom,hpm-min-load = <0x2710>;
  7026. status = "okay";
  7027.  
  7028. regulator-l17 {
  7029. compatible = "qcom,rpm-smd-regulator";
  7030. regulator-name = "pm8953_l17";
  7031. qcom,set = <0x3>;
  7032. status = "okay";
  7033. regulator-min-microvolt = <0x2b7cd0>;
  7034. regulator-max-microvolt = <0x2b7cd0>;
  7035. qcom,init-voltage = <0x2b7cd0>;
  7036. linux,phandle = <0x183>;
  7037. phandle = <0x183>;
  7038. };
  7039. };
  7040.  
  7041. rpm-regulator-ldoa19 {
  7042. compatible = "qcom,rpm-smd-regulator-resource";
  7043. qcom,resource-name = "ldoa";
  7044. qcom,resource-id = <0x13>;
  7045. qcom,regulator-type = <0x0>;
  7046. qcom,hpm-min-load = <0x2710>;
  7047. status = "okay";
  7048.  
  7049. regulator-l19 {
  7050. compatible = "qcom,rpm-smd-regulator";
  7051. regulator-name = "pm8953_l19";
  7052. qcom,set = <0x3>;
  7053. status = "okay";
  7054. regulator-min-microvolt = <0x124f80>;
  7055. regulator-max-microvolt = <0x149970>;
  7056. qcom,init-voltage = <0x124f80>;
  7057. linux,phandle = <0xfc>;
  7058. phandle = <0xfc>;
  7059. };
  7060. };
  7061.  
  7062. rpm-regulator-ldoa22 {
  7063. compatible = "qcom,rpm-smd-regulator-resource";
  7064. qcom,resource-name = "ldoa";
  7065. qcom,resource-id = <0x16>;
  7066. qcom,regulator-type = <0x0>;
  7067. qcom,hpm-min-load = <0x2710>;
  7068. status = "okay";
  7069.  
  7070. regulator-l22 {
  7071. compatible = "qcom,rpm-smd-regulator";
  7072. regulator-name = "pm8953_l22";
  7073. qcom,set = <0x3>;
  7074. status = "okay";
  7075. regulator-min-microvolt = <0x2ab980>;
  7076. regulator-max-microvolt = <0x2ab980>;
  7077. qcom,init-voltage = <0x2ab980>;
  7078. linux,phandle = <0x186>;
  7079. phandle = <0x186>;
  7080. };
  7081. };
  7082.  
  7083. rpm-regulator-ldoa23 {
  7084. compatible = "qcom,rpm-smd-regulator-resource";
  7085. qcom,resource-name = "ldoa";
  7086. qcom,resource-id = <0x17>;
  7087. qcom,regulator-type = <0x0>;
  7088. qcom,hpm-min-load = <0x2710>;
  7089. status = "okay";
  7090.  
  7091. regulator-l23 {
  7092. compatible = "qcom,rpm-smd-regulator";
  7093. regulator-name = "pm8953_l23";
  7094. qcom,set = <0x3>;
  7095. status = "okay";
  7096. regulator-min-microvolt = <0xee098>;
  7097. regulator-max-microvolt = <0x12b128>;
  7098. qcom,init-voltage = <0xee098>;
  7099. linux,phandle = <0x18b>;
  7100. phandle = <0x18b>;
  7101. };
  7102. };
  7103.  
  7104. rpm-regulator-clk0 {
  7105. compatible = "qcom,rpm-smd-regulator-resource";
  7106. qcom,resource-name = "clk0";
  7107. qcom,resource-id = <0x3>;
  7108. qcom,regulator-type = <0x1>;
  7109. status = "disabled";
  7110.  
  7111. regulator-clk0 {
  7112. compatible = "qcom,rpm-smd-regulator";
  7113. regulator-name = "rpm_apc";
  7114. qcom,set = <0x3>;
  7115. status = "disabled";
  7116. };
  7117. };
  7118. };
  7119.  
  7120. qcom,ipc-spinlock@1905000 {
  7121. compatible = "qcom,ipc-spinlock-sfpb";
  7122. reg = <0x1905000 0x8000>;
  7123. qcom,num-locks = <0x8>;
  7124. };
  7125.  
  7126. qcom,smem@86300000 {
  7127. compatible = "qcom,smem";
  7128. reg = <0x86300000 0x100000 0xb011008 0x4 0x60000 0x8000 0x193d000 0x8>;
  7129. reg-names = "smem", "irq-reg-base", "aux-mem1", "smem_targ_info_reg";
  7130. qcom,mpu-enabled;
  7131.  
  7132. qcom,smd-modem {
  7133. compatible = "qcom,smd";
  7134. qcom,smd-edge = <0x0>;
  7135. qcom,smd-irq-offset = <0x0>;
  7136. qcom,smd-irq-bitmask = <0x1000>;
  7137. interrupts = <0x0 0x19 0x1>;
  7138. label = "modem";
  7139. qcom,not-loadable;
  7140. };
  7141.  
  7142. qcom,smsm-modem {
  7143. compatible = "qcom,smsm";
  7144. qcom,smsm-edge = <0x0>;
  7145. qcom,smsm-irq-offset = <0x0>;
  7146. qcom,smsm-irq-bitmask = <0x2000>;
  7147. interrupts = <0x0 0x1a 0x1>;
  7148. };
  7149.  
  7150. qcom,smd-wcnss {
  7151. compatible = "qcom,smd";
  7152. qcom,smd-edge = <0x6>;
  7153. qcom,smd-irq-offset = <0x0>;
  7154. qcom,smd-irq-bitmask = <0x20000>;
  7155. interrupts = <0x0 0x8e 0x1>;
  7156. label = "wcnss";
  7157. };
  7158.  
  7159. qcom,smsm-wcnss {
  7160. compatible = "qcom,smsm";
  7161. qcom,smsm-edge = <0x6>;
  7162. qcom,smsm-irq-offset = <0x0>;
  7163. qcom,smsm-irq-bitmask = <0x80000>;
  7164. interrupts = <0x0 0x90 0x1>;
  7165. };
  7166.  
  7167. qcom,smd-adsp {
  7168. compatible = "qcom,smd";
  7169. qcom,smd-edge = <0x1>;
  7170. qcom,smd-irq-offset = <0x0>;
  7171. qcom,smd-irq-bitmask = <0x100>;
  7172. interrupts = <0x0 0x121 0x1>;
  7173. label = "adsp";
  7174. };
  7175.  
  7176. qcom,smsm-adsp {
  7177. compatible = "qcom,smsm";
  7178. qcom,smsm-edge = <0x1>;
  7179. qcom,smsm-irq-offset = <0x0>;
  7180. qcom,smsm-irq-bitmask = <0x200>;
  7181. interrupts = <0x0 0x122 0x1>;
  7182. };
  7183.  
  7184. qcom,smd-rpm {
  7185. compatible = "qcom,smd";
  7186. qcom,smd-edge = <0xf>;
  7187. qcom,smd-irq-offset = <0x0>;
  7188. qcom,smd-irq-bitmask = <0x1>;
  7189. interrupts = <0x0 0xa8 0x1>;
  7190. label = "rpm";
  7191. qcom,irq-no-suspend;
  7192. qcom,not-loadable;
  7193. };
  7194. };
  7195.  
  7196. qcom,wdt@b017000 {
  7197. compatible = "qcom,msm-watchdog";
  7198. reg = <0xb017000 0x1000>;
  7199. reg-names = "wdt-base";
  7200. interrupts = <0x0 0x3 0x0 0x0 0x4 0x0>;
  7201. qcom,bark-time = <0x2af8>;
  7202. qcom,pet-time = <0x2710>;
  7203. qcom,ipi-ping;
  7204. qcom,wakeup-enable;
  7205. };
  7206.  
  7207. qcom,chd {
  7208. compatible = "qcom,core-hang-detect";
  7209. qcom,threshold-arr = <0xb1880b0 0xb1980b0 0xb1a80b0 0xb1b80b0 0xb0880b0 0xb0980b0 0xb0a80b0 0xb0b80b0>;
  7210. qcom,config-arr = <0xb1880b8 0xb1980b8 0xb1a80b8 0xb1b80b8 0xb0880b8 0xb0980b8 0xb0a80b8 0xb0b80b8>;
  7211. };
  7212.  
  7213. qcom,msm-rtb {
  7214. compatible = "qcom,msm-rtb";
  7215. qcom,rtb-size = <0x100000>;
  7216. };
  7217.  
  7218. qcom,msm-imem@8600000 {
  7219. compatible = "qcom,msm-imem";
  7220. reg = <0x8600000 0x1000>;
  7221. ranges = <0x0 0x8600000 0x1000>;
  7222. #address-cells = <0x1>;
  7223. #size-cells = <0x1>;
  7224.  
  7225. mem_dump_table@10 {
  7226. compatible = "qcom,msm-imem-mem_dump_table";
  7227. reg = <0x10 0x8>;
  7228. };
  7229.  
  7230. dload_type@18 {
  7231. compatible = "qcom,msm-imem-dload-type";
  7232. reg = <0x18 0x4>;
  7233. };
  7234.  
  7235. restart_reason@65c {
  7236. compatible = "qcom,msm-imem-restart_reason";
  7237. reg = <0x65c 0x4>;
  7238. };
  7239.  
  7240. boot_stats@6b0 {
  7241. compatible = "qcom,msm-imem-boot_stats";
  7242. reg = <0x6b0 0x20>;
  7243. };
  7244.  
  7245. pil@94c {
  7246. compatible = "qcom,msm-imem-pil";
  7247. reg = <0x94c 0xc8>;
  7248. };
  7249. };
  7250.  
  7251. qcom,memshare {
  7252. compatible = "qcom,memshare";
  7253.  
  7254. qcom,client_1 {
  7255. compatible = "qcom,memshare-peripheral";
  7256. qcom,peripheral-size = <0x200000>;
  7257. qcom,client-id = <0x0>;
  7258. qcom,allocate-boot-time;
  7259. label = "modem";
  7260. };
  7261.  
  7262. qcom,client_2 {
  7263. compatible = "qcom,memshare-peripheral";
  7264. qcom,peripheral-size = <0x300000>;
  7265. qcom,client-id = <0x2>;
  7266. label = "modem";
  7267. };
  7268.  
  7269. qcom,client_3 {
  7270. compatible = "qcom,memshare-peripheral";
  7271. qcom,peripheral-size = <0x0>;
  7272. qcom,client-id = <0x1>;
  7273. label = "modem";
  7274. };
  7275. };
  7276.  
  7277. jtagfuse@a601c {
  7278. compatible = "qcom,jtag-fuse-v2";
  7279. reg = <0xa601c 0x8>;
  7280. reg-names = "fuse-base";
  7281. };
  7282.  
  7283. snfuse@0xa4128 {
  7284. compatible = "qcom,sn-fuse";
  7285. reg = <0xa4128 0x4>;
  7286. reg-names = "sn-base";
  7287. };
  7288.  
  7289. secbootfuse@0xa41d0 {
  7290. compatible = "qcom,sec-boot-fuse";
  7291. reg = <0xa41d0 0x4>;
  7292. reg-names = "sec-boot-base";
  7293. };
  7294.  
  7295. jtagmm@619c000 {
  7296. compatible = "qcom,jtagv8-mm";
  7297. reg = <0x619c000 0x1000 0x6190000 0x1000>;
  7298. reg-names = "etm-base", "debug-base";
  7299. qcom,coresight-jtagmm-cpu = <0x2>;
  7300. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  7301. clock-names = "core_clk", "core_a_clk";
  7302. };
  7303.  
  7304. jtagmm@619d000 {
  7305. compatible = "qcom,jtagv8-mm";
  7306. reg = <0x619d000 0x1000 0x6192000 0x1000>;
  7307. reg-names = "etm-base", "debug-base";
  7308. qcom,coresight-jtagmm-cpu = <0x3>;
  7309. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  7310. clock-names = "core_clk", "core_a_clk";
  7311. };
  7312.  
  7313. jtagmm@619e000 {
  7314. compatible = "qcom,jtagv8-mm";
  7315. reg = <0x619e000 0x1000 0x6194000 0x1000>;
  7316. reg-names = "etm-base", "debug-base";
  7317. qcom,coresight-jtagmm-cpu = <0x4>;
  7318. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  7319. clock-names = "core_clk", "core_a_clk";
  7320. };
  7321.  
  7322. jtagmm@619f000 {
  7323. compatible = "qcom,jtagv8-mm";
  7324. reg = <0x619f000 0x1000 0x6196000 0x1000>;
  7325. reg-names = "etm-base", "debug-base";
  7326. qcom,coresight-jtagmm-cpu = <0x5>;
  7327. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  7328. clock-names = "core_clk", "core_a_clk";
  7329. };
  7330.  
  7331. jtagmm@61bc000 {
  7332. compatible = "qcom,jtagv8-mm";
  7333. reg = <0x61bc000 0x1000 0x61b0000 0x1000>;
  7334. reg-names = "etm-base", "debug-base";
  7335. qcom,coresight-jtagmm-cpu = <0x6>;
  7336. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  7337. clock-names = "core_clk", "core_a_clk";
  7338. };
  7339.  
  7340. jtagmm@61bd000 {
  7341. compatible = "qcom,jtagv8-mm";
  7342. reg = <0x61bd000 0x1000 0x61b2000 0x1000>;
  7343. reg-names = "etm-base", "debug-base";
  7344. qcom,coresight-jtagmm-cpu = <0x7>;
  7345. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  7346. clock-names = "core_clk", "core_a_clk";
  7347. };
  7348.  
  7349. jtagmm@61be000 {
  7350. compatible = "qcom,jtagv8-mm";
  7351. reg = <0x61be000 0x1000 0x61b4000 0x1000>;
  7352. reg-names = "etm-base", "debug-base";
  7353. qcom,coresight-jtagmm-cpu = <0x8>;
  7354. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  7355. clock-names = "core_clk", "core_a_clk";
  7356. };
  7357.  
  7358. jtagmm@61bf000 {
  7359. compatible = "qcom,jtagv8-mm";
  7360. reg = <0x61bf000 0x1000 0x61b6000 0x1000>;
  7361. reg-names = "etm-base", "debug-base";
  7362. qcom,coresight-jtagmm-cpu = <0x9>;
  7363. clocks = <0x37 0x1492202a 0x37 0xdd121669>;
  7364. clock-names = "core_clk", "core_a_clk";
  7365. };
  7366.  
  7367. qcom,ipa@07900000 {
  7368. compatible = "qcom,ipa";
  7369. reg = <0x7900000 0x4effc 0x7904000 0x26934>;
  7370. reg-names = "ipa-base", "bam-base";
  7371. interrupts = <0x0 0xe4 0x0 0x0 0xe6 0x0>;
  7372. interrupt-names = "ipa-irq", "bam-irq";
  7373. qcom,ipa-hw-ver = <0x6>;
  7374. qcom,ipa-hw-mode = <0x0>;
  7375. clock-names = "core_clk";
  7376. clocks = <0x37 0xfa685cda>;
  7377. qcom,ee = <0x0>;
  7378. qcom,use-ipa-tethering-bridge;
  7379. qcom,modem-cfg-emb-pipe-flt;
  7380. qcom,msm-bus,name = "ipa";
  7381. qcom,msm-bus,num-cases = <0x3>;
  7382. qcom,msm-bus,num-paths = <0x1>;
  7383. qcom,msm-bus,vectors-KBps = <0x5a 0x200 0x0 0x0 0x5a 0x200 0x186a0 0xc3500 0x5a 0x200 0x186a0 0x124f80>;
  7384. qcom,bus-vector-names = "MIN", "SVS", "PERF";
  7385. };
  7386.  
  7387. qcom,rmnet-ipa {
  7388. compatible = "qcom,rmnet-ipa";
  7389. qcom,rmnet-ipa-ssr;
  7390. qcom,ipa-loaduC;
  7391. qcom,ipa-advertise-sg-support;
  7392. };
  7393.  
  7394. qcom,smdtty {
  7395. compatible = "qcom,smdtty";
  7396.  
  7397. qcom,smdtty-apps-fm {
  7398. qcom,smdtty-remote = "wcnss";
  7399. qcom,smdtty-port-name = "APPS_FM";
  7400. };
  7401.  
  7402. smdtty-apps-riva-bt-acl {
  7403. qcom,smdtty-remote = "wcnss";
  7404. qcom,smdtty-port-name = "APPS_RIVA_BT_ACL";
  7405. };
  7406.  
  7407. qcom,smdtty-apps-riva-bt-cmd {
  7408. qcom,smdtty-remote = "wcnss";
  7409. qcom,smdtty-port-name = "APPS_RIVA_BT_CMD";
  7410. };
  7411.  
  7412. qcom,smdtty-mbalbridge {
  7413. qcom,smdtty-remote = "modem";
  7414. qcom,smdtty-port-name = "MBALBRIDGE";
  7415. };
  7416.  
  7417. smdtty-apps-riva-ant-cmd {
  7418. qcom,smdtty-remote = "wcnss";
  7419. qcom,smdtty-port-name = "APPS_RIVA_ANT_CMD";
  7420. };
  7421.  
  7422. smdtty-apps-riva-ant-data {
  7423. qcom,smdtty-remote = "wcnss";
  7424. qcom,smdtty-port-name = "APPS_RIVA_ANT_DATA";
  7425. };
  7426.  
  7427. qcom,smdtty-data1 {
  7428. qcom,smdtty-remote = "modem";
  7429. qcom,smdtty-port-name = "DATA1";
  7430. };
  7431.  
  7432. qcom,smdtty-data4 {
  7433. qcom,smdtty-remote = "modem";
  7434. qcom,smdtty-port-name = "DATA4";
  7435. };
  7436.  
  7437. qcom,smdtty-data11 {
  7438. qcom,smdtty-remote = "modem";
  7439. qcom,smdtty-port-name = "DATA11";
  7440. };
  7441.  
  7442. qcom,smdtty-data21 {
  7443. qcom,smdtty-remote = "modem";
  7444. qcom,smdtty-port-name = "DATA21";
  7445. };
  7446.  
  7447. smdtty-loopback {
  7448. qcom,smdtty-remote = "modem";
  7449. qcom,smdtty-port-name = "LOOPBACK";
  7450. qcom,smdtty-dev-name = "LOOPBACK_TTY";
  7451. };
  7452. };
  7453.  
  7454. qcom,smdpkt {
  7455. compatible = "qcom,smdpkt";
  7456.  
  7457. qcom,smdpkt-data5-cntl {
  7458. qcom,smdpkt-remote = "modem";
  7459. qcom,smdpkt-port-name = "DATA5_CNTL";
  7460. qcom,smdpkt-dev-name = "smdcntl0";
  7461. };
  7462.  
  7463. qcom,smdpkt-data22 {
  7464. qcom,smdpkt-remote = "modem";
  7465. qcom,smdpkt-port-name = "DATA22";
  7466. qcom,smdpkt-dev-name = "smd22";
  7467. };
  7468.  
  7469. qcom,smdpkt-data40-cntl {
  7470. qcom,smdpkt-remote = "modem";
  7471. qcom,smdpkt-port-name = "DATA40_CNTL";
  7472. qcom,smdpkt-dev-name = "smdcntl8";
  7473. };
  7474.  
  7475. qcom,smdpkt-apr-apps2 {
  7476. qcom,smdpkt-remote = "adsp";
  7477. qcom,smdpkt-port-name = "apr_apps2";
  7478. qcom,smdpkt-dev-name = "apr_apps2";
  7479. };
  7480.  
  7481. qcom,smdpkt-loopback {
  7482. qcom,smdpkt-remote = "modem";
  7483. qcom,smdpkt-port-name = "LOOPBACK";
  7484. qcom,smdpkt-dev-name = "smd_pkt_loopback";
  7485. };
  7486. };
  7487.  
  7488. qcom,iris-fm {
  7489. compatible = "qcom,iris_fm";
  7490. };
  7491.  
  7492. qcom,wcnss-wlan@0a000000 {
  7493. compatible = "qcom,wcnss_wlan";
  7494. reg = <0xa000000 0x280000 0xb011008 0x4 0xa21b000 0x3000 0x3204000 0x100 0x3200800 0x200 0xa100400 0x200 0xa205050 0x200 0xa219000 0x20 0xa080488 0x8 0xa080fb0 0x8 0xa08040c 0x8 0xa0120a8 0x8 0xa012448 0x8 0xa080c00 0x1>;
  7495. reg-names = "wcnss_mmio", "wcnss_fiq", "pronto_phy_base", "riva_phy_base", "riva_ccu_base", "pronto_a2xb_base", "pronto_ccpu_base", "pronto_saw2_base", "wlan_tx_phy_aborts", "wlan_brdg_err_source", "wlan_tx_status", "alarms_txctl", "alarms_tactl", "pronto_mcu_base";
  7496. interrupts = <0x0 0x91 0x0 0x0 0x92 0x0>;
  7497. interrupt-names = "wcnss_wlantx_irq", "wcnss_wlanrx_irq";
  7498. qcom,pronto-vddmx-supply = <0xf7>;
  7499. qcom,pronto-vddcx-supply = <0xf4>;
  7500. qcom,pronto-vddpx-supply = <0xe1>;
  7501. qcom,iris-vddxo-supply = <0xfb>;
  7502. qcom,iris-vddrfa-supply = <0xfc>;
  7503. qcom,iris-vddpa-supply = <0xfd>;
  7504. qcom,iris-vdddig-supply = <0xe1>;
  7505. qcom,iris-vddxo-voltage-level = <0x1b7740 0x0 0x1b7740>;
  7506. qcom,iris-vddrfa-voltage-level = <0x13d620 0x0 0x13d620>;
  7507. qcom,iris-vddpa-voltage-level = <0x325aa0 0x0 0x325aa0>;
  7508. qcom,iris-vdddig-voltage-level = <0x1b7740 0x0 0x1b7740>;
  7509. qcom,vddmx-voltage-level = <0x180 0x0 0x180>;
  7510. qcom,vddcx-voltage-level = <0x100 0x0 0x180>;
  7511. qcom,vddpx-voltage-level = <0x1b7740 0x0 0x1b7740>;
  7512. qcom,iris-vddxo-current = <0x2710>;
  7513. qcom,iris-vddrfa-current = <0x186a0>;
  7514. qcom,iris-vddpa-current = <0x7dbb8>;
  7515. qcom,iris-vdddig-current = <0x2710>;
  7516. qcom,pronto-vddmx-current = <0x0>;
  7517. qcom,pronto-vddcx-current = <0x0>;
  7518. qcom,pronto-vddpx-current = <0x0>;
  7519. pinctrl-names = "wcnss_default", "wcnss_sleep", "wcnss_gpio_default";
  7520. pinctrl-0 = <0xfe>;
  7521. pinctrl-1 = <0xff>;
  7522. pinctrl-2 = <0x100>;
  7523. gpios = <0xbe 0x4c 0x0 0xbe 0x4d 0x0 0xbe 0x4e 0x0 0xbe 0x4f 0x0 0xbe 0x50 0x0>;
  7524. clocks = <0x37 0x116b76f 0x37 0x24a30992 0x101 0x8121ac15 0x37 0x709f430b>;
  7525. clock-names = "xo", "rf_clk", "measure", "wcnss_debug";
  7526. qcom,has-autodetect-xo;
  7527. qcom,is-pronto-v3;
  7528. qcom,has-pronto-hw;
  7529. qcom,has-vsys-adc-channel;
  7530. qcom,has-a2xb-split-reg;
  7531. qcom,wcnss-adc_tm = <0x102>;
  7532. };
  7533.  
  7534. qrng@e3000 {
  7535. compatible = "qcom,msm-rng";
  7536. reg = <0xe3000 0x1000>;
  7537. qcom,msm-rng-iface-clk;
  7538. qcom,no-qrng-config;
  7539. qcom,msm-bus,name = "msm-rng-noc";
  7540. qcom,msm-bus,num-cases = <0x2>;
  7541. qcom,msm-bus,num-paths = <0x1>;
  7542. qcom,msm-bus,vectors-KBps = <0x1 0x26a 0x0 0x0 0x1 0x26a 0x0 0x320>;
  7543. clocks = <0x37 0x397e7eaa>;
  7544. clock-names = "iface_clk";
  7545. };
  7546.  
  7547. tz-log@08600720 {
  7548. compatible = "qcom,tz-log";
  7549. reg = "\b`\a ", "", " ";
  7550. };
  7551.  
  7552. qcrypto@720000 {
  7553. compatible = "qcom,qcrypto";
  7554. reg = <0x720000 0x20000 0x704000 0x20000>;
  7555. reg-names = "crypto-base", "crypto-bam-base";
  7556. interrupts = <0x0 0xcf 0x0>;
  7557. qcom,bam-pipe-pair = <0x2>;
  7558. qcom,ce-hw-instance = <0x0>;
  7559. qcom,ce-device = <0x0>;
  7560. qcom,ce-hw-shared;
  7561. qcom,clk-mgmt-sus-res;
  7562. qcom,msm-bus,name = "qcrypto-noc";
  7563. qcom,msm-bus,num-cases = <0x2>;
  7564. qcom,msm-bus,num-paths = <0x1>;
  7565. qcom,msm-bus,vectors-KBps = <0x37 0x200 0x0 0x0 0x37 0x200 0x60180 0x60180>;
  7566. clocks = <0x37 0x37a21414 0x37 0xd390d2 0x37 0x94de4919 0x37 0xd4415c9b>;
  7567. clock-names = "core_clk_src", "core_clk", "iface_clk", "bus_clk";
  7568. qcom,use-sw-aes-cbc-ecb-ctr-algo;
  7569. qcom,use-sw-aes-xts-algo;
  7570. qcom,use-sw-aes-ccm-algo;
  7571. qcom,use-sw-ahash-algo;
  7572. qcom,ce-opp-freq = <0x5f5e100>;
  7573. };
  7574.  
  7575. qcedev@720000 {
  7576. compatible = "qcom,qcedev";
  7577. reg = <0x720000 0x20000 0x704000 0x20000>;
  7578. reg-names = "crypto-base", "crypto-bam-base";
  7579. interrupts = <0x0 0xcf 0x0>;
  7580. qcom,bam-pipe-pair = <0x1>;
  7581. qcom,ce-hw-instance = <0x0>;
  7582. qcom,ce-device = <0x0>;
  7583. qcom,ce-hw-shared;
  7584. qcom,msm-bus,name = "qcedev-noc";
  7585. qcom,msm-bus,num-cases = <0x2>;
  7586. qcom,msm-bus,num-paths = <0x1>;
  7587. qcom,msm-bus,vectors-KBps = <0x37 0x200 0x0 0x0 0x37 0x200 0x60180 0x60180>;
  7588. clocks = <0x37 0x37a21414 0x37 0xd390d2 0x37 0x94de4919 0x37 0xd4415c9b>;
  7589. clock-names = "core_clk_src", "core_clk", "iface_clk", "bus_clk";
  7590. qcom,ce-opp-freq = <0x5f5e100>;
  7591. };
  7592.  
  7593. qseecom@84A00000 {
  7594. compatible = "qcom,qseecom";
  7595. reg = <0x84a00000 0x1900000>;
  7596. reg-names = "secapp-region";
  7597. qcom,hlos-num-ce-hw-instances = <0x1>;
  7598. qcom,hlos-ce-hw-instance = <0x0>;
  7599. qcom,qsee-ce-hw-instance = <0x0>;
  7600. qcom,disk-encrypt-pipe-pair = <0x2>;
  7601. qcom,support-fde;
  7602. qcom,msm-bus,name = "qseecom-noc";
  7603. qcom,msm-bus,num-cases = <0x4>;
  7604. qcom,msm-bus,num-paths = <0x1>;
  7605. qcom,support-bus-scaling;
  7606. qcom,appsbl-qseecom-support;
  7607. qcom,msm-bus,vectors-KBps = <0x37 0x200 0x0 0x0 0x37 0x200 0x0 0x0 0x37 0x200 0x1d4c0 0x124f80 0x37 0x200 0x60180 0x3c0f00>;
  7608. clocks = <0x37 0x37a21414 0x37 0xd390d2 0x37 0x94de4919 0x37 0xd4415c9b>;
  7609. clock-names = "core_clk_src", "core_clk", "iface_clk", "bus_clk";
  7610. qcom,ce-opp-freq = <0x5f5e100>;
  7611. };
  7612.  
  7613. qcom,ipc_router {
  7614. compatible = "qcom,ipc_router";
  7615. qcom,node-id = <0x1>;
  7616. };
  7617.  
  7618. qcom,ipc_router_modem_xprt {
  7619. compatible = "qcom,ipc_router_smd_xprt";
  7620. qcom,ch-name = "IPCRTR";
  7621. qcom,xprt-remote = "modem";
  7622. qcom,xprt-linkid = <0x1>;
  7623. qcom,xprt-version = <0x1>;
  7624. qcom,fragmented-data;
  7625. qcom,disable-pil-loading;
  7626. };
  7627.  
  7628. qcom,ipc_router_q6_xprt {
  7629. compatible = "qcom,ipc_router_smd_xprt";
  7630. qcom,ch-name = "IPCRTR";
  7631. qcom,xprt-remote = "adsp";
  7632. qcom,xprt-linkid = <0x1>;
  7633. qcom,xprt-version = <0x1>;
  7634. qcom,fragmented-data;
  7635. };
  7636.  
  7637. qcom,ipc_router_wcnss_xprt {
  7638. compatible = "qcom,ipc_router_smd_xprt";
  7639. qcom,ch-name = "IPCRTR";
  7640. qcom,xprt-remote = "wcnss";
  7641. qcom,xprt-linkid = <0x1>;
  7642. qcom,xprt-version = <0x1>;
  7643. qcom,fragmented-data;
  7644. };
  7645.  
  7646. qcom,adsprpc-mem {
  7647. compatible = "qcom,msm-adsprpc-mem-region";
  7648. memory-region = <0x103>;
  7649. };
  7650.  
  7651. qcom,adsprpc_domains {
  7652. compatible = "qcom,msm-fastrpc-legacy-compute-cb";
  7653.  
  7654. qcom,msm_fastrpc_compute_cb {
  7655. qcom,adsp-shared-phandle = <0x104>;
  7656. qcom,adsp-shared-sids = <0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf>;
  7657. qcom,virtual-addr-pool = <0x80000000 0x7fffffff>;
  7658. };
  7659. };
  7660.  
  7661. sdcc1ice@7803000 {
  7662. compatible = "qcom,ice";
  7663. reg = <0x7803000 0x8000>;
  7664. interrupt-names = "sdcc_ice_nonsec_level_irq", "sdcc_ice_sec_level_irq";
  7665. interrupts = <0x0 0x138 0x0 0x0 0x139 0x0>;
  7666. qcom,enable-ice-clk;
  7667. clock-names = "ice_core_clk_src", "ice_core_clk", "bus_clk", "iface_clk";
  7668. clocks = <0x37 0xfd6a4301 0x37 0xfd5680a 0x37 0x9ad6fb96 0x37 0x691e0caa>;
  7669. qcom,op-freq-hz = <0x1017df80 0x0 0x0 0x0>;
  7670. qcom,msm-bus,name = "sdcc_ice_noc";
  7671. qcom,msm-bus,num-cases = <0x2>;
  7672. qcom,msm-bus,num-paths = <0x1>;
  7673. qcom,msm-bus,vectors-KBps = <0x4e 0x200 0x0 0x0 0x4e 0x200 0x3e8 0x0>;
  7674. qcom,bus-vector-names = "MIN", "MAX";
  7675. qcom,instance-type = "sdcc";
  7676. linux,phandle = <0x105>;
  7677. phandle = <0x105>;
  7678. };
  7679.  
  7680. sdhci@7824900 {
  7681. compatible = "qcom,sdhci-msm";
  7682. reg = <0x7824900 0x500 0x7824000 0x800 0x7824e00 0x200>;
  7683. reg-names = "hc_mem", "core_mem", "cmdq_mem";
  7684. interrupts = <0x0 0x7b 0x0 0x0 0x8a 0x0>;
  7685. interrupt-names = "hc_irq", "pwr_irq";
  7686. sdhc-msm-crypto = <0x105>;
  7687. qcom,bus-width = <0x8>;
  7688. qcom,devfreq,freq-table = <0x2faf080 0xbebc200>;
  7689. qcom,pm-qos-irq-type = "affine_irq";
  7690. qcom,pm-qos-irq-latency = <0x2 0xd5>;
  7691. qcom,pm-qos-cpu-groups = <0xf 0xf0>;
  7692. qcom,pm-qos-cmdq-latency-us = <0x2 0xd5 0x2 0xd5>;
  7693. qcom,pm-qos-legacy-latency-us = <0x2 0xd5 0x2 0xd5>;
  7694. qcom,msm-bus,name = "sdhc1";
  7695. qcom,msm-bus,num-cases = <0x9>;
  7696. qcom,msm-bus,num-paths = <0x1>;
  7697. qcom,msm-bus,vectors-KBps = <0x4e 0x200 0x0 0x0 0x4e 0x200 0x416 0xc80 0x4e 0x200 0xcc3e 0x27100 0x4e 0x200 0xff50 0x30d40 0x4e 0x200 0x1fe9e 0x61a80 0x4e 0x200 0x1fe9e 0x61a80 0x4e 0x200 0x3fd3e 0xc3500 0x4e 0x200 0x3fd3e 0xc3500 0x4e 0x200 0x146cc2 0x3e8000>;
  7698. qcom,bus-bw-vectors-bps = <0x0 0x61a80 0x1312d00 0x17d7840 0x2faf080 0x5f5e100 0xbebc200 0x17d78400 0xffffffff>;
  7699. clocks = <0x37 0x691e0caa 0x37 0x9ad6fb96 0x37 0xfd5680a>;
  7700. clock-names = "iface_clk", "core_clk", "ice_core_clk";
  7701. qcom,ice-clk-rates = <0x1017df80 0x9896800>;
  7702. qcom,large-address-bus;
  7703. status = "ok";
  7704. vdd-supply = <0x106>;
  7705. qcom,vdd-voltage-level = <0x2c4020 0x2c4020>;
  7706. qcom,vdd-current-level = <0xc8 0x8b290>;
  7707. vdd-io-supply = <0xe1>;
  7708. qcom,vdd-io-always-on;
  7709. qcom,vdd-io-lpm-sup;
  7710. qcom,vdd-io-voltage-level = <0x1b7740 0x1b7740>;
  7711. qcom,vdd-io-current-level = <0xc8 0x4f588>;
  7712. pinctrl-names = "active", "sleep";
  7713. pinctrl-0 = <0x107 0x108 0x109 0x10a>;
  7714. pinctrl-1 = <0x10b 0x10c 0x10d 0x10e>;
  7715. qcom,clk-rates = <0x61a80 0x1312d00 0x17d7840 0x2faf080 0x5f5e100 0xb71b000 0x16e36000>;
  7716. qcom,nonremovable;
  7717. qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v";
  7718. };
  7719.  
  7720. sdhci@7864900 {
  7721. compatible = "qcom,sdhci-msm";
  7722. reg = <0x7864900 0x500 0x7864000 0x800>;
  7723. reg-names = "hc_mem", "core_mem";
  7724. interrupts = <0x0 0x1 0x2>;
  7725. interrupt-names = "hc_irq", "pwr_irq", "status_irq";
  7726. qcom,bus-width = <0x4>;
  7727. qcom,pm-qos-irq-type = "affine_irq";
  7728. qcom,pm-qos-irq-latency = <0x2 0xd5>;
  7729. qcom,pm-qos-cpu-groups = <0xf 0xf0>;
  7730. qcom,pm-qos-legacy-latency-us = <0x2 0xd5 0x2 0xd5>;
  7731. qcom,devfreq,freq-table = <0x2faf080 0xbebc200>;
  7732. qcom,msm-bus,name = "sdhc2";
  7733. qcom,msm-bus,num-cases = <0x8>;
  7734. qcom,msm-bus,num-paths = <0x1>;
  7735. qcom,msm-bus,vectors-KBps = <0x51 0x200 0x0 0x0 0x51 0x200 0x416 0xc80 0x51 0x200 0xcc3e 0x27100 0x51 0x200 0xff50 0x30d40 0x51 0x200 0x1fe9e 0x61a80 0x51 0x200 0x3fd3e 0xc3500 0x51 0x200 0x3fd3e 0xc3500 0x51 0x200 0x146cc2 0x3e8000>;
  7736. qcom,bus-bw-vectors-bps = <0x0 0x61a80 0x1312d00 0x17d7840 0x2faf080 0x5f5e100 0xbebc200 0xffffffff>;
  7737. clocks = <0x37 0x23d5727f 0x37 0x861b20ac>;
  7738. clock-names = "iface_clk", "core_clk";
  7739. qcom,large-address-bus;
  7740. status = "ok";
  7741. vdd-supply = <0x6a>;
  7742. qcom,vdd-voltage-level = <0x2d0370 0x2d0370>;
  7743. qcom,vdd-current-level = <0x3a98 0xc3500>;
  7744. vdd-io-supply = <0x6b>;
  7745. qcom,vdd-io-voltage-level = <0x1b7740 0x2d0370>;
  7746. qcom,vdd-io-current-level = <0xc8 0x55f0>;
  7747. pinctrl-names = "active", "sleep";
  7748. pinctrl-0 = <0x10f 0x110 0x111 0x112>;
  7749. pinctrl-1 = <0x113 0x114 0x115 0x116>;
  7750. #address-cells = <0x0>;
  7751. interrupt-parent = <0x117>;
  7752. #interrupt-cells = <0x1>;
  7753. interrupt-map-mask = <0xffffffff>;
  7754. interrupt-map = <0x0 0x1 0x0 0x7d 0x0 0x1 0x1 0x0 0xdd 0x0 0x2 0xbe 0x85 0x0>;
  7755. cd-gpios = <0xbe 0x85 0x1>;
  7756. qcom,clk-rates = <0x61a80 0x1312d00 0x17d7840 0x2faf080 0x5f5e100 0xbebc200>;
  7757. qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104";
  7758. linux,phandle = <0x117>;
  7759. phandle = <0x117>;
  7760. };
  7761.  
  7762. qcom,spmi@200f000 {
  7763. compatible = "qcom,spmi-pmic-arb";
  7764. reg = <0x200f000 0x1000 0x2400000 0x800000 0x2c00000 0x800000 0x3800000 0x200000 0x200a000 0x2100>;
  7765. reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
  7766. interrupts = <0x0 0xbe 0x0>;
  7767. qcom,pmic-arb-channel = <0x0>;
  7768. qcom,pmic-arb-max-peripherals = <0x100>;
  7769. qcom,pmic-arb-max-periph-interrupts = <0x100>;
  7770. qcom,pmic-arb-ee = <0x0>;
  7771. #interrupt-cells = <0x3>;
  7772. interrupt-controller;
  7773. #address-cells = <0x1>;
  7774. #size-cells = <0x0>;
  7775. cell-index = <0x0>;
  7776. linux,phandle = <0x11a>;
  7777. phandle = <0x11a>;
  7778.  
  7779. qcom,pm8953@0 {
  7780. spmi-slave-container;
  7781. reg = <0x0>;
  7782. #address-cells = <0x1>;
  7783. #size-cells = <0x1>;
  7784.  
  7785. qcom,revid@100 {
  7786. compatible = "qcom,qpnp-revid";
  7787. reg = <0x100 0x100>;
  7788. };
  7789.  
  7790. qcom,power-on@800 {
  7791. compatible = "qcom,qpnp-power-on";
  7792. reg = <0x800 0x100>;
  7793. interrupts = <0x0 0x8 0x0 0x0 0x8 0x1 0x0 0x8 0x4 0x0 0x8 0x5>;
  7794. interrupt-names = "kpdpwr", "resin", "resin-bark", "kpdpwr-resin-bark";
  7795. qcom,pon-dbc-delay = <0x3d09>;
  7796. qcom,system-reset;
  7797.  
  7798. qcom,pon_1 {
  7799. qcom,pon-type = <0x0>;
  7800. qcom,pull-up = <0x1>;
  7801. qcom,support-reset = <0x1>;
  7802. qcom,s1-timer = <0x2810>;
  7803. qcom,s2-timer = <0x7d0>;
  7804. qcom,s2-type = <0x7>;
  7805. linux,code = <0x74>;
  7806. };
  7807.  
  7808. qcom,pon_2 {
  7809. qcom,pon-type = <0x1>;
  7810. qcom,pull-up = <0x1>;
  7811. linux,code = <0x72>;
  7812. };
  7813. };
  7814.  
  7815. qcom,temp-alarm@2400 {
  7816. compatible = "qcom,qpnp-temp-alarm";
  7817. reg = <0x2400 0x100>;
  7818. interrupts = <0x0 0x24 0x0>;
  7819. label = "pm8953_tz";
  7820. qcom,channel-num = <0x8>;
  7821. qcom,threshold-set = <0x0>;
  7822. qcom,temp_alarm-vadc = <0x118>;
  7823. };
  7824.  
  7825. qcom,coincell@2800 {
  7826. compatible = "qcom,qpnp-coincell";
  7827. reg = <0x2800 0x100>;
  7828. };
  7829.  
  7830. mpps {
  7831. compatible = "qcom,qpnp-pin";
  7832. spmi-dev-container;
  7833. gpio-controller;
  7834. #gpio-cells = <0x2>;
  7835. #address-cells = <0x1>;
  7836. #size-cells = <0x1>;
  7837. label = "pm8953-mpp";
  7838.  
  7839. mpp@a000 {
  7840. reg = <0xa000 0x100>;
  7841. qcom,pin-num = <0x1>;
  7842. status = "disabled";
  7843. };
  7844.  
  7845. mpp@a100 {
  7846. reg = <0xa100 0x100>;
  7847. qcom,pin-num = <0x2>;
  7848. qcom,mode = <0x4>;
  7849. qcom,invert = <0x1>;
  7850. qcom,ain-route = <0x1>;
  7851. qcom,master-en = <0x1>;
  7852. qcom,src-sel = <0x0>;
  7853. };
  7854.  
  7855. mpp@a200 {
  7856. reg = <0xa200 0x100>;
  7857. qcom,pin-num = <0x3>;
  7858. status = "disabled";
  7859. };
  7860.  
  7861. mpp@a300 {
  7862. reg = <0xa300 0x100>;
  7863. qcom,pin-num = <0x4>;
  7864. qcom,mode = <0x4>;
  7865. qcom,invert = <0x1>;
  7866. qcom,ain-route = <0x3>;
  7867. qcom,master-en = <0x1>;
  7868. qcom,src-sel = <0x0>;
  7869. };
  7870. };
  7871.  
  7872. gpios {
  7873. spmi-dev-container;
  7874. compatible = "qcom,qpnp-pin";
  7875. gpio-controller;
  7876. #gpio-cells = <0x2>;
  7877. #address-cells = <0x1>;
  7878. #size-cells = <0x1>;
  7879. label = "pm8953-gpio";
  7880. linux,phandle = <0xea>;
  7881. phandle = <0xea>;
  7882.  
  7883. gpio@c000 {
  7884. reg = <0xc000 0x100>;
  7885. qcom,pin-num = <0x1>;
  7886. status = "ok";
  7887. qcom,mode = <0x1>;
  7888. qcom,pull = <0x5>;
  7889. qcom,vin-sel = <0x0>;
  7890. qcom,src-sel = <0x2>;
  7891. qcom,master-en = <0x1>;
  7892. qcom,out-strength = <0x2>;
  7893. };
  7894.  
  7895. gpio@c100 {
  7896. reg = <0xc100 0x100>;
  7897. qcom,pin-num = <0x2>;
  7898. status = "okay";
  7899. qcom,mode = <0x0>;
  7900. qcom,output-type = <0x0>;
  7901. qcom,pull = <0x0>;
  7902. qcom,vin-sel = <0x2>;
  7903. qcom,out-strength = <0x3>;
  7904. qcom,src-sel = <0x0>;
  7905. qcom,master-en = <0x1>;
  7906. };
  7907.  
  7908. gpio@c200 {
  7909. reg = <0xc200 0x100>;
  7910. qcom,pin-num = <0x3>;
  7911. status = "disabled";
  7912. };
  7913.  
  7914. gpio@c300 {
  7915. reg = <0xc300 0x100>;
  7916. qcom,pin-num = <0x4>;
  7917. status = "disabled";
  7918. };
  7919.  
  7920. gpio@c400 {
  7921. reg = <0xc400 0x100>;
  7922. qcom,pin-num = <0x5>;
  7923. status = "disabled";
  7924. };
  7925.  
  7926. gpio@c500 {
  7927. reg = <0xc500 0x100>;
  7928. qcom,pin-num = <0x6>;
  7929. status = "disabled";
  7930. };
  7931.  
  7932. gpio@c600 {
  7933. reg = <0xc600 0x100>;
  7934. qcom,pin-num = <0x7>;
  7935. status = "disabled";
  7936. };
  7937.  
  7938. gpio@c700 {
  7939. reg = <0xc700 0x100>;
  7940. qcom,pin-num = <0x8>;
  7941. status = "disabled";
  7942. };
  7943. };
  7944.  
  7945. vadc@3100 {
  7946. compatible = "qcom,qpnp-vadc";
  7947. reg = <0x3100 0x100>;
  7948. #address-cells = <0x1>;
  7949. #size-cells = <0x0>;
  7950. interrupts = <0x0 0x31 0x0>;
  7951. interrupt-names = "eoc-int-en-set";
  7952. qcom,adc-bit-resolution = <0xf>;
  7953. qcom,adc-vdd-reference = <0x708>;
  7954. qcom,vadc-poll-eoc;
  7955. linux,phandle = <0x118>;
  7956. phandle = <0x118>;
  7957.  
  7958. chan@8 {
  7959. label = "die_temp";
  7960. reg = <0x8>;
  7961. qcom,decimation = <0x0>;
  7962. qcom,pre-div-channel-scaling = <0x0>;
  7963. qcom,calibration-type = "absolute";
  7964. qcom,scale-function = <0x3>;
  7965. qcom,hw-settle-time = <0x0>;
  7966. qcom,fast-avg-setup = <0x0>;
  7967. };
  7968.  
  7969. chan@9 {
  7970. label = "ref_625mv";
  7971. reg = <0x9>;
  7972. qcom,decimation = <0x0>;
  7973. qcom,pre-div-channel-scaling = <0x0>;
  7974. qcom,calibration-type = "absolute";
  7975. qcom,scale-function = <0x0>;
  7976. qcom,hw-settle-time = <0x0>;
  7977. qcom,fast-avg-setup = <0x0>;
  7978. };
  7979.  
  7980. chan@a {
  7981. label = "ref_1250v";
  7982. reg = <0xa>;
  7983. qcom,decimation = <0x0>;
  7984. qcom,pre-div-channel-scaling = <0x0>;
  7985. qcom,calibration-type = "absolute";
  7986. qcom,scale-function = <0x0>;
  7987. qcom,hw-settle-time = <0x0>;
  7988. qcom,fast-avg-setup = <0x0>;
  7989. };
  7990.  
  7991. chan@c {
  7992. label = "ref_buf_625mv";
  7993. reg = <0xc>;
  7994. qcom,decimation = <0x0>;
  7995. qcom,pre-div-channel-scaling = <0x0>;
  7996. qcom,calibration-type = "absolute";
  7997. qcom,scale-function = <0x0>;
  7998. qcom,hw-settle-time = <0x0>;
  7999. qcom,fast-avg-setup = <0x0>;
  8000. };
  8001.  
  8002. chan@5 {
  8003. label = "vcoin";
  8004. reg = <0x5>;
  8005. qcom,decimation = <0x0>;
  8006. qcom,pre-div-channel-scaling = <0x1>;
  8007. qcom,calibration-type = "absolute";
  8008. qcom,scale-function = <0x0>;
  8009. qcom,hw-settle-time = <0x0>;
  8010. qcom,fast-avg-setup = <0x0>;
  8011. };
  8012.  
  8013. chan@7 {
  8014. label = "vph_pwr";
  8015. reg = <0x7>;
  8016. qcom,decimation = <0x0>;
  8017. qcom,pre-div-channel-scaling = <0x1>;
  8018. qcom,calibration-type = "absolute";
  8019. qcom,scale-function = <0x0>;
  8020. qcom,hw-settle-time = <0x0>;
  8021. qcom,fast-avg-setup = <0x0>;
  8022. };
  8023.  
  8024. chan@36 {
  8025. label = "pa_therm0";
  8026. reg = <0x36>;
  8027. qcom,decimation = <0x0>;
  8028. qcom,pre-div-channel-scaling = <0x0>;
  8029. qcom,calibration-type = "ratiometric";
  8030. qcom,scale-function = <0x2>;
  8031. qcom,hw-settle-time = <0x2>;
  8032. qcom,fast-avg-setup = <0x0>;
  8033. };
  8034.  
  8035. chan@32 {
  8036. label = "xo_therm";
  8037. reg = <0x32>;
  8038. qcom,decimation = <0x0>;
  8039. qcom,pre-div-channel-scaling = <0x0>;
  8040. qcom,calibration-type = "ratiometric";
  8041. qcom,scale-function = <0x4>;
  8042. qcom,hw-settle-time = <0x2>;
  8043. qcom,fast-avg-setup = <0x0>;
  8044. qcom,vadc-thermal-node;
  8045. };
  8046.  
  8047. chan@3c {
  8048. label = "xo_therm_buf";
  8049. reg = <0x3c>;
  8050. qcom,decimation = <0x0>;
  8051. qcom,pre-div-channel-scaling = <0x0>;
  8052. qcom,calibration-type = "ratiometric";
  8053. qcom,scale-function = <0x4>;
  8054. qcom,hw-settle-time = <0x2>;
  8055. qcom,fast-avg-setup = <0x0>;
  8056. qcom,vadc-thermal-node;
  8057. };
  8058.  
  8059. chan@13 {
  8060. label = "case_therm";
  8061. reg = <0x13>;
  8062. qcom,decimation = <0x0>;
  8063. qcom,pre-div-channel-scaling = <0x0>;
  8064. qcom,calibration-type = "ratiometric";
  8065. qcom,scale-function = <0x2>;
  8066. qcom,hw-settle-time = <0x2>;
  8067. qcom,fast-avg-setup = <0x0>;
  8068. qcom,vadc-thermal-node;
  8069. };
  8070. };
  8071.  
  8072. vadc@3400 {
  8073. compatible = "qcom,qpnp-adc-tm";
  8074. reg = <0x3400 0x100>;
  8075. #address-cells = <0x1>;
  8076. #size-cells = <0x0>;
  8077. interrupts = <0x0 0x34 0x0 0x0 0x34 0x3 0x0 0x34 0x4>;
  8078. interrupt-names = "eoc-int-en-set", "high-thr-en-set", "low-thr-en-set";
  8079. qcom,adc-bit-resolution = <0xf>;
  8080. qcom,adc-vdd-reference = <0x708>;
  8081. qcom,adc_tm-vadc = <0x118>;
  8082. linux,phandle = <0x102>;
  8083. phandle = <0x102>;
  8084.  
  8085. chan@36 {
  8086. label = "pa_therm0";
  8087. reg = <0x36>;
  8088. qcom,decimation = <0x0>;
  8089. qcom,pre-div-channel-scaling = <0x0>;
  8090. qcom,calibration-type = "ratiometric";
  8091. qcom,scale-function = <0x2>;
  8092. qcom,hw-settle-time = <0x2>;
  8093. qcom,fast-avg-setup = <0x0>;
  8094. qcom,btm-channel-number = <0x48>;
  8095. qcom,thermal-node;
  8096. };
  8097.  
  8098. chan@7 {
  8099. label = "vph_pwr";
  8100. reg = <0x7>;
  8101. qcom,decimation = <0x0>;
  8102. qcom,pre-div-channel-scaling = <0x1>;
  8103. qcom,calibration-type = "absolute";
  8104. qcom,scale-function = <0x0>;
  8105. qcom,hw-settle-time = <0x0>;
  8106. qcom,fast-avg-setup = <0x0>;
  8107. qcom,btm-channel-number = <0x68>;
  8108. };
  8109. };
  8110.  
  8111. qcom,pm8953_rtc {
  8112. spmi-dev-container;
  8113. compatible = "qcom,qpnp-rtc";
  8114. #address-cells = <0x1>;
  8115. #size-cells = <0x1>;
  8116. qcom,qpnp-rtc-write = <0x0>;
  8117. qcom,qpnp-rtc-alarm-pwrup = <0x0>;
  8118.  
  8119. qcom,pm8953_rtc_rw@6000 {
  8120. reg = <0x6000 0x100>;
  8121. };
  8122.  
  8123. qcom,pm8953_rtc_alarm@6100 {
  8124. reg = <0x6100 0x100>;
  8125. interrupts = <0x0 0x61 0x1>;
  8126. };
  8127. };
  8128.  
  8129. qcom,pm8953_typec@bf00 {
  8130. compatible = "qcom,qpnp-typec";
  8131. reg = <0xbf00 0x100>;
  8132. interrupts = <0x0 0xbf 0x0 0x0 0xbf 0x1 0x0 0xbf 0x2 0x0 0xbf 0x3 0x0 0xbf 0x4 0x0 0xbf 0x6 0x0 0xbf 0x7>;
  8133. interrupt-names = "vrd-change", "ufp-detect", "ufp-detach", "dfp-detect", "dfp-detach", "vbus-err", "vconn-oc";
  8134. ss-mux-supply = <0xf3>;
  8135. qcom,ssmux-gpio = <0xbe 0x8b 0x1>;
  8136. pinctrl-names = "default";
  8137. pinctrl-0 = <0x119>;
  8138. };
  8139. };
  8140.  
  8141. qcom,pm8953@1 {
  8142. spmi-slave-container;
  8143. reg = <0x1>;
  8144. #address-cells = <0x1>;
  8145. #size-cells = <0x1>;
  8146.  
  8147. pwm@bc00 {
  8148. status = "disabled";
  8149. compatible = "qcom,qpnp-pwm";
  8150. reg = <0xbc00 0x100>;
  8151. reg-names = "qpnp-lpg-channel-base";
  8152. qcom,channel-id = <0x0>;
  8153. qcom,supported-sizes = <0x6 0x9>;
  8154. #pwm-cells = <0x2>;
  8155. };
  8156.  
  8157. spm-regulator@2000 {
  8158. compatible = "qcom,spm-regulator";
  8159. reg = <0x2000 0x100>;
  8160. regulator-name = "pm8953_s5";
  8161. regulator-min-microvolt = <0x61a80>;
  8162. regulator-max-microvolt = <0x116520>;
  8163. linux,phandle = <0x12f>;
  8164. phandle = <0x12f>;
  8165.  
  8166. avs-limit-regulator {
  8167. regulator-name = "pm8953_s5_avs_limit";
  8168. regulator-min-microvolt = <0x61a80>;
  8169. regulator-max-microvolt = <0x116520>;
  8170. linux,phandle = <0x130>;
  8171. phandle = <0x130>;
  8172. };
  8173. };
  8174.  
  8175. 8953_wcd_codec@f000 {
  8176. compatible = "qcom,msm8x16_wcd_codec";
  8177. reg = <0xf000 0x100>;
  8178. interrupt-parent = <0x11a>;
  8179. interrupts = <0x1 0xf0 0x0 0x1 0xf0 0x1 0x1 0xf0 0x2 0x1 0xf0 0x3 0x1 0xf0 0x4 0x1 0xf0 0x5 0x1 0xf0 0x6 0x1 0xf0 0x7>;
  8180. interrupt-names = "spk_cnp_int", "spk_clip_int", "spk_ocp_int", "ins_rem_det1", "but_rel_det", "but_press_det", "ins_rem_det", "mbhc_int";
  8181. cdc-vdda-cp-supply = <0x11b>;
  8182. qcom,cdc-vdda-cp-voltage = <0x1cfde0 0x1f47d0>;
  8183. qcom,cdc-vdda-cp-current = <0x7a120>;
  8184. cdc-vdd-io-supply = <0xe1>;
  8185. qcom,cdc-vdd-io-voltage = <0x1b7740 0x1b7740>;
  8186. qcom,cdc-vdd-io-current = <0x1388>;
  8187. cdc-vdd-pa-supply = <0x11b>;
  8188. qcom,cdc-vdd-pa-voltage = <0x1cfde0 0x1f47d0>;
  8189. qcom,cdc-vdd-pa-current = <0x3f7a0>;
  8190. cdc-vdd-mic-bias-supply = <0xf3>;
  8191. qcom,cdc-vdd-mic-bias-voltage = <0x2faf08 0x2faf08>;
  8192. qcom,cdc-vdd-mic-bias-current = <0x1388>;
  8193. qcom,cdc-mclk-clk-rate = <0x927c00>;
  8194. qcom,cdc-static-supplies = "cdc-vdd-io", "cdc-vdd-pa", "cdc-vdda-cp";
  8195. qcom,cdc-on-demand-supplies = "cdc-vdd-mic-bias";
  8196. qcom,dig-cdc-base-addr = <0xc0f0000>;
  8197. status = "okay";
  8198. linux,phandle = <0x168>;
  8199. phandle = <0x168>;
  8200. };
  8201.  
  8202. 8953_wcd_codec@f100 {
  8203. compatible = "qcom,msm8x16_wcd_codec";
  8204. reg = <0xf100 0x100>;
  8205. interrupt-parent = <0x11a>;
  8206. interrupts = <0x1 0xf1 0x0 0x1 0xf1 0x1 0x1 0xf1 0x2 0x1 0xf1 0x3 0x1 0xf1 0x4 0x1 0xf1 0x5>;
  8207. interrupt-names = "ear_ocp_int", "hphr_ocp_int", "hphl_ocp_det", "ear_cnp_int", "hphr_cnp_int", "hphl_cnp_int";
  8208. qcom,dig-cdc-base-addr = <0xc0f0000>;
  8209. status = "okay";
  8210. };
  8211. };
  8212.  
  8213. qcom,pmi8950@2 {
  8214. spmi-slave-container;
  8215. reg = <0x2>;
  8216. #address-cells = <0x1>;
  8217. #size-cells = <0x1>;
  8218.  
  8219. qcom,revid@100 {
  8220. compatible = "qcom,qpnp-revid";
  8221. reg = <0x100 0x100>;
  8222. linux,phandle = <0x11c>;
  8223. phandle = <0x11c>;
  8224. };
  8225.  
  8226. qcom,power-on@800 {
  8227. compatible = "qcom,qpnp-power-on";
  8228. reg = <0x800 0x100>;
  8229. qcom,secondary-pon-reset;
  8230. qcom,hard-reset-poweroff-type = <0x4>;
  8231.  
  8232. qcom,pon_perph_reg {
  8233. regulator-name = "pon_spare_reg";
  8234. qcom,pon-spare-reg-addr = <0x8c>;
  8235. qcom,pon-spare-reg-bit = <0x1>;
  8236. };
  8237. };
  8238.  
  8239. vadc@3100 {
  8240. compatible = "qcom,qpnp-vadc";
  8241. reg = <0x3100 0x100>;
  8242. #address-cells = <0x1>;
  8243. #size-cells = <0x0>;
  8244. interrupts = <0x2 0x31 0x0>;
  8245. interrupt-names = "eoc-int-en-set";
  8246. qcom,adc-bit-resolution = <0xf>;
  8247. qcom,adc-vdd-reference = <0x708>;
  8248. qcom,vadc-poll-eoc;
  8249.  
  8250. chan@0 {
  8251. label = "usbin";
  8252. reg = <0x0>;
  8253. qcom,decimation = <0x0>;
  8254. qcom,pre-div-channel-scaling = <0x4>;
  8255. qcom,calibration-type = "absolute";
  8256. qcom,scale-function = <0x0>;
  8257. qcom,hw-settle-time = <0x0>;
  8258. qcom,fast-avg-setup = <0x0>;
  8259. };
  8260.  
  8261. chan@1 {
  8262. label = "dcin";
  8263. reg = <0x1>;
  8264. qcom,decimation = <0x0>;
  8265. qcom,pre-div-channel-scaling = <0x4>;
  8266. qcom,calibration-type = "absolute";
  8267. qcom,scale-function = <0x0>;
  8268. qcom,hw-settle-time = <0x0>;
  8269. qcom,fast-avg-setup = <0x0>;
  8270. };
  8271.  
  8272. chan@3 {
  8273. label = "vchg_sns";
  8274. reg = <0x3>;
  8275. qcom,decimation = <0x0>;
  8276. qcom,pre-div-channel-scaling = <0x1>;
  8277. qcom,calibration-type = "absolute";
  8278. qcom,scale-function = <0x0>;
  8279. qcom,hw-settle-time = <0x0>;
  8280. qcom,fast-avg-setup = <0x0>;
  8281. };
  8282.  
  8283. chan@9 {
  8284. label = "ref_625mv";
  8285. reg = <0x9>;
  8286. qcom,decimation = <0x0>;
  8287. qcom,pre-div-channel-scaling = <0x0>;
  8288. qcom,calibration-type = "absolute";
  8289. qcom,scale-function = <0x0>;
  8290. qcom,hw-settle-time = <0x0>;
  8291. qcom,fast-avg-setup = <0x0>;
  8292. };
  8293.  
  8294. chan@a {
  8295. label = "ref_1250v";
  8296. reg = <0xa>;
  8297. qcom,decimation = <0x0>;
  8298. qcom,pre-div-channel-scaling = <0x0>;
  8299. qcom,calibration-type = "absolute";
  8300. qcom,scale-function = <0x0>;
  8301. qcom,hw-settle-time = <0x0>;
  8302. qcom,fast-avg-setup = <0x0>;
  8303. };
  8304.  
  8305. chan@d {
  8306. label = "chg_temp";
  8307. reg = <0xd>;
  8308. qcom,decimation = <0x0>;
  8309. qcom,pre-div-channel-scaling = <0x0>;
  8310. qcom,calibration-type = "absolute";
  8311. qcom,scale-function = <0x10>;
  8312. qcom,hw-settle-time = <0x0>;
  8313. qcom,fast-avg-setup = <0x0>;
  8314. qcom,vadc-thermal-node;
  8315. };
  8316.  
  8317. chan@43 {
  8318. label = "usb_dp";
  8319. reg = <0x43>;
  8320. qcom,decimation = <0x0>;
  8321. qcom,pre-div-channel-scaling = <0x1>;
  8322. qcom,calibration-type = "absolute";
  8323. qcom,scale-function = <0x0>;
  8324. qcom,hw-settle-time = <0x0>;
  8325. qcom,fast-avg-setup = <0x0>;
  8326. };
  8327.  
  8328. chan@44 {
  8329. label = "usb_dm";
  8330. reg = <0x44>;
  8331. qcom,decimation = <0x0>;
  8332. qcom,pre-div-channel-scaling = <0x1>;
  8333. qcom,calibration-type = "absolute";
  8334. qcom,scale-function = <0x0>;
  8335. qcom,hw-settle-time = <0x0>;
  8336. qcom,fast-avg-setup = <0x0>;
  8337. };
  8338. };
  8339.  
  8340. gpios {
  8341. spmi-dev-container;
  8342. compatible = "qcom,qpnp-pin";
  8343. gpio-controller;
  8344. #gpio-cells = <0x2>;
  8345. #address-cells = <0x1>;
  8346. #size-cells = <0x1>;
  8347. label = "pmi8950-gpio";
  8348.  
  8349. gpio@c000 {
  8350. reg = <0xc000 0x100>;
  8351. qcom,pin-num = <0x1>;
  8352. status = "disabled";
  8353. };
  8354.  
  8355. gpio@c100 {
  8356. reg = <0xc100 0x100>;
  8357. qcom,pin-num = <0x2>;
  8358. status = "disabled";
  8359. };
  8360. };
  8361.  
  8362. mpps {
  8363. spmi-dev-container;
  8364. compatible = "qcom,qpnp-pin";
  8365. gpio-controller;
  8366. #gpio-cells = <0x2>;
  8367. #address-cells = <0x1>;
  8368. #size-cells = <0x1>;
  8369. label = "pmi8950-mpp";
  8370.  
  8371. mpp@a000 {
  8372. reg = <0xa000 0x100>;
  8373. qcom,pin-num = <0x1>;
  8374. status = "disabled";
  8375. };
  8376.  
  8377. mpp@a100 {
  8378. reg = <0xa100 0x100>;
  8379. qcom,pin-num = <0x2>;
  8380. status = "disabled";
  8381. };
  8382.  
  8383. mpp@a200 {
  8384. reg = <0xa200 0x100>;
  8385. qcom,pin-num = <0x3>;
  8386. status = "disabled";
  8387. };
  8388.  
  8389. mpp@a300 {
  8390. reg = <0xa300 0x100>;
  8391. qcom,pin-num = <0x4>;
  8392. status = "disabled";
  8393. };
  8394. };
  8395.  
  8396. qcom,qpnp-smbcharger {
  8397. spmi-dev-container;
  8398. compatible = "qcom,qpnp-smbcharger";
  8399. #address-cells = <0x1>;
  8400. #size-cells = <0x1>;
  8401. qcom,iterm-ma = <0x64>;
  8402. qcom,resume-delta-mv = <0x32>;
  8403. qcom,chg-inhibit-fg;
  8404. qcom,rparasitic-uohm = <0x186a0>;
  8405. qcom,bms-psy-name = "bms";
  8406. qcom,pmic-revid = <0x11c>;
  8407. qcom,force-aicl-rerun;
  8408. qcom,aicl-rerun-period-s = <0xb4>;
  8409. qcom,autoadjust-vfloat;
  8410. qcom,battery-data = <0x11d>;
  8411. qcom,float-voltage-mv = <0x1130>;
  8412. qcom,thermal-mitigation = <0x7d0 0x4b0 0x3e8 0x320 0x320>;
  8413. qcom,charge-unknown-battery;
  8414. status = "okay";
  8415.  
  8416. qcom,chgr@1000 {
  8417. reg = <0x1000 0x100>;
  8418. interrupts = <0x2 0x10 0x0 0x2 0x10 0x1 0x2 0x10 0x2 0x2 0x10 0x3 0x2 0x10 0x4 0x2 0x10 0x5 0x2 0x10 0x6 0x2 0x10 0x7>;
  8419. interrupt-names = "chg-error", "chg-inhibit", "chg-prechg-sft", "chg-complete-chg-sft", "chg-p2f-thr", "chg-rechg-thr", "chg-taper-thr", "chg-tcc-thr";
  8420. };
  8421.  
  8422. qcom,otg@1100 {
  8423. reg = <0x1100 0x100>;
  8424. interrupts = <0x2 0x11 0x0 0x2 0x11 0x1 0x2 0x11 0x3>;
  8425. interrupt-names = "otg-fail", "otg-oc", "usbid-change";
  8426. };
  8427.  
  8428. qcom,bat-if@1200 {
  8429. reg = <0x1200 0x100>;
  8430. interrupts = <0x2 0x12 0x0 0x2 0x12 0x1 0x2 0x12 0x2 0x2 0x12 0x3 0x2 0x12 0x4 0x2 0x12 0x5 0x2 0x12 0x6 0x2 0x12 0x7>;
  8431. interrupt-names = "batt-hot", "batt-warm", "batt-cold", "batt-cool", "batt-ov", "batt-low", "batt-missing", "batt-term-missing";
  8432. };
  8433.  
  8434. qcom,usb-chgpth@1300 {
  8435. reg = <0x1300 0x100>;
  8436. interrupts = <0x2 0x13 0x0 0x2 0x13 0x1 0x2 0x13 0x2 0x2 0x13 0x5>;
  8437. interrupt-names = "usbin-uv", "usbin-ov", "usbin-src-det", "aicl-done";
  8438. };
  8439.  
  8440. qcom,dc-chgpth@1400 {
  8441. reg = <0x1400 0x100>;
  8442. interrupts = <0x2 0x14 0x0 0x2 0x14 0x1>;
  8443. interrupt-names = "dcin-uv", "dcin-ov";
  8444. };
  8445.  
  8446. qcom,chgr-misc@1600 {
  8447. reg = <0x1600 0x100>;
  8448. interrupts = <0x2 0x16 0x0 0x2 0x16 0x1 0x2 0x16 0x2 0x2 0x16 0x3 0x2 0x16 0x4 0x2 0x16 0x5>;
  8449. interrupt-names = "power-ok", "temp-shutdown", "wdog-timeout", "flash-fail", "otst2", "otst3";
  8450. };
  8451.  
  8452. qcom,smbcharger-boost-otg {
  8453. regulator-name = "smbcharger_charger_otg";
  8454. linux,phandle = <0x129>;
  8455. phandle = <0x129>;
  8456. };
  8457. };
  8458.  
  8459. qcom,fg {
  8460. spmi-dev-container;
  8461. compatible = "qcom,qpnp-fg";
  8462. #address-cells = <0x1>;
  8463. #size-cells = <0x1>;
  8464. qcom,resume-soc = <0x63>;
  8465. status = "okay";
  8466. qcom,bcl-lm-threshold-ma = <0x7f>;
  8467. qcom,bcl-mh-threshold-ma = <0x195>;
  8468. qcom,fg-iterm-ma = <0x96>;
  8469. qcom,fg-chg-iterm-ma = <0x64>;
  8470. qcom,pmic-revid = <0x11c>;
  8471. qcom,fg-cutoff-voltage-mv = <0xd48>;
  8472. qcom,cycle-counter-en;
  8473. qcom,capacity-learning-on;
  8474. qcom,battery-data = <0x11d>;
  8475. qcom,cold-bat-decidegc = <0x0>;
  8476. qcom,cool-bat-decidegc = <0x64>;
  8477. qcom,hot-bat-decidegc = <0x258>;
  8478. qcom,warm-bat-decidegc = <0x1c2>;
  8479. qcom,fg-cc-cv-threshold-mv = <0x1126>;
  8480. qcom,cl-max-increment-deciperc = <0x1>;
  8481. qcom,cl-max-decrement-deciperc = <0x1>;
  8482. qcom,fg-delta-soc = <0x1>;
  8483. qcom,bad-battery-detection-enable;
  8484. qcom,hold-soc-while-full;
  8485. qcom,thermal-coefficients = [c2 86 bb 50 cf 37];
  8486.  
  8487. qcom,fg-soc@4000 {
  8488. status = "okay";
  8489. reg = <0x4000 0x100>;
  8490. interrupts = <0x2 0x40 0x0 0x2 0x40 0x1 0x2 0x40 0x2 0x2 0x40 0x3 0x2 0x40 0x4 0x2 0x40 0x5 0x2 0x40 0x6>;
  8491. interrupt-names = "high-soc", "low-soc", "full-soc", "empty-soc", "delta-soc", "first-est-done", "update-soc";
  8492. };
  8493.  
  8494. qcom,fg-batt@4100 {
  8495. reg = <0x4100 0x100>;
  8496. interrupts = <0x2 0x41 0x0 0x2 0x41 0x1 0x2 0x41 0x2 0x2 0x41 0x3 0x2 0x41 0x4 0x2 0x41 0x5 0x2 0x41 0x6 0x2 0x41 0x7>;
  8497. interrupt-names = "soft-cold", "soft-hot", "vbatt-low", "batt-ided", "batt-id-req", "batt-unknown", "batt-missing", "batt-match";
  8498. };
  8499.  
  8500. qcom,revid-tp-rev@1f1 {
  8501. reg = <0x1f1 0x1>;
  8502. };
  8503.  
  8504. qcom,fg-memif@4400 {
  8505. status = "okay";
  8506. reg = <0x4400 0x100>;
  8507. interrupts = <0x2 0x44 0x0 0x2 0x44 0x2>;
  8508. interrupt-names = "mem-avail", "data-rcvry-sug";
  8509. };
  8510. };
  8511.  
  8512. bcl@4200 {
  8513. compatible = "qcom,msm-bcl";
  8514. reg = <0x4200 0xff 0x88e 0x2>;
  8515. reg-names = "fg_user_adc", "pon_spare";
  8516. interrupts = <0x2 0x42 0x0 0x2 0x42 0x1>;
  8517. interrupt-names = "bcl-high-ibat-int", "bcl-low-vbat-int";
  8518. qcom,vbat-scaling-factor = <0x9858>;
  8519. qcom,vbat-gain-numerator = <0x1>;
  8520. qcom,vbat-gain-denominator = <0x80>;
  8521. qcom,vbat-polling-delay-ms = <0x64>;
  8522. qcom,ibat-scaling-factor = <0x9858>;
  8523. qcom,ibat-gain-numerator = <0x1>;
  8524. qcom,ibat-gain-denominator = <0x80>;
  8525. qcom,ibat-offset-numerator = <0x4b0>;
  8526. qcom,ibat-offset-denominator = <0x1>;
  8527. qcom,ibat-polling-delay-ms = <0x64>;
  8528. qcom,inhibit-derating-ua = <0x86470>;
  8529. };
  8530.  
  8531. qcom,leds@a100 {
  8532. compatible = "qcom,leds-qpnp";
  8533. reg = <0xa100 0x100>;
  8534. label = "mpp";
  8535. status = "ok";
  8536.  
  8537. qcom,led_mpp_2 {
  8538. label = "mpp";
  8539. linux,name = "button-backlight";
  8540. linux,default-trigger = "none";
  8541. qcom,default-state = "off";
  8542. qcom,max-current = <0x28>;
  8543. qcom,current-setting = <0x5>;
  8544. qcom,id = <0x6>;
  8545. qcom,mode = "manual";
  8546. qcom,source-sel = <0x1>;
  8547. qcom,mode-ctrl = <0x60>;
  8548. };
  8549. };
  8550. };
  8551.  
  8552. qcom,pmi8950@3 {
  8553. spmi-slave-container;
  8554. reg = <0x3>;
  8555. #address-cells = <0x1>;
  8556. #size-cells = <0x1>;
  8557.  
  8558. pwm@b000 {
  8559. status = "disabled";
  8560. compatible = "qcom,qpnp-pwm";
  8561. reg = <0xb000 0x100>;
  8562. reg-names = "qpnp-lpg-channel-base";
  8563. qcom,channel-id = <0x0>;
  8564. qcom,supported-sizes = <0x6 0x9>;
  8565. #pwm-cells = <0x2>;
  8566. };
  8567.  
  8568. qpnp-labibb-regulator {
  8569. status = "ok";
  8570. spmi-dev-container;
  8571. compatible = "qcom,qpnp-labibb-regulator";
  8572. #address-cells = <0x1>;
  8573. #size-cells = <0x1>;
  8574. qcom,pmic-revid = <0x11c>;
  8575. qpnp,qpnp-labibb-mode = "lcd";
  8576.  
  8577. qcom,ibb@dc00 {
  8578. reg = <0xdc00 0x100>;
  8579. reg-names = "ibb_reg";
  8580. regulator-name = "ibb_reg";
  8581. regulator-min-microvolt = <0x4630c0>;
  8582. regulator-max-microvolt = <0x5b8d80>;
  8583. qcom,qpnp-ibb-min-voltage = <0x155cc0>;
  8584. qcom,qpnp-ibb-step-size = <0x186a0>;
  8585. qcom,qpnp-ibb-slew-rate = <0x1e8480>;
  8586. qcom,qpnp-ibb-init-voltage = <0x53ec60>;
  8587. qcom,qpnp-ibb-init-amoled-voltage = <0x3d0900>;
  8588. qcom,qpnp-ibb-init-lcd-voltage = <0x56f9a0>;
  8589. qcom,qpnp-ibb-soft-start = <0x3e8>;
  8590. qcom,qpnp-ibb-discharge-resistor = <0x20>;
  8591. qcom,qpnp-ibb-lab-pwrup-delay = <0x1f40>;
  8592. qcom,qpnp-ibb-lab-pwrdn-delay = <0x1f40>;
  8593. qcom,qpnp-ibb-en-discharge;
  8594. qcom,qpnp-ibb-full-pull-down;
  8595. qcom,qpnp-ibb-pull-down-enable;
  8596. qcom,qpnp-ibb-switching-clock-frequency = <0x5c8>;
  8597. qcom,qpnp-ibb-limit-maximum-current = <0x60e>;
  8598. qcom,qpnp-ibb-debounce-cycle = <0x10>;
  8599. qcom,qpnp-ibb-limit-max-current-enable;
  8600. qcom,qpnp-ibb-ps-enable;
  8601. linux,phandle = <0x19d>;
  8602. phandle = <0x19d>;
  8603. };
  8604.  
  8605. qcom,lab@de00 {
  8606. reg = <0xde00 0x100>;
  8607. reg-names = "lab";
  8608. regulator-name = "lab_reg";
  8609. regulator-min-microvolt = <0x4630c0>;
  8610. regulator-max-microvolt = <0x5b8d80>;
  8611. qcom,qpnp-lab-min-voltage = <0x4630c0>;
  8612. qcom,qpnp-lab-step-size = <0x186a0>;
  8613. qcom,qpnp-lab-slew-rate = <0x1388>;
  8614. qcom,qpnp-lab-use-default-voltage;
  8615. qcom,qpnp-lab-init-voltage = <0x53ec60>;
  8616. qcom,qpnp-lab-init-amoled-voltage = <0x4630c0>;
  8617. qcom,qpnp-lab-init-lcd-voltage = <0x53ec60>;
  8618. qcom,qpnp-lab-soft-start = <0x320>;
  8619. qcom,qpnp-lab-full-pull-down;
  8620. qcom,qpnp-lab-pull-down-enable;
  8621. qcom,qpnp-lab-switching-clock-frequency = <0x640>;
  8622. qcom,qpnp-lab-limit-maximum-current = <0x320>;
  8623. qcom,qpnp-lab-limit-max-current-enable;
  8624. qcom,qpnp-lab-ps-threshold = <0x28>;
  8625. qcom,qpnp-lab-ps-enable;
  8626. qcom,qpnp-lab-nfet-size = <0x64>;
  8627. qcom,qpnp-lab-pfet-size = <0x64>;
  8628. qcom,qpnp-lab-max-precharge-time = <0x12c>;
  8629. qcom,qpnp-ibb-init-lcd-voltage = <0x56f9a0>;
  8630. linux,phandle = <0x19c>;
  8631. phandle = <0x19c>;
  8632. };
  8633. };
  8634.  
  8635. qcom,leds@d800 {
  8636. compatible = "qcom,qpnp-wled";
  8637. reg = <0xd800 0x100 0xd900 0x100 0xdc00 0x100 0xde00 0x100>;
  8638. reg-names = "qpnp-wled-ctrl-base", "qpnp-wled-sink-base", "qpnp-wled-ibb-base", "qpnp-wled-lab-base";
  8639. interrupts = <0x3 0xd8 0x2>;
  8640. interrupt-names = "sc-irq";
  8641. status = "okay";
  8642. linux,name = "wled";
  8643. linux,default-trigger = "bkl-trigger";
  8644. qcom,fdbk-output = "auto";
  8645. qcom,vref-mv = <0x15e>;
  8646. qcom,switch-freq-khz = <0x320>;
  8647. qcom,ovp-mv = <0x733c>;
  8648. qcom,ilim-ma = <0x3d4>;
  8649. qcom,boost-duty-ns = <0x1a>;
  8650. qcom,mod-freq-khz = <0x2580>;
  8651. qcom,dim-mode = "hybrid";
  8652. qcom,dim-method = "linear";
  8653. qcom,hyb-thres = <0x271>;
  8654. qcom,sync-dly-us = <0x320>;
  8655. qcom,fs-curr-ua = <0x4e20>;
  8656. qcom,en-phase-stag;
  8657. qcom,ibb-pwrup-dly = <0x8>;
  8658. qcom,led-strings-list = [00 01];
  8659. qcom,en-ext-pfet-sc-pro;
  8660. qcom,cons-sync-write-delay-us = <0x3e8>;
  8661. };
  8662.  
  8663. qcom,leds@d300 {
  8664. compatible = "qcom,qpnp-flash-led";
  8665. status = "okay";
  8666. reg = <0xd300 0x100>;
  8667. label = "flash";
  8668. qcom,headroom = <0x1f4>;
  8669. qcom,startup-dly = <0x80>;
  8670. qcom,clamp-curr = <0xc8>;
  8671. qcom,pmic-charger-support;
  8672. qcom,self-check-enabled;
  8673. qcom,thermal-derate-enabled;
  8674. qcom,thermal-derate-threshold = <0x64>;
  8675. qcom,thermal-derate-rate = "5_PERCENT";
  8676. qcom,current-ramp-enabled;
  8677. qcom,ramp_up_step = "6P7_US";
  8678. qcom,ramp_dn_step = "6P7_US";
  8679. qcom,vph-pwr-droop-enabled;
  8680. qcom,vph-pwr-droop-threshold = <0xbb8>;
  8681. qcom,vph-pwr-droop-debounce-time = <0xa>;
  8682. qcom,headroom-sense-ch0-enabled;
  8683. qcom,headroom-sense-ch1-enabled;
  8684. qcom,pmic-revid = <0x11c>;
  8685.  
  8686. qcom,flash_0 {
  8687. label = "flash";
  8688. qcom,led-name = "led:flash_0";
  8689. qcom,default-led-trigger = "flash0_trigger";
  8690. qcom,max-current = <0x3e8>;
  8691. qcom,duration = <0x500>;
  8692. qcom,id = <0x0>;
  8693. qcom,current = <0x2ee>;
  8694. linux,phandle = <0x1a7>;
  8695. phandle = <0x1a7>;
  8696. };
  8697.  
  8698. qcom,flash_1 {
  8699. label = "flash";
  8700. qcom,led-name = "led:flash_1";
  8701. qcom,default-led-trigger = "flash1_trigger";
  8702. qcom,max-current = <0x3e8>;
  8703. qcom,duration = <0x500>;
  8704. qcom,id = <0x1>;
  8705. qcom,current = <0x2ee>;
  8706. linux,phandle = <0x1a8>;
  8707. phandle = <0x1a8>;
  8708. };
  8709.  
  8710. qcom,torch_0 {
  8711. label = "torch";
  8712. qcom,led-name = "led:torch_0";
  8713. qcom,default-led-trigger = "torch0_trigger";
  8714. qcom,max-current = <0xc8>;
  8715. qcom,id = <0x0>;
  8716. qcom,current = <0x64>;
  8717. linux,phandle = <0x1a9>;
  8718. phandle = <0x1a9>;
  8719. };
  8720.  
  8721. qcom,torch_1 {
  8722. label = "torch";
  8723. qcom,led-name = "led:torch_1";
  8724. qcom,default-led-trigger = "torch1_trigger";
  8725. qcom,max-current = <0xc8>;
  8726. qcom,id = <0x1>;
  8727. qcom,current = <0x64>;
  8728. linux,phandle = <0x1aa>;
  8729. phandle = <0x1aa>;
  8730. };
  8731.  
  8732. qcom,torch_2 {
  8733. label = "torch";
  8734. qcom,led-name = "flashlight";
  8735. qcom,default-led-trigger = "torch2_trigger";
  8736. qcom,max-current = <0xc8>;
  8737. qcom,id = <0x1>;
  8738. qcom,current = <0x64>;
  8739. linux,phandle = <0x1ab>;
  8740. phandle = <0x1ab>;
  8741. };
  8742.  
  8743. qcom,switch {
  8744. label = "switch";
  8745. qcom,led-name = "led:switch";
  8746. qcom,default-led-trigger = "switch_trigger";
  8747. qcom,max-current = <0x3e8>;
  8748. qcom,duration = <0x500>;
  8749. qcom,id = <0x2>;
  8750. qcom,current = <0x271>;
  8751. linux,phandle = <0x1ac>;
  8752. phandle = <0x1ac>;
  8753.  
  8754. reg0 {
  8755. regulator-name = "pon_spare_reg";
  8756. };
  8757. };
  8758. };
  8759.  
  8760. qcom,haptic@c000 {
  8761. compatible = "qcom,qpnp-haptic";
  8762. reg = <0xc000 0x100>;
  8763. interrupts = <0x3 0xc0 0x0 0x3 0xc0 0x1>;
  8764. interrupt-names = "sc-irq", "play-irq";
  8765. qcom,play-mode = "direct";
  8766. qcom,wave-play-rate-us = <0x148f>;
  8767. qcom,actuator-type = "erm";
  8768. qcom,wave-shape = "square";
  8769. qcom,vmax-mv = <0x7d0>;
  8770. qcom,ilim-ma = <0x320>;
  8771. qcom,sc-deb-cycles = <0x8>;
  8772. qcom,int-pwm-freq-khz = <0x1f9>;
  8773. qcom,en-brake;
  8774. qcom,brake-pattern = <0x3030000>;
  8775. qcom,use-play-irq;
  8776. qcom,use-sc-irq;
  8777. qcom,wave-samples = <0x3e3e3e3e 0x3e3e3e3e>;
  8778. qcom,wave-rep-cnt = <0x1>;
  8779. qcom,wave-samp-rep-cnt = <0x1>;
  8780. };
  8781. };
  8782. };
  8783.  
  8784. qcom,mss@4080000 {
  8785. compatible = "qcom,pil-q6v55-mss";
  8786. reg = <0x4080000 0x100 0x194f000 0x10 0x1950000 0x8 0x1951000 0x8 0x4020000 0x40 0x1871000 0x4>;
  8787. reg-names = "qdsp6_base", "halt_q6", "halt_modem", "halt_nc", "rmb_base", "restart_reg";
  8788. interrupts = <0x0 0x18 0x1>;
  8789. vdd_mss-supply = <0x11e>;
  8790. vdd_cx-supply = <0xf4>;
  8791. vdd_cx-voltage = <0x180>;
  8792. vdd_mx-supply = <0xf7>;
  8793. vdd_mx-uV = <0x180>;
  8794. vdd_pll-supply = <0xfb>;
  8795. qcom,vdd_pll = <0x1b7740>;
  8796. clocks = <0x37 0xe97a8354 0x37 0x111cde81 0x37 0x67544d62 0x37 0xde2adeb1>;
  8797. clock-names = "xo", "iface_clk", "bus_clk", "mem_clk";
  8798. qcom,proxy-clock-names = "xo";
  8799. qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk";
  8800. qcom,firmware-name = "modem";
  8801. qcom,pil-self-auth;
  8802. qcom,sysmon-id = <0x0>;
  8803. qcom,ssctl-instance-id = <0x12>;
  8804. qcom,qdsp6v56-1-10;
  8805. qcom,gpio-err-fatal = <0x11f 0x0 0x0>;
  8806. qcom,gpio-err-ready = <0x11f 0x1 0x0>;
  8807. qcom,gpio-proxy-unvote = <0x11f 0x2 0x0>;
  8808. qcom,gpio-stop-ack = <0x11f 0x3 0x0>;
  8809. qcom,gpio-shutdown-ack = <0x11f 0x7 0x0>;
  8810. qcom,gpio-force-stop = <0x120 0x0 0x0>;
  8811. memory-region = <0x121>;
  8812. };
  8813.  
  8814. qcom,lpass@c200000 {
  8815. compatible = "qcom,pil-tz-generic";
  8816. reg = <0xc200000 0x100>;
  8817. interrupts = <0x0 0x125 0x1>;
  8818. vdd_cx-supply = <0xf4>;
  8819. qcom,proxy-reg-names = "vdd_cx";
  8820. qcom,vdd_cx-uV-uA = <0x180 0x186a0>;
  8821. clocks = <0x37 0xb72aa4c9 0x37 0xd390d2 0x37 0x94de4919 0x37 0xd4415c9b 0x37 0x37a21414>;
  8822. clock-names = "xo", "scm_core_clk", "scm_iface_clk", "scm_bus_clk", "scm_core_clk_src";
  8823. qcom,proxy-clock-names = "xo", "scm_core_clk", "scm_iface_clk", "scm_bus_clk", "scm_core_clk_src";
  8824. qcom,scm_core_clk_src-freq = <0x4c4b400>;
  8825. qcom,pas-id = <0x1>;
  8826. qcom,complete-ramdump;
  8827. qcom,proxy-timeout-ms = <0x2710>;
  8828. qcom,smem-id = <0x1a7>;
  8829. qcom,sysmon-id = <0x1>;
  8830. qcom,ssctl-instance-id = <0x14>;
  8831. qcom,firmware-name = "adsp";
  8832. qcom,gpio-err-fatal = <0x122 0x0 0x0>;
  8833. qcom,gpio-proxy-unvote = <0x122 0x2 0x0>;
  8834. qcom,gpio-err-ready = <0x122 0x1 0x0>;
  8835. qcom,gpio-stop-ack = <0x122 0x3 0x0>;
  8836. qcom,gpio-force-stop = <0x123 0x0 0x0>;
  8837. memory-region = <0x124>;
  8838. };
  8839.  
  8840. qcom,venus@1de0000 {
  8841. compatible = "qcom,pil-tz-generic";
  8842. reg = <0x1de0000 0x4000>;
  8843. vdd-supply = <0xb8>;
  8844. qcom,proxy-reg-names = "vdd";
  8845. clocks = <0x37 0xf76a02bb 0x37 0x8d778c6 0x37 0xcdf4c8f6 0x37 0xd390d2 0x37 0x94de4919 0x37 0xd4415c9b 0x37 0x37a21414>;
  8846. clock-names = "core_clk", "iface_clk", "bus_clk", "scm_core_clk", "scm_iface_clk", "scm_bus_clk", "scm_core_clk_src";
  8847. qcom,proxy-clock-names = "core_clk", "iface_clk", "bus_clk", "scm_core_clk", "scm_iface_clk", "scm_bus_clk", "scm_core_clk_src";
  8848. qcom,scm_core_clk_src-freq = <0x4c4b400>;
  8849. qcom,msm-bus,name = "pil-venus";
  8850. qcom,msm-bus,num-cases = <0x2>;
  8851. qcom,msm-bus,num-paths = <0x1>;
  8852. qcom,msm-bus,vectors-KBps = <0x3f 0x200 0x0 0x0 0x3f 0x200 0x0 0x4a380>;
  8853. qcom,pas-id = <0x9>;
  8854. qcom,proxy-timeout-ms = <0x64>;
  8855. qcom,firmware-name = "venus";
  8856. memory-region = <0x125>;
  8857. };
  8858.  
  8859. qcom,msm-ssc-sensors {
  8860. compatible = "qcom,msm-ssc-sensors";
  8861. };
  8862.  
  8863. qcom,pronto@a21b000 {
  8864. compatible = "qcom,pil-tz-generic";
  8865. reg = <0xa21b000 0x3000>;
  8866. interrupts = <0x0 0x95 0x1>;
  8867. vdd_pronto_pll-supply = <0xfb>;
  8868. proxy-reg-names = "vdd_pronto_pll";
  8869. vdd_pronto_pll-uV-uA = <0x1b7740 0x4650>;
  8870. clocks = <0x37 0x89dae6d0 0x37 0xd390d2 0x37 0x94de4919 0x37 0xd4415c9b 0x37 0x37a21414>;
  8871. clock-names = "xo", "scm_core_clk", "scm_iface_clk", "scm_bus_clk", "scm_core_clk_src";
  8872. qcom,proxy-clock-names = "xo", "scm_core_clk", "scm_iface_clk", "scm_bus_clk", "scm_core_clk_src";
  8873. qcom,scm_core_clk_src = <0x4c4b400>;
  8874. qcom,pas-id = <0x6>;
  8875. qcom,proxy-timeout-ms = <0x2710>;
  8876. qcom,smem-id = <0x1a6>;
  8877. qcom,sysmon-id = <0x6>;
  8878. qcom,ssctl-instance-id = <0x13>;
  8879. qcom,firmware-name = "wcnss";
  8880. qcom,gpio-err-fatal = <0x126 0x0 0x0>;
  8881. qcom,gpio-err-ready = <0x126 0x1 0x0>;
  8882. qcom,gpio-proxy-unvote = <0x126 0x2 0x0>;
  8883. qcom,gpio-stop-ack = <0x126 0x3 0x0>;
  8884. qcom,gpio-force-stop = <0x127 0x0 0x0>;
  8885. memory-region = <0x124>;
  8886. };
  8887.  
  8888. ssusb@7000000 {
  8889. compatible = "qcom,dwc-usb3-msm";
  8890. reg = <0x7000000 0xfc000 0x7e000 0x400>;
  8891. reg-names = "core_base", "ahb2phy_base";
  8892. #address-cells = <0x1>;
  8893. #size-cells = <0x1>;
  8894. ranges;
  8895. interrupts = <0x0 0x88 0x0 0x0 0xdc 0x0 0x0 0x86 0x0>;
  8896. interrupt-names = "hs_phy_irq", "ss_phy_irq", "pwr_event_irq";
  8897. USB3_GDSC-supply = <0x128>;
  8898. vbus_dwc3-supply = <0x129>;
  8899. qcom,usb-dbm = <0x12a>;
  8900. qcom,msm-bus,name = "usb3";
  8901. qcom,msm-bus,num-cases = <0x2>;
  8902. qcom,msm-bus,num-paths = <0x1>;
  8903. qcom,msm-bus,vectors-KBps = <0x3d 0x200 0x0 0x0 0x3d 0x200 0x3a980 0xc3500>;
  8904. qcom,dwc-usb3-msm-tx-fifo-size = <0x5328>;
  8905. clocks = <0x37 0xb3b4e2cb 0x37 0xf7f4b314 0x37 0xa800b65a 0x37 0xd0b65c92 0x37 0xfad488ce 0x37 0xccb7e26f>;
  8906. clock-names = "core_clk", "iface_clk", "utmi_clk", "sleep_clk", "xo", "cfg_ahb_clk";
  8907.  
  8908. dwc3@7000000 {
  8909. compatible = "snps,dwc3";
  8910. reg = <0x7000000 0xc8d0>;
  8911. interrupt-parent = <0x1>;
  8912. interrupts = <0x0 0x8c 0x0>;
  8913. usb-phy = <0x12b 0x12c>;
  8914. tx-fifo-resize;
  8915. snps,usb3-u1u2-disable;
  8916. snps,nominal-elastic-buffer;
  8917. snps,is-utmi-l1-suspend;
  8918. snps,hird-threshold = [00];
  8919. };
  8920.  
  8921. qcom,usbbam@7104000 {
  8922. compatible = "qcom,usb-bam-msm";
  8923. reg = <0x7104000 0x1a934>;
  8924. interrupt-parent = <0x1>;
  8925. interrupts = <0x0 0x87 0x0>;
  8926. qcom,bam-type = <0x0>;
  8927. qcom,usb-bam-fifo-baseaddr = "\b`P";
  8928. qcom,usb-bam-num-pipes = <0x8>;
  8929. qcom,ignore-core-reset-ack;
  8930. qcom,disable-clk-gating;
  8931. qcom,usb-bam-override-threshold = <0x4001>;
  8932. qcom,usb-bam-max-mbps-highspeed = <0x190>;
  8933. qcom,usb-bam-max-mbps-superspeed = <0xe10>;
  8934. qcom,reset-bam-on-connect;
  8935.  
  8936. qcom,pipe0 {
  8937. label = "ssusb-ipa-out-0";
  8938. qcom,usb-bam-mem-type = <0x1>;
  8939. qcom,dir = <0x0>;
  8940. qcom,pipe-num = <0x0>;
  8941. qcom,peer-bam = <0x1>;
  8942. qcom,src-bam-pipe-index = <0x1>;
  8943. qcom,data-fifo-size = <0x8000>;
  8944. qcom,descriptor-fifo-size = <0x2000>;
  8945. };
  8946.  
  8947. qcom,pipe1 {
  8948. label = "ssusb-ipa-in-0";
  8949. qcom,usb-bam-mem-type = <0x1>;
  8950. qcom,dir = <0x1>;
  8951. qcom,pipe-num = <0x0>;
  8952. qcom,peer-bam = <0x1>;
  8953. qcom,dst-bam-pipe-index = <0x0>;
  8954. qcom,data-fifo-size = <0x8000>;
  8955. qcom,descriptor-fifo-size = <0x2000>;
  8956. };
  8957.  
  8958. qcom,pipe2 {
  8959. label = "ssusb-qdss-in-0";
  8960. qcom,usb-bam-mem-type = <0x2>;
  8961. qcom,dir = <0x1>;
  8962. qcom,pipe-num = <0x0>;
  8963. qcom,peer-bam = <0x0>;
  8964. qcom,peer-bam-physical-address = <0x6044000>;
  8965. qcom,src-bam-pipe-index = <0x0>;
  8966. qcom,dst-bam-pipe-index = <0x2>;
  8967. qcom,data-fifo-offset = <0x0>;
  8968. qcom,data-fifo-size = <0xe00>;
  8969. qcom,descriptor-fifo-offset = <0xe00>;
  8970. qcom,descriptor-fifo-size = <0x200>;
  8971. };
  8972.  
  8973. qcom,pipe3 {
  8974. label = "ssusb-dpl-ipa-in-1";
  8975. qcom,usb-bam-mem-type = <0x1>;
  8976. qcom,dir = <0x1>;
  8977. qcom,pipe-num = <0x1>;
  8978. qcom,peer-bam = <0x1>;
  8979. qcom,dst-bam-pipe-index = <0x2>;
  8980. qcom,data-fifo-size = <0x8000>;
  8981. qcom,descriptor-fifo-size = <0x2000>;
  8982. };
  8983. };
  8984. };
  8985.  
  8986. qusb@79000 {
  8987. compatible = "qcom,qusb2phy";
  8988. reg = <0x79000 0x180 0x70f8800 0x400 0x1841030 0x4 0x193f044 0x4>;
  8989. reg-names = "qusb_phy_base", "qscratch_base", "ref_clk_addr", "tcsr_phy_clk_scheme_sel";
  8990. vdd-supply = <0x12d>;
  8991. vdda18-supply = <0xfb>;
  8992. vdda33-supply = <0xf3>;
  8993. qcom,vdd-voltage-level = <0x0 0xe1d48 0xe1d48>;
  8994. qcom,qusb-phy-init-seq = <0xf8 0x80 0xb3 0x84 0x83 0x88 0xc0 0x8c 0x14 0x9c 0x30 0x8 0x79 0xc 0x21 0x10 0x0 0x90 0x9f 0x1c 0x0 0x18>;
  8995. phy_type = "utmi";
  8996. clocks = <0x37 0xf5304268 0x37 0x16e35a90 0x37 0xccb7e26f 0x37 0x3ce5fa84>;
  8997. clock-names = "ref_clk_src", "ref_clk", "cfg_ahb_clk", "phy_reset";
  8998. linux,phandle = <0x12b>;
  8999. phandle = <0x12b>;
  9000. };
  9001.  
  9002. usb_nop_phy {
  9003. status = "disabled";
  9004. compatible = "usb-nop-xceiv";
  9005. };
  9006.  
  9007. ssphy@78000 {
  9008. compatible = "qcom,usb-ssphy-qmp";
  9009. reg = <0x78000 0x9f8 0x193f244 0x4 0x193f044 0x4>;
  9010. reg-names = "qmp_phy_base", "vls_clamp_reg", "tcsr_phy_clk_scheme_sel";
  9011. qcom,qmp-phy-init-seq = <0xac 0x14 0x1a 0x0 0x34 0x8 0x8 0x0 0x174 0x30 0x30 0x0 0x3c 0x6 0x6 0x0 0xb4 0x0 0x0 0x0 0xb8 0x8 0x8 0x0 0x194 0x6 0x6 0x3e8 0x19c 0x1 0x1 0x0 0x178 0x0 0x0 0x0 0xd0 0x82 0x82 0x0 0xdc 0x55 0x55 0x0 0xe0 0x55 0x55 0x0 0xe4 0x3 0x3 0x0 0x78 0xb 0xb 0x0 0x84 0x16 0x16 0x0 0x90 0x28 0x28 0x0 0x108 0x80 0x80 0x0 0x10c 0x0 0x0 0x0 0x184 0xa 0xa 0x0 0x4c 0x15 0x15 0x0 0x50 0x34 0x34 0x0 0x54 0x0 0x0 0x0 0xc8 0x0 0x0 0x0 0x18c 0x0 0x0 0x0 0xcc 0x0 0x0 0x0 0x128 0x0 0x0 0x0 0xc 0xa 0xa 0x0 0x10 0x1 0x1 0x0 0x1c 0x31 0x31 0x0 0x20 0x1 0x1 0x0 0x14 0x0 0x0 0x0 0x18 0x0 0x0 0x0 0x24 0xde 0xde 0x0 0x28 0x7 0x7 0x0 0x48 0xf 0xf 0x0 0x70 0xf 0xf 0x0 0x100 0x80 0x80 0x0 0x440 0xb 0xb 0x0 0x4d8 0x2 0x2 0x0 0x4dc 0x6c 0x6c 0x0 0x4e0 0xbb 0xbb 0x0 0x508 0x77 0x77 0x0 0x50c 0x80 0x80 0x0 0x514 0x3 0x3 0x0 0x51c 0x16 0x16 0x0 0x448 0x75 0x75 0x0 0x454 0x0 0x0 0x0 0x40c 0xa 0xa 0x0 0x41c 0x6 0x6 0x0 0x510 0x0 0x0 0x0 0x268 0x45 0x45 0x0 0x2ac 0x12 0x12 0x0 0x294 0x6 0x6 0x0 0x254 0x0 0x0 0x0 0x8c8 0x83 0x83 0x0 0x8c4 0x2 0x2 0x0 0x8cc 0x9 0x9 0x0 0x8d0 0xa2 0xa2 0x0 0x8d4 0x85 0x85 0x0 0x880 0xd1 0xd1 0x0 0x884 0x1f 0x1f 0x0 0x888 0x47 0x47 0x0 0x80c 0x9f 0x9f 0x0 0x824 0x17 0x17 0x0 0x828 0xf 0xf 0x0 0x8b8 0x75 0x75 0x0 0x8bc 0x13 0x13 0x0 0x8b0 0x86 0x86 0x0 0x8a0 0x4 0x4 0x0 0x88c 0x44 0x44 0x0 0x870 0xe7 0xe7 0x0 0x874 0x3 0x3 0x0 0x878 0x40 0x40 0x0 0x87c 0x0 0x0 0x0 0x9d8 0x88 0x88 0x0 0xffffffff 0xffffffff 0x0 0x0>;
  9012. qcom,qmp-phy-reg-offset = <0x988 0x98c 0x990 0x994 0x974 0x8d8 0x8dc 0x804 0x800 0x808>;
  9013. vdd-supply = <0x12d>;
  9014. vdda18-supply = <0xfb>;
  9015. qcom,vdd-voltage-level = <0x0 0xe1d48 0xe1d48>;
  9016. qcom,vbus-valid-override;
  9017. clocks = <0x37 0x555d16b2 0x37 0x26f8a97a 0x37 0xccb7e26f 0x37 0x3d559f1 0x37 0xb1a4f885 0x37 0xf5304268 0x37 0xb85dadfa>;
  9018. clock-names = "aux_clk", "pipe_clk", "cfg_ahb_clk", "phy_reset", "phy_phy_reset", "ref_clk_src", "ref_clk";
  9019. linux,phandle = <0x12c>;
  9020. phandle = <0x12c>;
  9021. };
  9022.  
  9023. dbm@70f8000 {
  9024. compatible = "qcom,usb-dbm-1p5";
  9025. reg = <0x70f8000 0x300>;
  9026. qcom,reset-ep-after-lpm-resume;
  9027. linux,phandle = <0x12a>;
  9028. phandle = <0x12a>;
  9029. };
  9030.  
  9031. android_usb@86000c8 {
  9032. compatible = "qcom,android-usb";
  9033. reg = <0x86000c8 0xc8>;
  9034. qcom,pm-qos-latency = <0x2 0xd5 0x2b14>;
  9035. };
  9036.  
  9037. regulator@019461d4 {
  9038. compatible = "qcom,mem-acc-regulator";
  9039. reg = <0x19461d4 0x4 0x19461d8 0x4>;
  9040. reg-names = "acc-sel-l1", "acc-sel-l2";
  9041. regulator-name = "apc_mem_acc_corner";
  9042. regulator-min-microvolt = <0x1>;
  9043. regulator-max-microvolt = <0x2>;
  9044. qcom,corner-acc-map = <0x1 0x0>;
  9045. qcom,acc-sel-l1-bit-pos = <0x0>;
  9046. qcom,acc-sel-l1-bit-size = <0x1>;
  9047. qcom,acc-sel-l2-bit-pos = <0x0>;
  9048. qcom,acc-sel-l2-bit-size = <0x1>;
  9049. linux,phandle = <0x131>;
  9050. phandle = <0x131>;
  9051. };
  9052.  
  9053. cpr4-ctrl@b018000 {
  9054. compatible = "qcom,cpr4-msm8953-apss-regulator";
  9055. reg = <0xb018000 0x4000 0xa4000 0x1000>;
  9056. reg-names = "cpr_ctrl", "fuse_base";
  9057. interrupts = <0x0 0xf 0x1>;
  9058. interrupt-names = "cpr";
  9059. qcom,cpr-ctrl-name = "apc";
  9060. qcom,cpr-sensor-time = <0x3e8>;
  9061. qcom,cpr-loop-time = <0x4c4b40>;
  9062. qcom,cpr-idle-cycles = <0xf>;
  9063. qcom,cpr-step-quot-init-min = <0xc>;
  9064. qcom,cpr-step-quot-init-max = <0xe>;
  9065. qcom,cpr-count-mode = <0x0>;
  9066. qcom,cpr-count-repeat = <0x1>;
  9067. qcom,cpr-down-error-step-limit = <0x1>;
  9068. qcom,cpr-up-error-step-limit = <0x1>;
  9069. qcom,apm-ctrl = <0x12e>;
  9070. qcom,apm-threshold-voltage = <0xcf850>;
  9071. qcom,apm-hysteresis-voltage = <0x1388>;
  9072. vdd-supply = <0x12f>;
  9073. qcom,voltage-step = <0x1388>;
  9074. vdd-limit-supply = <0x130>;
  9075. mem-acc-supply = <0x131>;
  9076. qcom,cpr-enable;
  9077. qcom,cpr-hw-closed-loop;
  9078.  
  9079. thread@0 {
  9080. qcom,cpr-thread-id = <0x0>;
  9081. qcom,cpr-consecutive-up = <0x0>;
  9082. qcom,cpr-consecutive-down = <0x2>;
  9083. qcom,cpr-up-threshold = <0x2>;
  9084. qcom,cpr-down-threshold = <0x2>;
  9085.  
  9086. regulator {
  9087. regulator-name = "apc_corner";
  9088. regulator-min-microvolt = <0x1>;
  9089. regulator-max-microvolt = <0x9>;
  9090. qcom,cpr-fuse-corners = <0x4>;
  9091. qcom,cpr-fuse-combos = <0x40>;
  9092. qcom,cpr-speed-bins = <0x8>;
  9093. qcom,cpr-speed-bin-corners = <0x9 0x0 0x7 0x0 0x0 0x0 0x0 0x9>;
  9094. qcom,cpr-corners = <0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x7 0x7 0x7 0x7 0x7 0x7 0x7 0x7 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9>;
  9095. qcom,cpr-corner-fmax-map = <0x1 0x2 0x4 0x9 0x0 0x0 0x0 0x0 0x1 0x2 0x4 0x7 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x1 0x2 0x4 0x9>;
  9096. qcom,cpr-voltage-ceiling = <0xae8f8 0xc0df0 0xd1f60 0xd32e8 0xe09c0 0xf1b30 0x104028 0x104028 0x104028 0xae8f8 0xc0df0 0xd1f60 0xd32e8 0xe09c0 0xf1b30 0x104028 0xae8f8 0xc0df0 0xd1f60 0xd32e8 0xe09c0 0xf1b30 0x104028 0x104028 0x104028>;
  9097. qcom,cpr-voltage-floor = <0x7a120 0x7a120 0x7a120 0x7a120 0x7a120 0x7a120 0x7a120 0x7a120 0x7a120 0x7a120 0x7a120 0x7a120 0x7a120 0x7a120 0x7a120 0x7a120 0x7a120 0x7a120 0x7a120 0x7a120 0x7a120 0x7a120 0x7a120 0x7a120 0x7a120>;
  9098. qcom,cpr-floor-to-ceiling-max-range = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350 0xc350>;
  9099. qcom,cpr-misc-fuse-voltage-adjustment = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x7530 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x7530 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x7530 0x0 0x0 0x0 0x0 0x0 0x0>;
  9100. qcom,mem-acc-voltage = <0x1 0x1 0x2 0x2 0x2 0x2 0x2 0x2 0x2 0x1 0x1 0x2 0x2 0x2 0x2 0x2 0x1 0x1 0x2 0x2 0x2 0x2 0x2 0x2 0x2>;
  9101. qcom,corner-frequencies = <0x26e8f000 0x3dcc5000 0x538ab800 0x64b54000 0x6ddd0000 0x74bad000 0x7829b800 0x802c8000 0x839b6800 0x26e8f000 0x3dcc5000 0x538ab800 0x64b54000 0x6ddd0000 0x74bad000 0x7829b800 0x26e8f000 0x3dcc5000 0x538ab800 0x64b54000 0x6ddd0000 0x74bad000 0x7829b800 0x802c8000 0x839b6800>;
  9102. qcom,cpr-open-loop-voltage-fuse-adjustment = <0x0 0x0 0x0 0x0 0x61a8 0x0 0x1388 0x9c40 0x61a8 0x0 0x1388 0x9c40 0x61a8 0x0 0x1388 0x9c40 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x61a8 0x0 0x1388 0x9c40 0x61a8 0x0 0x1388 0x9c40 0x61a8 0x0 0x1388 0x9c40 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x61a8 0x0 0x1388 0x9c40 0x61a8 0x0 0x1388 0x9c40 0x61a8 0x0 0x1388 0x9c40 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
  9103. qcom,cpr-closed-loop-voltage-fuse-adjustment = <0x0 0x0 0x0 0x0 0x2710 0xffffc568 0x0 0x61a8 0x2710 0xffffc568 0x0 0x61a8 0x2710 0xffffc568 0x0 0x61a8 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x2710 0xffffc568 0x0 0x61a8 0x2710 0xffffc568 0x0 0x61a8 0x2710 0xffffc568 0x0 0x61a8 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x2710 0xffffc568 0x0 0x61a8 0x2710 0xffffc568 0x0 0x61a8 0x2710 0xffffc568 0x0 0x61a8 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
  9104. qcom,cpr-ro-scaling-factor = <0xe1a 0xece 0x0 0x898 0x992 0x906 0x87a 0x8a2 0x91a 0x8a2 0x9a6 0x924 0x30c 0xa8c 0x992 0x82a 0xe1a 0xece 0x0 0x898 0x992 0x906 0x87a 0x8a2 0x91a 0x8a2 0x9a6 0x924 0x30c 0xa8c 0x992 0x82a 0xe1a 0xece 0x0 0x898 0x992 0x906 0x87a 0x8a2 0x91a 0x8a2 0x9a6 0x924 0x30c 0xa8c 0x992 0x82a 0xe1a 0xece 0x0 0x898 0x992 0x906 0x87a 0x8a2 0x91a 0x8a2 0x9a6 0x924 0x30c 0xa8c 0x992 0x82a>;
  9105. qcom,allow-voltage-interpolation;
  9106. qcom,allow-quotient-interpolation;
  9107. qcom,cpr-scaled-open-loop-voltage-as-ceiling;
  9108. linux,phandle = <0xf8>;
  9109. phandle = <0xf8>;
  9110. };
  9111. };
  9112. };
  9113.  
  9114. regulator@0194415c {
  9115. compatible = "qcom,mem-acc-regulator";
  9116. reg = <0x194415c 0x4>;
  9117. reg-names = "acc-sel-l1";
  9118. regulator-name = "gfx_mem_acc_corner";
  9119. regulator-min-microvolt = <0x1>;
  9120. regulator-max-microvolt = <0x2>;
  9121. qcom,acc-sel-l1-bit-pos = <0x0>;
  9122. qcom,acc-sel-l1-bit-size = <0x1>;
  9123. qcom,corner-acc-map = <0x1 0x0>;
  9124. linux,phandle = <0x132>;
  9125. phandle = <0x132>;
  9126. };
  9127.  
  9128. ldo@0185f000 {
  9129. compatible = "qcom,msm8953-gfx-ldo";
  9130. reg = <0x185f000 0x30 0xa4000 0x1000>;
  9131. reg-names = "ldo_addr", "efuse_addr";
  9132. regulator-name = "msm_gfx_ldo";
  9133. regulator-min-microvolt = <0x1>;
  9134. regulator-max-microvolt = <0x7>;
  9135. qcom,ldo-voltage-ceiling = <0x975e0 0xa6040 0xb71b0>;
  9136. qcom,ldo-voltage-floor = <0x7c830 0x7c830 0x927c0>;
  9137. qcom,num-corners = <0x7>;
  9138. qcom,num-ldo-corners = <0x3>;
  9139. qcom,ldo-enable-corner-map = <0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
  9140. qcom,init-corner = <0x4>;
  9141. vdd-cx-supply = <0xf4>;
  9142. qcom,vdd-cx-corner-map = <0x40 0x40 0x80 0xc0 0x100 0x140 0x180>;
  9143. mem-acc-supply = <0x132>;
  9144. qcom,mem-acc-corner-map = <0x1 0x1 0x1 0x2 0x2 0x2 0x2>;
  9145. linux,phandle = <0xc8>;
  9146. phandle = <0xc8>;
  9147. };
  9148.  
  9149. eldo2 {
  9150. compatible = "regulator-fixed";
  9151. regulator-name = "eldo2_8953";
  9152. startup-delay-us = <0x0>;
  9153. enable-active-high;
  9154. gpio = <0xbe 0x32 0x0>;
  9155. regulator-always-on;
  9156. linux,phandle = <0xf2>;
  9157. phandle = <0xf2>;
  9158. };
  9159.  
  9160. adv_vreg {
  9161. compatible = "regulator-fixed";
  9162. regulator-name = "adv_vreg";
  9163. startup-delay-us = <0x190>;
  9164. enable-active-high;
  9165. gpio = <0xea 0x5 0x0>;
  9166. linux,phandle = <0xd7>;
  9167. phandle = <0xd7>;
  9168. };
  9169.  
  9170. qcom,msm-pcm {
  9171. compatible = "qcom,msm-pcm-dsp";
  9172. qcom,msm-pcm-dsp-id = <0x0>;
  9173. linux,phandle = <0x13f>;
  9174. phandle = <0x13f>;
  9175. };
  9176.  
  9177. qcom,msm-pcm-routing {
  9178. compatible = "qcom,msm-pcm-routing";
  9179. linux,phandle = <0x149>;
  9180. phandle = <0x149>;
  9181. };
  9182.  
  9183. qcom,msm-ultra-low-latency {
  9184. compatible = "qcom,msm-pcm-dsp";
  9185. qcom,msm-pcm-dsp-id = <0x2>;
  9186. qcom,msm-pcm-low-latency;
  9187. qcom,latency-level = "ultra";
  9188. linux,phandle = <0x141>;
  9189. phandle = <0x141>;
  9190. };
  9191.  
  9192. qcom,msm-pcm-low-latency {
  9193. compatible = "qcom,msm-pcm-dsp";
  9194. qcom,msm-pcm-dsp-id = <0x1>;
  9195. qcom,msm-pcm-low-latency;
  9196. qcom,latency-level = "regular";
  9197. linux,phandle = <0x140>;
  9198. phandle = <0x140>;
  9199. };
  9200.  
  9201. qcom,msm-cpe-lsm {
  9202. compatible = "qcom,msm-cpe-lsm";
  9203. linux,phandle = <0x16a>;
  9204. phandle = <0x16a>;
  9205. };
  9206.  
  9207. qcom,msm-pcm-lpa {
  9208. compatible = "qcom,msm-pcm-lpa";
  9209. linux,phandle = <0x14a>;
  9210. phandle = <0x14a>;
  9211. };
  9212.  
  9213. qcom,msm-compress-dsp {
  9214. compatible = "qcom,msm-compress-dsp";
  9215. linux,phandle = <0x145>;
  9216. phandle = <0x145>;
  9217. };
  9218.  
  9219. qcom,msm-voip-dsp {
  9220. compatible = "qcom,msm-voip-dsp";
  9221. linux,phandle = <0x142>;
  9222. phandle = <0x142>;
  9223. };
  9224.  
  9225. qcom,msm-pcm-voice {
  9226. compatible = "qcom,msm-pcm-voice";
  9227. qcom,destroy-cvd;
  9228. qcom,vote-bms;
  9229. linux,phandle = <0x143>;
  9230. phandle = <0x143>;
  9231. };
  9232.  
  9233. qcom,msm-stub-codec {
  9234. compatible = "qcom,msm-stub-codec";
  9235. linux,phandle = <0x167>;
  9236. phandle = <0x167>;
  9237. };
  9238.  
  9239. qcom,msm-dai-fe {
  9240. compatible = "qcom,msm-dai-fe";
  9241. };
  9242.  
  9243. qcom,msm-pcm-afe {
  9244. compatible = "qcom,msm-pcm-afe";
  9245. linux,phandle = <0x147>;
  9246. phandle = <0x147>;
  9247. };
  9248.  
  9249. qcom,msm-pcm-loopback {
  9250. compatible = "qcom,msm-pcm-loopback";
  9251. linux,phandle = <0x144>;
  9252. phandle = <0x144>;
  9253. };
  9254.  
  9255. qcom,msm-dai-mi2s {
  9256. compatible = "qcom,msm-dai-mi2s";
  9257.  
  9258. qcom,msm-dai-q6-mi2s-prim {
  9259. compatible = "qcom,msm-dai-q6-mi2s";
  9260. qcom,msm-dai-q6-mi2s-dev-id = <0x0>;
  9261. qcom,msm-mi2s-rx-lines = <0x3>;
  9262. qcom,msm-mi2s-tx-lines = <0x0>;
  9263. linux,phandle = <0x14c>;
  9264. phandle = <0x14c>;
  9265. };
  9266.  
  9267. qcom,msm-dai-q6-mi2s-sec {
  9268. compatible = "qcom,msm-dai-q6-mi2s";
  9269. qcom,msm-dai-q6-mi2s-dev-id = <0x1>;
  9270. qcom,msm-mi2s-rx-lines = <0x1>;
  9271. qcom,msm-mi2s-tx-lines = <0x0>;
  9272. linux,phandle = <0x14d>;
  9273. phandle = <0x14d>;
  9274. };
  9275.  
  9276. qcom,msm-dai-q6-mi2s-quat {
  9277. compatible = "qcom,msm-dai-q6-mi2s";
  9278. qcom,msm-dai-q6-mi2s-dev-id = <0x3>;
  9279. qcom,msm-mi2s-rx-lines = <0x1>;
  9280. qcom,msm-mi2s-tx-lines = <0x2>;
  9281. linux,phandle = <0x14f>;
  9282. phandle = <0x14f>;
  9283. };
  9284.  
  9285. qcom,msm-dai-q6-mi2s-tert {
  9286. compatible = "qcom,msm-dai-q6-mi2s";
  9287. qcom,msm-dai-q6-mi2s-dev-id = <0x2>;
  9288. qcom,msm-mi2s-rx-lines = <0x0>;
  9289. qcom,msm-mi2s-tx-lines = <0x3>;
  9290. linux,phandle = <0x14e>;
  9291. phandle = <0x14e>;
  9292. };
  9293.  
  9294. qcom,msm-dai-q6-mi2s-quin {
  9295. compatible = "qcom,msm-dai-q6-mi2s";
  9296. qcom,msm-dai-q6-mi2s-dev-id = <0x5>;
  9297. qcom,msm-mi2s-rx-lines = <0x1>;
  9298. qcom,msm-mi2s-tx-lines = <0x2>;
  9299. linux,phandle = <0x150>;
  9300. phandle = <0x150>;
  9301. };
  9302.  
  9303. qcom,msm-dai-q6-mi2s-senary {
  9304. compatible = "qcom,msm-dai-q6-mi2s";
  9305. qcom,msm-dai-q6-mi2s-dev-id = <0x6>;
  9306. qcom,msm-mi2s-rx-lines = <0x0>;
  9307. qcom,msm-mi2s-tx-lines = <0x3>;
  9308. linux,phandle = <0x151>;
  9309. phandle = <0x151>;
  9310. };
  9311. };
  9312.  
  9313. qcom,msm-lsm-client {
  9314. compatible = "qcom,msm-lsm-client";
  9315. linux,phandle = <0x148>;
  9316. phandle = <0x148>;
  9317. };
  9318.  
  9319. qcom,msm-dai-q6 {
  9320. compatible = "qcom,msm-dai-q6";
  9321.  
  9322. qcom,msm-dai-q6-sb-0-rx {
  9323. compatible = "qcom,msm-dai-q6-dev";
  9324. qcom,msm-dai-q6-dev-id = <0x4000>;
  9325. linux,phandle = <0x152>;
  9326. phandle = <0x152>;
  9327. };
  9328.  
  9329. qcom,msm-dai-q6-sb-0-tx {
  9330. compatible = "qcom,msm-dai-q6-dev";
  9331. qcom,msm-dai-q6-dev-id = <0x4001>;
  9332. linux,phandle = <0x153>;
  9333. phandle = <0x153>;
  9334. };
  9335.  
  9336. qcom,msm-dai-q6-sb-1-rx {
  9337. compatible = "qcom,msm-dai-q6-dev";
  9338. qcom,msm-dai-q6-dev-id = <0x4002>;
  9339. linux,phandle = <0x154>;
  9340. phandle = <0x154>;
  9341. };
  9342.  
  9343. qcom,msm-dai-q6-sb-1-tx {
  9344. compatible = "qcom,msm-dai-q6-dev";
  9345. qcom,msm-dai-q6-dev-id = <0x4003>;
  9346. linux,phandle = <0x155>;
  9347. phandle = <0x155>;
  9348. };
  9349.  
  9350. qcom,msm-dai-q6-sb-2-rx {
  9351. compatible = "qcom,msm-dai-q6-dev";
  9352. qcom,msm-dai-q6-dev-id = <0x4004>;
  9353. linux,phandle = <0x16b>;
  9354. phandle = <0x16b>;
  9355. };
  9356.  
  9357. qcom,msm-dai-q6-sb-2-tx {
  9358. compatible = "qcom,msm-dai-q6-dev";
  9359. qcom,msm-dai-q6-dev-id = <0x4005>;
  9360. linux,phandle = <0x16c>;
  9361. phandle = <0x16c>;
  9362. };
  9363.  
  9364. qcom,msm-dai-q6-sb-3-rx {
  9365. compatible = "qcom,msm-dai-q6-dev";
  9366. qcom,msm-dai-q6-dev-id = <0x4006>;
  9367. linux,phandle = <0x156>;
  9368. phandle = <0x156>;
  9369. };
  9370.  
  9371. qcom,msm-dai-q6-sb-3-tx {
  9372. compatible = "qcom,msm-dai-q6-dev";
  9373. qcom,msm-dai-q6-dev-id = <0x4007>;
  9374. linux,phandle = <0x157>;
  9375. phandle = <0x157>;
  9376. };
  9377.  
  9378. qcom,msm-dai-q6-sb-4-rx {
  9379. compatible = "qcom,msm-dai-q6-dev";
  9380. qcom,msm-dai-q6-dev-id = <0x4008>;
  9381. linux,phandle = <0x158>;
  9382. phandle = <0x158>;
  9383. };
  9384.  
  9385. qcom,msm-dai-q6-sb-4-tx {
  9386. compatible = "qcom,msm-dai-q6-dev";
  9387. qcom,msm-dai-q6-dev-id = <0x4009>;
  9388. linux,phandle = <0x159>;
  9389. phandle = <0x159>;
  9390. };
  9391.  
  9392. qcom,msm-dai-q6-sb-5-tx {
  9393. compatible = "qcom,msm-dai-q6-dev";
  9394. qcom,msm-dai-q6-dev-id = <0x400b>;
  9395. linux,phandle = <0x16d>;
  9396. phandle = <0x16d>;
  9397. };
  9398.  
  9399. qcom,msm-dai-q6-sb-5-rx {
  9400. compatible = "qcom,msm-dai-q6-dev";
  9401. qcom,msm-dai-q6-dev-id = <0x400a>;
  9402. linux,phandle = <0x16e>;
  9403. phandle = <0x16e>;
  9404. };
  9405.  
  9406. qcom,msm-dai-q6-bt-sco-rx {
  9407. compatible = "qcom,msm-dai-q6-dev";
  9408. qcom,msm-dai-q6-dev-id = <0x3000>;
  9409. linux,phandle = <0x15a>;
  9410. phandle = <0x15a>;
  9411. };
  9412.  
  9413. qcom,msm-dai-q6-bt-sco-tx {
  9414. compatible = "qcom,msm-dai-q6-dev";
  9415. qcom,msm-dai-q6-dev-id = <0x3001>;
  9416. linux,phandle = <0x15b>;
  9417. phandle = <0x15b>;
  9418. };
  9419.  
  9420. qcom,msm-dai-q6-int-fm-rx {
  9421. compatible = "qcom,msm-dai-q6-dev";
  9422. qcom,msm-dai-q6-dev-id = <0x3004>;
  9423. linux,phandle = <0x15c>;
  9424. phandle = <0x15c>;
  9425. };
  9426.  
  9427. qcom,msm-dai-q6-int-fm-tx {
  9428. compatible = "qcom,msm-dai-q6-dev";
  9429. qcom,msm-dai-q6-dev-id = <0x3005>;
  9430. linux,phandle = <0x15d>;
  9431. phandle = <0x15d>;
  9432. };
  9433.  
  9434. qcom,msm-dai-q6-be-afe-pcm-rx {
  9435. compatible = "qcom,msm-dai-q6-dev";
  9436. qcom,msm-dai-q6-dev-id = <0xe0>;
  9437. linux,phandle = <0x15e>;
  9438. phandle = <0x15e>;
  9439. };
  9440.  
  9441. qcom,msm-dai-q6-be-afe-pcm-tx {
  9442. compatible = "qcom,msm-dai-q6-dev";
  9443. qcom,msm-dai-q6-dev-id = <0xe1>;
  9444. linux,phandle = <0x15f>;
  9445. phandle = <0x15f>;
  9446. };
  9447.  
  9448. qcom,msm-dai-q6-afe-proxy-rx {
  9449. compatible = "qcom,msm-dai-q6-dev";
  9450. qcom,msm-dai-q6-dev-id = <0xf1>;
  9451. linux,phandle = <0x160>;
  9452. phandle = <0x160>;
  9453. };
  9454.  
  9455. qcom,msm-dai-q6-afe-proxy-tx {
  9456. compatible = "qcom,msm-dai-q6-dev";
  9457. qcom,msm-dai-q6-dev-id = <0xf0>;
  9458. linux,phandle = <0x161>;
  9459. phandle = <0x161>;
  9460. };
  9461.  
  9462. qcom,msm-dai-q6-incall-record-rx {
  9463. compatible = "qcom,msm-dai-q6-dev";
  9464. qcom,msm-dai-q6-dev-id = <0x8003>;
  9465. linux,phandle = <0x162>;
  9466. phandle = <0x162>;
  9467. };
  9468.  
  9469. qcom,msm-dai-q6-incall-record-tx {
  9470. compatible = "qcom,msm-dai-q6-dev";
  9471. qcom,msm-dai-q6-dev-id = <0x8004>;
  9472. linux,phandle = <0x163>;
  9473. phandle = <0x163>;
  9474. };
  9475.  
  9476. qcom,msm-dai-q6-incall-music-rx {
  9477. compatible = "qcom,msm-dai-q6-dev";
  9478. qcom,msm-dai-q6-dev-id = <0x8005>;
  9479. linux,phandle = <0x164>;
  9480. phandle = <0x164>;
  9481. };
  9482.  
  9483. qcom,msm-dai-q6-incall-music-2-rx {
  9484. compatible = "qcom,msm-dai-q6-dev";
  9485. qcom,msm-dai-q6-dev-id = <0x8002>;
  9486. linux,phandle = <0x165>;
  9487. phandle = <0x165>;
  9488. };
  9489. };
  9490.  
  9491. qcom,msm-pcm-hostless {
  9492. compatible = "qcom,msm-pcm-hostless";
  9493. linux,phandle = <0x146>;
  9494. phandle = <0x146>;
  9495. };
  9496.  
  9497. qcom,msm-pri-auxpcm {
  9498. compatible = "qcom,msm-auxpcm-dev";
  9499. qcom,msm-cpudai-auxpcm-mode = <0x0 0x0>;
  9500. qcom,msm-cpudai-auxpcm-sync = <0x1 0x1>;
  9501. qcom,msm-cpudai-auxpcm-frame = <0x5 0x4>;
  9502. qcom,msm-cpudai-auxpcm-quant = <0x2 0x2>;
  9503. qcom,msm-cpudai-auxpcm-num-slots = <0x1 0x1>;
  9504. qcom,msm-cpudai-auxpcm-slot-mapping = <0x1 0x1>;
  9505. qcom,msm-cpudai-auxpcm-data = <0x0 0x0>;
  9506. qcom,msm-cpudai-auxpcm-pcm-clk-rate = <0x1f4000 0x1f4000>;
  9507. qcom,msm-auxpcm-interface = "primary";
  9508. linux,phandle = <0x14b>;
  9509. phandle = <0x14b>;
  9510. };
  9511.  
  9512. qcom,msm-hdmi-dba-codec-rx {
  9513. compatible = "qcom,msm-hdmi-dba-codec-rx";
  9514. qcom,dba-bridge-chip = "adv7533";
  9515. linux,phandle = <0x169>;
  9516. phandle = <0x169>;
  9517. };
  9518.  
  9519. qcom,msm-audio-ion {
  9520. compatible = "qcom,msm-audio-ion";
  9521. qcom,smmu-version = <0x1>;
  9522. qcom,smmu-enabled;
  9523. iommus = <0x133 0x1>;
  9524. };
  9525.  
  9526. qcom,msm-adsp-loader {
  9527. compatible = "qcom,adsp-loader";
  9528. qcom,adsp-state = <0x0>;
  9529. };
  9530.  
  9531. qcom,avtimer@c0a300c {
  9532. compatible = "qcom,avtimer";
  9533. reg = <0xc0a300c 0x4 0xc0a3010 0x4>;
  9534. reg-names = "avtimer_lsb_addr", "avtimer_msb_addr";
  9535. qcom,clk-div = <0x1b>;
  9536. };
  9537.  
  9538. sound {
  9539. compatible = "qcom,msm8952-audio-codec";
  9540. qcom,model = "msm8953-snd-card-mtp";
  9541. reg = <0xc051000 0x4 0xc051004 0x4 0xc055000 0x4 0xc052000 0x4>;
  9542. reg-names = "csr_gp_io_mux_mic_ctl", "csr_gp_io_mux_spkr_ctl", "csr_gp_io_lpaif_pri_pcm_pri_mode_muxsel", "csr_gp_io_mux_quin_ctl";
  9543. qcom,msm-ext-pa = "primary";
  9544. qcom,msm-mclk-freq = <0x927c00>;
  9545. qcom,msm-mbhc-hphl-swh = <0x1>;
  9546. qcom,msm-mbhc-gnd-swh = <0x0>;
  9547. qcom,msm-hs-micbias-type = "internal";
  9548. ext-spk-amp-gpio = <0xbe 0x60 0x0>;
  9549. qcom,msm-micbias1-ext-cap;
  9550. qcom,audio-routing = "RX_BIAS", "MCLK", "SPK_RX_BIAS", "MCLK", "INT_LDO_H", "MCLK", "MIC BIAS External", "Handset Mic", "MIC BIAS Internal2", "Headset Mic", "MIC BIAS External", "Secondary Mic", "AMIC1", "MIC BIAS External", "AMIC2", "MIC BIAS Internal2", "AMIC3", "MIC BIAS External", "WSA_SPK OUT", "VDD_WSA_SWITCH", "SpkrMono WSA_IN", "WSA_SPK OUT";
  9551. qcom,hdmi-dba-codec-rx;
  9552. qcom,msm-gpios = "pri_i2s", "us_eu_gpio", "quin_i2s", "comp_gpio";
  9553. qcom,pinctrl-names = "all_off", "pri_i2s_act", "us_eu_gpio_act", "pri_i2s_us_eu_gpio_act", "quin_act", "quin_pri_i2s_act", "quin_us_eu_gpio_act", "quin_us_eu_gpio_pri_i2s_act", "comp_gpio_act", "comp_gpio_pri_i2s_act", "comp_gpio_us_eu_gpio_act", "comp_gpio_pri_i2s_us_eu_gpio_act", "comp_gpio_quin_act", "comp_gpio_quin_pri_i2s_act", "comp_gpio_quin_us_eu_gpio_act", "comp_gpio_quin_us_eu_gpio_pri_i2s_act";
  9554. pinctrl-names = "all_off", "pri_i2s_act", "us_eu_gpio_act", "pri_i2s_us_eu_gpio_act", "quin_act", "quin_pri_i2s_act", "quin_us_eu_gpio_act", "quin_us_eu_gpio_pri_i2s_act", "comp_gpio_act", "comp_gpio_pri_i2s_act", "comp_gpio_us_eu_gpio_act", "comp_gpio_pri_i2s_us_eu_gpio_act", "comp_gpio_quin_act", "comp_gpio_quin_pri_i2s_act", "comp_gpio_quin_us_eu_gpio_act", "comp_gpio_quin_us_eu_gpio_pri_i2s_act";
  9555. pinctrl-0 = <0x134 0x135 0x136 0x137 0x138 0x139>;
  9556. pinctrl-1 = <0x13a 0x135 0x13b 0x137 0x138 0x139>;
  9557. pinctrl-2 = <0x134 0x135 0x136 0x13c 0x138 0x139>;
  9558. pinctrl-3 = <0x13a 0x135 0x13b 0x13c 0x138 0x139>;
  9559. pinctrl-4 = <0x134 0x135 0x136 0x137 0x13d 0x13e>;
  9560. pinctrl-5 = <0x13a 0x135 0x13b 0x137 0x13d 0x13e>;
  9561. pinctrl-6 = <0x134 0x135 0x136 0x13c 0x13d 0x13e>;
  9562. pinctrl-7 = <0x13a 0x135 0x13b 0x13c 0x13d 0x13e>;
  9563. asoc-platform = <0x13f 0x140 0x141 0x142 0x143 0x144 0x145 0x146 0x147 0x148 0x149 0x14a>;
  9564. asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", "msm-pcm-dsp.2", "msm-voip-dsp", "msm-pcm-voice", "msm-pcm-loopback", "msm-compress-dsp", "msm-pcm-hostless", "msm-pcm-afe", "msm-lsm-client", "msm-pcm-routing", "msm-pcm-lpa";
  9565. asoc-cpu = <0x14b 0x14c 0x14d 0x14e 0x14f 0x150 0x151 0x152 0x153 0x154 0x155 0x156 0x157 0x158 0x159 0x15a 0x15b 0x15c 0x15d 0x15e 0x15f 0x160 0x161 0x162 0x163 0x164 0x165>;
  9566. asoc-cpu-names = "msm-dai-q6-auxpcm.1", "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", "msm-dai-q6-mi2s.5", "msm-dai-q6-mi2s.6", "msm-dai-q6-dev.16384", "msm-dai-q6-dev.16385", "msm-dai-q6-dev.16386", "msm-dai-q6-dev.16387", "msm-dai-q6-dev.16390", "msm-dai-q6-dev.16391", "msm-dai-q6-dev.16392", "msm-dai-q6-dev.16393", "msm-dai-q6-dev.12288", "msm-dai-q6-dev.12289", "msm-dai-q6-dev.12292", "msm-dai-q6-dev.12293", "msm-dai-q6-dev.224", "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773", "msm-dai-q6-dev.32770";
  9567. qcom,cdc-us-euro-gpios = <0xbe 0x3f 0x0>;
  9568. pinctrl-8 = <0x134 0x166 0x136 0x137 0x138 0x139>;
  9569. pinctrl-9 = <0x13a 0x166 0x13b 0x137 0x138 0x139>;
  9570. pinctrl-10 = <0x134 0x166 0x136 0x13c 0x138 0x139>;
  9571. pinctrl-11 = <0x13a 0x166 0x13b 0x13c 0x138 0x139>;
  9572. pinctrl-12 = <0x134 0x166 0x136 0x137 0x13d 0x13e>;
  9573. pinctrl-13 = <0x13a 0x166 0x13b 0x137 0x13d 0x13e>;
  9574. pinctrl-14 = <0x134 0x166 0x136 0x13c 0x13d 0x13e>;
  9575. pinctrl-15 = <0x13a 0x166 0x13b 0x13c 0x13d 0x13e>;
  9576. asoc-codec = <0x167 0x168 0x169>;
  9577. asoc-codec-names = "msm-stub-codec.1", "cajon_codec", "msm-hdmi-dba-codec-rx";
  9578. msm-vdd-wsa-switch-supply = <0xe1>;
  9579. qcom,msm-vdd-wsa-switch-voltage = <0x1b7740>;
  9580. qcom,msm-vdd-wsa-switch-current = <0x2710>;
  9581. status = "okay";
  9582. };
  9583.  
  9584. sound-9335 {
  9585. status = "disabled";
  9586. compatible = "qcom,msm8952-audio-slim-codec";
  9587. qcom,model = "msm8953-tasha-snd-card";
  9588. reg = <0xc051000 0x4 0xc051004 0x4 0xc055000 0x4 0xc052000 0x4>;
  9589. reg-names = "csr_gp_io_mux_mic_ctl", "csr_gp_io_mux_spkr_ctl", "csr_gp_io_lpaif_pri_pcm_pri_mode_muxsel", "csr_gp_io_mux_quin_ctl";
  9590. qcom,audio-routing = "AIF4 VI", "MCLK", "AIF4 VI", "MICBIAS_REGULATOR", "RX_BIAS", "MCLK", "MADINPUT", "MCLK", "AIF4 MAD", "MICBIAS_REGULATOR", "AMIC2", "MIC BIAS2", "MIC BIAS2", "Headset Mic", "AMIC3", "MIC BIAS2", "MIC BIAS2", "ANCRight Headset Mic", "AMIC4", "MIC BIAS2", "MIC BIAS2", "ANCLeft Headset Mic", "AMIC5", "MIC BIAS3", "MIC BIAS3", "Handset Mic", "AMIC6", "MIC BIAS4", "MIC BIAS4", "Analog Mic6", "DMIC0", "MIC BIAS1", "MIC BIAS1", "Digital Mic0", "DMIC1", "MIC BIAS1", "MIC BIAS1", "Digital Mic1", "DMIC2", "MIC BIAS3", "MIC BIAS3", "Digital Mic2", "DMIC3", "MIC BIAS3", "MIC BIAS3", "Digital Mic3", "DMIC4", "MIC BIAS4", "MIC BIAS4", "Digital Mic4", "DMIC5", "MIC BIAS4", "MIC BIAS4", "Digital Mic5", "MIC BIAS1", "MICBIAS_REGULATOR", "MIC BIAS2", "MICBIAS_REGULATOR", "MIC BIAS3", "MICBIAS_REGULATOR", "MIC BIAS4", "MICBIAS_REGULATOR", "SpkrLeft IN", "SPK1 OUT", "SpkrRight IN", "SPK2 OUT";
  9591. qcom,hdmi-dba-codec-rx;
  9592. qcom,msm-gpios = "quin_i2s", "us_eu_gpio";
  9593. qcom,pinctrl-names = "all_off", "quin_act", "us_eu_gpio_act", "quin_us_eu_gpio_act";
  9594. pinctrl-names = "all_off", "quin_act", "us_eu_gpio_act", "quin_us_eu_gpio_act";
  9595. pinctrl-0 = <0x138 0x139 0x137>;
  9596. pinctrl-1 = <0x13d 0x13e 0x137>;
  9597. pinctrl-2 = <0x138 0x139 0x13c>;
  9598. pinctrl-3 = <0x13d 0x13e 0x13c>;
  9599. qcom,msm-mbhc-hphl-swh = <0x0>;
  9600. qcom,msm-mbhc-gnd-swh = <0x0>;
  9601. qcom,tasha-mclk-clk-freq = <0x927c00>;
  9602. asoc-platform = <0x13f 0x140 0x141 0x142 0x143 0x144 0x145 0x146 0x147 0x148 0x149 0x16a 0x14a>;
  9603. asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", "msm-pcm-dsp.2", "msm-voip-dsp", "msm-pcm-voice", "msm-pcm-loopback", "msm-compress-dsp", "msm-pcm-hostless", "msm-pcm-afe", "msm-lsm-client", "msm-pcm-routing", "msm-cpe-lsm", "msm-pcm-lpa";
  9604. asoc-cpu = <0x14b 0x14e 0x14f 0x150 0x152 0x153 0x154 0x155 0x16b 0x16c 0x156 0x157 0x158 0x159 0x16d 0x15e 0x15f 0x160 0x161 0x162 0x163 0x164 0x165 0x16e 0x15a 0x15b 0x15c 0x15d>;
  9605. asoc-cpu-names = "msm-dai-q6-auxpcm.1", "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", "msm-dai-q6-mi2s.5", "msm-dai-q6-dev.16384", "msm-dai-q6-dev.16385", "msm-dai-q6-dev.16386", "msm-dai-q6-dev.16387", "msm-dai-q6-dev.16388", "msm-dai-q6-dev.16389", "msm-dai-q6-dev.16390", "msm-dai-q6-dev.16391", "msm-dai-q6-dev.16392", "msm-dai-q6-dev.16393", "msm-dai-q6-dev.16395", "msm-dai-q6-dev.224", "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773", "msm-dai-q6-dev.32770", "msm-dai-q6-dev.16394", "msm-dai-q6-dev.12288", "msm-dai-q6-dev.12289", "msm-dai-q6-dev.12292", "msm-dai-q6-dev.12293";
  9606. asoc-codec = <0x167 0x169>;
  9607. asoc-codec-names = "msm-stub-codec.1", "msm-hdmi-dba-codec-rx";
  9608. qcom,cdc-us-euro-gpios = <0xbe 0x3f 0x0>;
  9609. qcom,wsa-max-devs = <0x2>;
  9610. qcom,wsa-devs = <0x16f 0x170 0x171 0x172>;
  9611. qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight", "SpkrLeft", "SpkrRight";
  9612. };
  9613.  
  9614. wcd9xxx-irq {
  9615. status = "disabled";
  9616. compatible = "qcom,wcd9xxx-irq";
  9617. interrupt-controller;
  9618. #interrupt-cells = <0x1>;
  9619. interrupt-names = "cdc-int";
  9620. pinctrl-names = "default";
  9621. pinctrl-0 = <0x173>;
  9622. interrupt-parent = <0xbe>;
  9623. interrupts = <0x49 0x0>;
  9624. qcom,gpio-connect = <0xbe 0x49 0x0>;
  9625. linux,phandle = <0xef>;
  9626. phandle = <0xef>;
  9627. };
  9628.  
  9629. wcd_gpio_ctrl {
  9630. status = "disabled";
  9631. compatible = "qcom,wcd-gpio-ctrl";
  9632. pinctrl-names = "aud_active", "aud_sleep";
  9633. pinctrl-0 = <0x174>;
  9634. pinctrl-1 = <0x175>;
  9635. qcom,cdc-rst-n-gpio = <0xbe 0x43 0x0>;
  9636. linux,phandle = <0xf0>;
  9637. phandle = <0xf0>;
  9638. };
  9639.  
  9640. audio_ext_clk {
  9641. status = "disabled";
  9642. compatible = "qcom,audio-ref-clk";
  9643. clock-names = "osr_clk";
  9644. qcom,node_has_rpm_clock;
  9645. #clock-cells = <0x1>;
  9646. qcom,audio-ref-clk-gpio = <0xea 0x1 0x0>;
  9647. qcom,lpass-mclk-id = "pri_mclk";
  9648. clocks = <0x37 0xd454019f>;
  9649. pinctrl-names = "sleep", "active";
  9650. pinctrl-0 = <0x176>;
  9651. pinctrl-1 = <0x177>;
  9652. linux,phandle = <0xf1>;
  9653. phandle = <0xf1>;
  9654. };
  9655.  
  9656. qcom,gdsc@184c018 {
  9657. compatible = "qcom,gdsc";
  9658. regulator-name = "gdsc_venus";
  9659. reg = <0x184c018 0x4>;
  9660. status = "okay";
  9661. clock-names = "bus_clk", "core_clk";
  9662. clocks = <0x37 0xcdf4c8f6 0x37 0xf76a02bb>;
  9663. linux,phandle = <0xb8>;
  9664. phandle = <0xb8>;
  9665. };
  9666.  
  9667. qcom,gdsc@184d078 {
  9668. compatible = "qcom,gdsc";
  9669. regulator-name = "gdsc_mdss";
  9670. reg = <0x184d078 0x4>;
  9671. status = "okay";
  9672. clock-names = "core_clk", "bus_clk";
  9673. clocks = <0x37 0x22f3521f 0x37 0x668f51de>;
  9674. proxy-supply = <0x178>;
  9675. qcom,proxy-consumer-enable;
  9676. linux,phandle = <0x178>;
  9677. phandle = <0x178>;
  9678. };
  9679.  
  9680. qcom,gdsc@185701c {
  9681. compatible = "qcom,gdsc";
  9682. regulator-name = "gdsc_jpeg";
  9683. reg = <0x185701c 0x4>;
  9684. status = "okay";
  9685. clock-names = "core_clk", "bus_clk";
  9686. clocks = <0x37 0x1ed3f032 0x37 0x3e278896>;
  9687. linux,phandle = <0x17d>;
  9688. phandle = <0x17d>;
  9689. };
  9690.  
  9691. qcom,gdsc@1858034 {
  9692. compatible = "qcom,gdsc";
  9693. regulator-name = "gdsc_vfe";
  9694. reg = <0x1858034 0x4>;
  9695. status = "okay";
  9696. clock-names = "core_clk", "bus_clk", "micro_clk", "csi_clk";
  9697. clocks = <0x37 0xaaa3cd97 0x37 0x77fe2384 0x37 0xfbbee8cf 0x37 0xcc73453c>;
  9698. linux,phandle = <0x17a>;
  9699. phandle = <0x17a>;
  9700. };
  9701.  
  9702. qcom,gdsc@185806c {
  9703. compatible = "qcom,gdsc";
  9704. regulator-name = "gdsc_vfe1";
  9705. reg = <0x185806c 0x4>;
  9706. status = "okay";
  9707. clock-names = "core_clk", "bus_clk", "micro_clk", "csi_clk";
  9708. clocks = <0x37 0xcaf20d99 0x37 0xaf7463b3 0x37 0xfbbee8cf 0x37 0xb1ef6e8b>;
  9709. linux,phandle = <0x17b>;
  9710. phandle = <0x17b>;
  9711. };
  9712.  
  9713. qcom,gdsc@1858078 {
  9714. compatible = "qcom,gdsc";
  9715. regulator-name = "gdsc_cpp";
  9716. reg = <0x1858078 0x4>;
  9717. status = "okay";
  9718. clock-names = "core_clk", "bus_clk";
  9719. clocks = <0x37 0x7118a0de 0x37 0xbbf73861>;
  9720. linux,phandle = <0x17e>;
  9721. phandle = <0x17e>;
  9722. };
  9723.  
  9724. qcom,gdsc@185901c {
  9725. compatible = "qcom,gdsc";
  9726. regulator-name = "gdsc_oxili_gx";
  9727. reg = <0x185901c 0x4>;
  9728. status = "okay";
  9729. clock-names = "core_root_clk";
  9730. clocks = <0x38 0x917f76ef>;
  9731. qcom,force-enable-root-clk;
  9732. parent-supply = <0xc8>;
  9733. linux,phandle = <0x3b>;
  9734. phandle = <0x3b>;
  9735. };
  9736.  
  9737. qcom,gdsc@184c028 {
  9738. compatible = "qcom,gdsc";
  9739. regulator-name = "gdsc_venus_core0";
  9740. reg = <0x184c028 0x4>;
  9741. status = "okay";
  9742. qcom,support-hw-trigger;
  9743. clock-names = "core0_clk";
  9744. clocks = <0x37 0x83a7f549>;
  9745. linux,phandle = <0xb9>;
  9746. phandle = <0xb9>;
  9747. };
  9748.  
  9749. qcom,gdsc@184c030 {
  9750. compatible = "qcom,gdsc";
  9751. regulator-name = "gdsc_venus_core1";
  9752. reg = <0x184c030 0x4>;
  9753. status = "disabled";
  9754. };
  9755.  
  9756. qcom,gdsc@185904c {
  9757. compatible = "qcom,gdsc";
  9758. regulator-name = "gdsc_oxili_cx";
  9759. reg = <0x185904c 0x4>;
  9760. status = "okay";
  9761. clock-names = "core_clk";
  9762. clocks = <0x38 0x49a51fd9>;
  9763. linux,phandle = <0x3a>;
  9764. phandle = <0x3a>;
  9765. };
  9766.  
  9767. qcom,gdsc@183f078 {
  9768. compatible = "qcom,gdsc";
  9769. regulator-name = "gdsc_usb30";
  9770. reg = <0x183f078 0x4>;
  9771. status = "okay";
  9772. linux,phandle = <0x128>;
  9773. phandle = <0x128>;
  9774. };
  9775.  
  9776. qcom,msm-cam@1b00000 {
  9777. compatible = "qcom,msm-cam";
  9778. reg = <0x1b00000 0x40000>;
  9779. reg-names = "msm-cam";
  9780. status = "ok";
  9781. bus-vectors = "suspend", "svs", "nominal", "turbo";
  9782. qcom,bus-votes = <0x0 0x1312d000 0x2625a000 0x2625a000>;
  9783. };
  9784.  
  9785. qcom,csiphy@1b34000 {
  9786. status = "ok";
  9787. cell-index = <0x0>;
  9788. compatible = "qcom,csiphy-v3.5", "qcom,csiphy";
  9789. reg = <0x1b34000 0x1000 0x1b00030 0x4>;
  9790. reg-names = "csiphy", "csiphy_clk_mux";
  9791. interrupts = <0x0 0x4e 0x0>;
  9792. interrupt-names = "csiphy";
  9793. clocks = <0x37 0x4e814a78 0x37 0x3c0a858f 0x37 0xc8a309be 0x37 0xf8897589 0x37 0xf92304fb 0x37 0x6a41ff7 0x37 0x9894b414>;
  9794. clock-names = "camss_top_ahb_clk", "ispif_ahb_clk", "csiphy_timer_src_clk", "csiphy_timer_clk", "camss_ahb_src", "csi_phy_clk", "camss_ahb_clk";
  9795. qcom,clock-rates = <0x0 0x3ab06a0 0xbebc200 0x0 0x0 0x0 0x0>;
  9796. };
  9797.  
  9798. qcom,csiphy@1b35000 {
  9799. status = "ok";
  9800. cell-index = <0x1>;
  9801. compatible = "qcom,csiphy-v3.5", "qcom,csiphy";
  9802. reg = <0x1b35000 0x1000 0x1b00038 0x4>;
  9803. reg-names = "csiphy", "csiphy_clk_mux";
  9804. interrupts = <0x0 0x4f 0x0>;
  9805. interrupt-names = "csiphy";
  9806. clocks = <0x37 0x4e814a78 0x37 0x3c0a858f 0x37 0x7c0fe23a 0x37 0x4d26438f 0x37 0xf92304fb 0x37 0xfd1d1fa 0x37 0x9894b414>;
  9807. clock-names = "camss_top_ahb_clk", "ispif_ahb_clk", "csiphy_timer_src_clk", "csiphy_timer_clk", "camss_ahb_src", "csi_phy_clk", "camss_ahb_clk";
  9808. qcom,clock-rates = <0x0 0x3ab06a0 0xbebc200 0x0 0x0 0x0 0x0>;
  9809. };
  9810.  
  9811. qcom,csiphy@1b36000 {
  9812. status = "ok";
  9813. cell-index = <0x2>;
  9814. compatible = "qcom,csiphy-v3.5", "qcom,csiphy";
  9815. reg = <0x1b36000 0x1000 0x1b00040 0x4>;
  9816. reg-names = "csiphy", "csiphy_clk_mux";
  9817. interrupts = <0x0 0x13b 0x0>;
  9818. interrupt-names = "csiphy";
  9819. clocks = <0x37 0x4e814a78 0x37 0x3c0a858f 0x37 0x62ffea9c 0x37 0xe768898c 0x37 0xf92304fb 0x37 0xbeeffbcd 0x37 0x9894b414>;
  9820. clock-names = "camss_top_ahb_clk", "ispif_ahb_clk", "csiphy_timer_src_clk", "csiphy_timer_clk", "camss_ahb_src", "csi_phy_clk", "camss_ahb_clk";
  9821. qcom,clock-rates = <0x0 0x3ab06a0 0xbebc200 0x0 0x0 0x0 0x0>;
  9822. };
  9823.  
  9824. qcom,csid@1b30000 {
  9825. status = "ok";
  9826. cell-index = <0x0>;
  9827. compatible = "qcom,csid-v3.5.1", "qcom,csid";
  9828. reg = <0x1b30000 0x400>;
  9829. reg-names = "csid";
  9830. interrupts = <0x0 0x33 0x0>;
  9831. interrupt-names = "csid";
  9832. qcom,csi-vdd-voltage = <0x12b128>;
  9833. qcom,mipi-csi-vdd-supply = <0x179>;
  9834. clocks = <0x37 0x4e814a78 0x37 0x3c0a858f 0x37 0x175d672a 0x37 0x227e65bc 0x37 0x6b01b3e1 0x37 0x61a8a930 0x37 0x7053c7ae 0x37 0x9894b414>;
  9835. clock-names = "camss_top_ahb_clk", "ispif_ahb_clk", "csi_ahb_clk", "csi_src_clk", "csi_clk", "csi_pix_clk", "csi_rdi_clk", "camss_ahb_clk";
  9836. qcom,clock-rates = <0x0 0x3ab06a0 0x0 0xbebc200 0x0 0x0 0x0 0x0>;
  9837. };
  9838.  
  9839. qcom,csid@1b30400 {
  9840. status = "ok";
  9841. cell-index = <0x1>;
  9842. compatible = "qcom,csid-v3.5.1", "qcom,csid";
  9843. reg = <0x1b30400 0x400>;
  9844. reg-names = "csid";
  9845. interrupts = <0x0 0x34 0x0>;
  9846. interrupt-names = "csid";
  9847. qcom,csi-vdd-voltage = <0x12b128>;
  9848. qcom,mipi-csi-vdd-supply = <0x179>;
  9849. clocks = <0x37 0x4e814a78 0x37 0x3c0a858f 0x37 0x2c2dc261 0x37 0x6a2a6c36 0x37 0x1aba4a8c 0x37 0x87fc98d8 0x37 0x6ac996fe 0x37 0x9894b414>;
  9850. clock-names = "camss_top_ahb_clk", "ispif_ahb_clk", "csi_ahb_clk", "csi_src_clk", "csi_clk", "csi_pix_clk", "csi_rdi_clk", "camss_ahb_clk";
  9851. qcom,clock-rates = <0x0 0x3ab06a0 0x0 0xbebc200 0x0 0x0 0x0 0x0>;
  9852. };
  9853.  
  9854. qcom,csid@1b30800 {
  9855. status = "ok";
  9856. cell-index = <0x2>;
  9857. compatible = "qcom,csid-v3.5.1", "qcom,csid";
  9858. reg = <0x1b30800 0x400>;
  9859. reg-names = "csid";
  9860. interrupts = <0x0 0x99 0x0>;
  9861. interrupt-names = "csid";
  9862. qcom,csi-vdd-voltage = <0x12b128>;
  9863. qcom,mipi-csi-vdd-supply = <0x179>;
  9864. clocks = <0x37 0x4e814a78 0x37 0x3c0a858f 0x37 0xf3f25940 0x37 0x4113589f 0x37 0xb6857fa2 0x37 0xa619561a 0x37 0x19fd3f1 0x37 0x9894b414>;
  9865. clock-names = "camss_top_ahb_clk", "ispif_ahb_clk", "csi_ahb_clk", "csi_src_clk", "csi_clk", "csi_pix_clk", "csi_rdi_clk", "camss_ahb_clk";
  9866. qcom,clock-rates = <0x0 0x3ab06a0 0x0 0xbebc200 0x0 0x0 0x0 0x0>;
  9867. };
  9868.  
  9869. qcom,ispif@1b31000 {
  9870. cell-index = <0x0>;
  9871. compatible = "qcom,ispif-v3.0", "qcom,ispif";
  9872. reg = <0x1b31000 0x500 0x1b00020 0x10>;
  9873. reg-names = "ispif", "csi_clk_mux";
  9874. interrupts = <0x0 0x37 0x0>;
  9875. interrupt-names = "ispif";
  9876. qcom,num-isps = <0x2>;
  9877. vfe0-vdd-supply = <0x17a>;
  9878. vfe1-vdd-supply = <0x17b>;
  9879. qcom,vdd-names = "vfe0-vdd", "vfe1-vdd";
  9880. clocks = <0x37 0x3c0a858f 0x37 0x9894b414 0x37 0x4e814a78 0x37 0xf92304fb 0x37 0x227e65bc 0x37 0x6b01b3e1 0x37 0x7053c7ae 0x37 0x61a8a930 0x37 0x6a2a6c36 0x37 0x1aba4a8c 0x37 0x6ac996fe 0x37 0x87fc98d8 0x37 0x4113589f 0x37 0xb6857fa2 0x37 0x19fd3f1 0x37 0xa619561a 0x37 0xa0c2bd8f 0x37 0xaaa3cd97 0x37 0xcc73453c 0x37 0x4e357366 0x37 0xcaf20d99 0x37 0xb1ef6e8b>;
  9881. clock-names = "ispif_ahb_clk", "camss_ahb_clk", "camss_top_ahb_clk", "camss_ahb_src", "csi0_src_clk", "csi0_clk", "csi0_rdi_clk", "csi0_pix_clk", "csi1_src_clk", "csi1_clk", "csi1_rdi_clk", "csi1_pix_clk", "csi2_src_clk", "csi2_clk", "csi2_rdi_clk", "csi2_pix_clk", "vfe0_clk_src", "camss_vfe_vfe0_clk", "camss_csi_vfe0_clk", "vfe1_clk_src", "camss_vfe_vfe1_clk", "camss_csi_vfe1_clk";
  9882. qcom,clock-rates = <0x3ab06a0 0x0 0x0 0x0 0xbebc200 0x0 0x0 0x0 0xbebc200 0x0 0x0 0x0 0xbebc200 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
  9883. qcom,clock-control = "SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "INIT_RATE", "NO_SET_RATE", "NO_SET_RATE", "INIT_RATE", "NO_SET_RATE", "NO_SET_RATE";
  9884. };
  9885.  
  9886. qcom,vfe0@1b10000 {
  9887. cell-index = <0x0>;
  9888. compatible = "qcom,vfe40";
  9889. reg = <0x1b10000 0x1000 0x1b40000 0x200>;
  9890. reg-names = "vfe", "vfe_vbif";
  9891. interrupts = <0x0 0x39 0x0>;
  9892. interrupt-names = "vfe";
  9893. vdd-supply = <0x17a>;
  9894. clocks = <0x37 0x4e814a78 0x37 0x9894b414 0x37 0xa0c2bd8f 0x37 0xaaa3cd97 0x37 0xcc73453c 0x37 0x4050f47a 0x37 0x77fe2384 0x37 0x3c0a858f>;
  9895. clock-names = "camss_top_ahb_clk", "camss_ahb_clk", "vfe_clk_src", "camss_vfe_vfe_clk", "camss_csi_vfe_clk", "iface_clk", "bus_clk", "iface_ahb_clk";
  9896. qcom,clock-rates = <0x0 0x0 0xfe50fb0 0x0 0x0 0x0 0x0 0x0>;
  9897. qos-entries = <0x8>;
  9898. qos-regs = <0x2c4 0x2c8 0x2cc 0x2d0 0x2d4 0x2d8 0x2dc 0x2e0>;
  9899. qos-settings = <0xaa55aa55 0xaa55aa55 0xaa55aa55 0xaa55aa55 0xaa55aa55 0xaa55aa55 0xaa55aa55 0xaa55aa55>;
  9900. vbif-entries = <0x1>;
  9901. vbif-regs = <0x124>;
  9902. vbif-settings = <0x3>;
  9903. ds-entries = <0x11>;
  9904. ds-regs = <0x988 0x98c 0x990 0x994 0x998 0x99c 0x9a0 0x9a4 0x9a8 0x9ac 0x9b0 0x9b4 0x9b8 0x9bc 0x9c0 0x9c4 0x9c8>;
  9905. ds-settings = <0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0x110>;
  9906. max-clk-nominal = <0x1312d000>;
  9907. max-clk-turbo = <0x1bb75640>;
  9908. };
  9909.  
  9910. qcom,vfe1@1b14000 {
  9911. cell-index = <0x1>;
  9912. compatible = "qcom,vfe40";
  9913. reg = <0x1b14000 0x1000 0x1ba0000 0x200>;
  9914. reg-names = "vfe", "vfe_vbif";
  9915. interrupts = <0x0 0x1d 0x0>;
  9916. interrupt-names = "vfe";
  9917. vdd-supply = <0x17b>;
  9918. clocks = <0x37 0x4e814a78 0x37 0x9894b414 0x37 0x4e357366 0x37 0xcaf20d99 0x37 0xb1ef6e8b 0x37 0x634a738a 0x37 0xaf7463b3 0x37 0x3c0a858f>;
  9919. clock-names = "camss_top_ahb_clk", "camss_ahb_clk", "vfe_clk_src", "camss_vfe_vfe_clk", "camss_csi_vfe_clk", "iface_clk", "bus_clk", "iface_ahb_clk";
  9920. qcom,clock-rates = <0x0 0x0 0xfe50fb0 0x0 0x0 0x0 0x0 0x0>;
  9921. qos-entries = <0x8>;
  9922. qos-regs = <0x2c4 0x2c8 0x2cc 0x2d0 0x2d4 0x2d8 0x2dc 0x2e0>;
  9923. qos-settings = <0xaa55aa55 0xaa55aa55 0xaa55aa55 0xaa55aa55 0xaa55aa55 0xaa55aa55 0xaa55aa55 0xaa55aa55>;
  9924. vbif-entries = <0x1>;
  9925. vbif-regs = <0x124>;
  9926. vbif-settings = <0x3>;
  9927. ds-entries = <0x11>;
  9928. ds-regs = <0x988 0x98c 0x990 0x994 0x998 0x99c 0x9a0 0x9a4 0x9a8 0x9ac 0x9b0 0x9b4 0x9b8 0x9bc 0x9c0 0x9c4 0x9c8>;
  9929. ds-settings = <0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0x110>;
  9930. max-clk-nominal = <0x1312d000>;
  9931. max-clk-turbo = <0x1bb75640>;
  9932. };
  9933.  
  9934. qcom,vfe {
  9935. compatible = "qcom,vfe";
  9936. num_child = <0x2>;
  9937. };
  9938.  
  9939. qcom,cam_smmu {
  9940. status = "ok";
  9941. compatible = "qcom,msm-cam-smmu";
  9942.  
  9943. msm_cam_smmu_cb1 {
  9944. compatible = "qcom,qsmmu-cam-cb";
  9945. iommus = <0x17c 0x400 0x17c 0x2800>;
  9946. label = "vfe";
  9947. qcom,scratch-buf-support;
  9948. };
  9949.  
  9950. msm_cam_smmu_cb3 {
  9951. compatible = "qcom,qsmmu-cam-cb";
  9952. iommus = <0x17c 0x1c00>;
  9953. label = "cpp";
  9954. };
  9955.  
  9956. msm_cam_smmu_cb4 {
  9957. compatible = "qcom,qsmmu-cam-cb";
  9958. iommus = <0x17c 0x1800>;
  9959. label = "jpeg_enc0";
  9960. };
  9961. };
  9962.  
  9963. qcom,jpeg@1b1c000 {
  9964. status = "ok";
  9965. cell-index = <0x0>;
  9966. compatible = "qcom,jpeg";
  9967. reg = <0x1b1c000 0x400 0x1b60000 0xc30>;
  9968. reg-names = "jpeg_hw", "jpeg_vbif";
  9969. interrupts = <0x0 0x3b 0x0>;
  9970. interrupt-names = "jpeg";
  9971. vdd-supply = <0x17d>;
  9972. qcom,vdd-names = "vdd";
  9973. clock-names = "core_clk", "iface_clk", "bus_clk0", "camss_top_ahb_clk", "camss_ahb_clk";
  9974. clocks = <0x37 0x1ed3f032 0x37 0x3bfa7603 0x37 0x3e278896 0x37 0x4e814a78 0x37 0x9894b414>;
  9975. qcom,clock-rates = <0xfe50fb0 0x0 0x0 0x0 0x0>;
  9976. qcom,qos-reg-settings = <0x28 0x555e 0xc8 0x5555>;
  9977. qcom,vbif-reg-settings = <0xc0 0x10101000 0xb0 0x10100010>;
  9978. qcom,msm-bus,name = "msm_camera_jpeg0";
  9979. qcom,msm-bus,num-cases = <0x2>;
  9980. qcom,msm-bus,num-paths = <0x1>;
  9981. qcom,msm-bus,vectors-KBps = <0x3e 0x200 0x0 0x0 0x3e 0x200 0xc3500 0xc3500>;
  9982. };
  9983.  
  9984. qcom,irqrouter@1b00000 {
  9985. status = "ok";
  9986. cell-index = <0x0>;
  9987. compatible = "qcom,irqrouter";
  9988. reg = <0x1b00000 0x100>;
  9989. reg-names = "irqrouter";
  9990. };
  9991.  
  9992. qcom,cpp@1b04000 {
  9993. status = "ok";
  9994. cell-index = <0x0>;
  9995. compatible = "qcom,cpp";
  9996. reg = <0x1b04000 0x100 0x1b80000 0x200 0x1b18000 0x18 0x1858078 0x4>;
  9997. reg-names = "cpp", "cpp_vbif", "cpp_hw", "camss_cpp";
  9998. interrupts = <0x0 0x31 0x0>;
  9999. interrupt-names = "cpp";
  10000. vdd-supply = <0x17e>;
  10001. qcom,vdd-names = "vdd";
  10002. clocks = <0x37 0x4e814a78 0x37 0x8382f56d 0x37 0x4ac95e14 0x37 0xbbf73861 0x37 0x7118a0de 0x37 0xfbbee8cf 0x37 0x9894b414>;
  10003. clock-names = "camss_top_ahb_clk", "cpp_core_clk", "camss_vfe_cpp_ahb_clk", "camss_vfe_cpp_axi_clk", "camss_vfe_cpp_clk", "micro_iface_clk", "camss_ahb_clk";
  10004. qcom,clock-rates = <0x0 0xaba9500 0x0 0x0 0xaba9500 0x0 0x0>;
  10005. qcom,min-clock-rate = <0x5f5e100>;
  10006. qcom,bus-master = <0x1>;
  10007. qcom,msm-bus,name = "msm_camera_cpp";
  10008. qcom,msm-bus,num-cases = <0x2>;
  10009. qcom,msm-bus,num-paths = <0x1>;
  10010. qcom,msm-bus,vectors-KBps = <0x6a 0x200 0x0 0x0 0x6a 0x200 0x0 0x0>;
  10011. qcom,msm-bus-vector-dyn-vote;
  10012.  
  10013. qcom,cpp-fw-payload-info {
  10014. qcom,stripe-base = <0x9c>;
  10015. qcom,plane-base = <0x8d>;
  10016. qcom,stripe-size = <0x1b>;
  10017. qcom,plane-size = <0x5>;
  10018. qcom,fe-ptr-off = <0x5>;
  10019. qcom,we-ptr-off = <0xb>;
  10020. };
  10021. };
  10022.  
  10023. qcom,cci@1b0c000 {
  10024. status = "ok";
  10025. cell-index = <0x0>;
  10026. compatible = "qcom,cci";
  10027. reg = <0x1b0c000 0x4000>;
  10028. #address-cells = <0x1>;
  10029. #size-cells = <0x0>;
  10030. reg-names = "cci";
  10031. interrupts = <0x0 0x32 0x0>;
  10032. interrupt-names = "cci";
  10033. clocks = <0x37 0x3c0a858f 0x37 0x822f3d97 0x37 0xa81c11ba 0x37 0xb7dd8824 0x37 0x9894b414 0x37 0x4e814a78>;
  10034. clock-names = "ispif_ahb_clk", "cci_src_clk", "cci_ahb_clk", "camss_cci_clk", "camss_ahb_clk", "camss_top_ahb_clk";
  10035. qcom,clock-rates = <0x3ab06a0 0x124f800 0x0 0x0 0x0 0x0 0x3ab06a0 0x23c3460 0x0 0x0 0x0 0x0>;
  10036. pinctrl-names = "cci_default", "cci_suspend";
  10037. pinctrl-0 = <0x17f 0x180>;
  10038. pinctrl-1 = <0x181 0x182>;
  10039. gpios = <0xbe 0x1d 0x0 0xbe 0x1e 0x0 0xbe 0x1f 0x0 0xbe 0x20 0x0>;
  10040. qcom,gpio-tbl-num = <0x0 0x1 0x2 0x3>;
  10041. qcom,gpio-tbl-flags = <0x1 0x1 0x1 0x1>;
  10042. qcom,gpio-tbl-label = "CCI_I2C_DATA0", "CCI_I2C_CLK0", "CCI_I2C_DATA1", "CCI_I2C_CLK1";
  10043.  
  10044. qcom,i2c_standard_mode {
  10045. status = "disabled";
  10046. qcom,hw-thigh = <0x4e>;
  10047. qcom,hw-tlow = <0x72>;
  10048. qcom,hw-tsu-sto = <0x1c>;
  10049. qcom,hw-tsu-sta = <0x1c>;
  10050. qcom,hw-thd-dat = <0xa>;
  10051. qcom,hw-thd-sta = <0x4d>;
  10052. qcom,hw-tbuf = <0x76>;
  10053. qcom,hw-scl-stretch-en = <0x0>;
  10054. qcom,hw-trdhld = <0x6>;
  10055. qcom,hw-tsp = <0x1>;
  10056. };
  10057.  
  10058. qcom,i2c_fast_mode {
  10059. status = "ok";
  10060. qcom,hw-thigh = <0x14>;
  10061. qcom,hw-tlow = <0x1c>;
  10062. qcom,hw-tsu-sto = <0x15>;
  10063. qcom,hw-tsu-sta = <0x15>;
  10064. qcom,hw-thd-dat = <0xd>;
  10065. qcom,hw-thd-sta = <0x12>;
  10066. qcom,hw-tbuf = <0x20>;
  10067. qcom,hw-scl-stretch-en = <0x0>;
  10068. qcom,hw-trdhld = <0x6>;
  10069. qcom,hw-tsp = <0x3>;
  10070. };
  10071.  
  10072. qcom,i2c_custom_mode {
  10073. status = "ok";
  10074. qcom,hw-thigh = <0xf>;
  10075. qcom,hw-tlow = <0x1c>;
  10076. qcom,hw-tsu-sto = <0x15>;
  10077. qcom,hw-tsu-sta = <0x15>;
  10078. qcom,hw-thd-dat = <0xd>;
  10079. qcom,hw-thd-sta = <0x12>;
  10080. qcom,hw-tbuf = <0x19>;
  10081. qcom,hw-scl-stretch-en = <0x1>;
  10082. qcom,hw-trdhld = <0x6>;
  10083. qcom,hw-tsp = <0x3>;
  10084. };
  10085.  
  10086. qcom,i2c_fast_plus_mode {
  10087. status = "ok";
  10088. qcom,hw-thigh = <0x10>;
  10089. qcom,hw-tlow = <0x16>;
  10090. qcom,hw-tsu-sto = <0x11>;
  10091. qcom,hw-tsu-sta = <0x12>;
  10092. qcom,hw-thd-dat = <0x10>;
  10093. qcom,hw-thd-sta = <0xf>;
  10094. qcom,hw-tbuf = <0x13>;
  10095. qcom,hw-scl-stretch-en = <0x1>;
  10096. qcom,hw-trdhld = <0x3>;
  10097. qcom,hw-tsp = <0x3>;
  10098. qcom,cci-clk-src = <0x23c3460>;
  10099. };
  10100.  
  10101. qcom,actuator@0 {
  10102. cell-index = <0x0>;
  10103. reg = <0x0>;
  10104. compatible = "qcom,actuator";
  10105. qcom,cci-master = <0x0>;
  10106. cam_vaf-supply = <0x183>;
  10107. qcom,cam-vreg-name = "cam_vaf";
  10108. qcom,cam-vreg-min-voltage = <0x2b7cd0>;
  10109. qcom,cam-vreg-max-voltage = <0x2b7cd0>;
  10110. qcom,cam-vreg-op-mode = <0x13880>;
  10111. linux,phandle = <0x191>;
  10112. phandle = <0x191>;
  10113. };
  10114.  
  10115. qcom,eeprom@0 {
  10116. cell-index = <0x0>;
  10117. reg = <0x0>;
  10118. qcom,eeprom-name = "s5k3l8";
  10119. compatible = "qcom,eeprom";
  10120. qcom,slave-addr = <0xa0>;
  10121. qcom,cci-master = <0x0>;
  10122. qcom,num-blocks = <0x1>;
  10123. qcom,page0 = <0x0 0x0 0x2 0x1 0x1 0x1>;
  10124. qcom,poll0 = <0x0 0x0 0x2 0x0 0x1 0x1>;
  10125. qcom,mem0 = <0x86f 0x0 0x2 0x0 0x1 0x0>;
  10126. cam_vdig-supply = <0x184>;
  10127. cam_vio-supply = <0x185>;
  10128. cam_vana-supply = <0x186>;
  10129. cam_vaf-supply = <0x183>;
  10130. qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana", "cam_vaf";
  10131. qcom,cam-vreg-min-voltage = <0x124f80 0x1b7740 0x2ab980 0x2b7cd0>;
  10132. qcom,cam-vreg-max-voltage = <0x124f80 0x1b7740 0x2ab980 0x2b7cd0>;
  10133. qcom,cam-vreg-op-mode = <0x30d40 0x13880 0x13880 0x186a0>;
  10134. pinctrl-names = "cam_default", "cam_suspend";
  10135. pinctrl-0 = <0x187 0x188>;
  10136. pinctrl-1 = <0x189 0x18a>;
  10137. gpios = <0xbe 0x1a 0x0 0xbe 0x28 0x0 0xbe 0x27 0x0>;
  10138. qcom,gpio-reset = <0x1>;
  10139. qcom,gpio-standby = <0x2>;
  10140. qcom,gpio-req-tbl-num = <0x0 0x1 0x2>;
  10141. qcom,gpio-req-tbl-flags = <0x1 0x0 0x0>;
  10142. qcom,gpio-req-tbl-label = "CAMIF_MCLK0", "CAM_RESET0", "CAM_STANDBY0";
  10143. qcom,cam-power-seq-type = "sensor_vreg", "sensor_vreg", "sensor_vreg", "sensor_clk", "sensor_gpio", "sensor_gpio";
  10144. qcom,cam-power-seq-val = "cam_vio", "cam_vana", "cam_vdig", "sensor_cam_mclk", "sensor_gpio_reset", "sensor_gpio_standby";
  10145. qcom,cam-power-seq-cfg-val = <0x1 0x1 0x1 0x16e3600 0x1 0x1>;
  10146. qcom,cam-power-seq-delay = <0x1 0x1 0x5 0x5 0x5 0xa>;
  10147. status = "ok";
  10148. clocks = <0x37 0x266b3853 0x37 0x80902deb>;
  10149. clock-names = "cam_src_clk", "cam_clk";
  10150. qcom,clock-rates = <0x124f800 0x0>;
  10151. linux,phandle = <0x190>;
  10152. phandle = <0x190>;
  10153. };
  10154.  
  10155. qcom,eeprom@3 {
  10156. cell-index = <0x3>;
  10157. reg = <0x3>;
  10158. qcom,eeprom-name = "ov5670";
  10159. compatible = "qcom,eeprom";
  10160. qcom,slave-addr = <0x6c>;
  10161. qcom,cci-master = <0x1>;
  10162. qcom,num-blocks = <0x4>;
  10163. qcom,page0 = <0x1 0x3d88 0x2 0x1b62 0x2 0x1>;
  10164. qcom,poll0 = <0x1 0x3d88 0x2 0x1b62 0x2 0x1>;
  10165. qcom,mem0 = <0x0 0x0 0x2 0x0 0x1 0x0>;
  10166. qcom,page1 = <0x1 0x3d8a 0x2 0x710f 0x2 0x1>;
  10167. qcom,poll1 = <0x1 0x3d8a 0x2 0x710f 0x2 0x1>;
  10168. qcom,mem1 = <0x0 0x3d00 0x2 0x0 0x1 0x0>;
  10169. qcom,page2 = <0x1 0x3d85 0x2 0x6 0x1 0x1>;
  10170. qcom,poll2 = <0x1 0x3d85 0x2 0x6 0x1 0x1>;
  10171. qcom,mem2 = <0x0 0x3d00 0x2 0x0 0x1 0x0>;
  10172. qcom,page3 = <0x1 0x100 0x2 0x1 0x1 0x1>;
  10173. qcom,pageen3 = <0x0 0x3d85 0x2 0x16 0x1 0x0>;
  10174. qcom,poll3 = <0x0 0x3d85 0x2 0x16 0x1 0x0>;
  10175. qcom,mem3 = <0x1e 0x7010 0x2 0x0 0x1 0x1>;
  10176. cam_vdig-supply = <0x18b>;
  10177. cam_vana-supply = <0x186>;
  10178. cam_vio-supply = <0x185>;
  10179. qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana";
  10180. qcom,cam-vreg-min-voltage = <0x124f80 0x1b7740 0x2ab980>;
  10181. qcom,cam-vreg-max-voltage = <0x124f80 0x1b7740 0x2ab980>;
  10182. qcom,cam-vreg-op-mode = <0x19a28 0x0 0x13880>;
  10183. qcom,gpio-no-mux = <0x0>;
  10184. pinctrl-names = "cam_default", "cam_suspend";
  10185. pinctrl-0 = <0x18c 0x18d>;
  10186. pinctrl-1 = <0x18e 0x18f>;
  10187. gpios = <0xbe 0x1b 0x0 0xbe 0x81 0x0 0xbe 0x82 0x0>;
  10188. qcom,gpio-reset = <0x1>;
  10189. qcom,gpio-standby = <0x2>;
  10190. qcom,gpio-req-tbl-num = <0x0 0x1 0x2>;
  10191. qcom,gpio-req-tbl-flags = <0x1 0x0 0x0>;
  10192. qcom,gpio-req-tbl-label = "CAMIF_MCLK2", "CAM_RESET2", "CAM_STANDBY2";
  10193. qcom,cam-power-seq-type = "sensor_vreg", "sensor_vreg", "sensor_vreg", "sensor_gpio", "sensor_gpio", "sensor_clk";
  10194. qcom,cam-power-seq-val = "cam_vdig", "cam_vana", "cam_vio", "sensor_gpio_reset", "sensor_gpio_standby", "sensor_cam_mclk";
  10195. qcom,cam-power-seq-cfg-val = <0x1 0x1 0x1 0x1 0x1 0x16e3600>;
  10196. qcom,cam-power-seq-delay = <0x1 0x1 0x1 0x5 0x5 0xa>;
  10197. status = "ok";
  10198. clocks = <0x37 0xa73cad0c 0x37 0x5002d85f>;
  10199. clock-names = "cam_src_clk", "cam_clk";
  10200. qcom,clock-rates = <0x124f800 0x0>;
  10201. linux,phandle = <0x193>;
  10202. phandle = <0x193>;
  10203. };
  10204.  
  10205. qcom,eeprom@4 {
  10206. cell-index = <0x4>;
  10207. reg = <0x4>;
  10208. qcom,eeprom-name = "s5k5e8";
  10209. compatible = "qcom,eeprom";
  10210. qcom,slave-addr = <0x20>;
  10211. qcom,cci-master = <0x1>;
  10212. qcom,num-blocks = <0x5>;
  10213. qcom,page0 = <0x1 0xa00 0x2 0x4 0x1 0x1>;
  10214. qcom,poll0 = <0x0 0xa00 0x2 0x4 0x1 0x1>;
  10215. qcom,mem0 = <0x0 0x0 0x2 0x0 0x1 0x0>;
  10216. qcom,page1 = <0x1 0xa02 0x2 0x4 0x1 0x1>;
  10217. qcom,poll1 = <0x0 0xa02 0x2 0x4 0x2 0x1>;
  10218. qcom,mem1 = <0x0 0x0 0x2 0x0 0x1 0x0>;
  10219. qcom,page2 = <0x1 0xa00 0x2 0x1 0x1 0x1>;
  10220. qcom,poll2 = <0x0 0xa00 0x2 0x1 0x1 0x1>;
  10221. qcom,mem2 = <0x30 0xa04 0x2 0x0 0x1 0x1>;
  10222. qcom,page3 = <0x1 0xa00 0x2 0x4 0x1 0x1>;
  10223. qcom,poll3 = <0x0 0xa00 0x2 0x4 0x1 0x1>;
  10224. qcom,mem3 = <0x0 0x0 0x2 0x0 0x1 0x0>;
  10225. qcom,page4 = <0x1 0xa00 0x2 0x0 0x1 0x1>;
  10226. qcom,poll4 = <0x0 0xa00 0x2 0x0 0x1 0x0>;
  10227. qcom,mem4 = <0x0 0x0 0x2 0x0 0x1 0x0>;
  10228. cam_vdig-supply = <0x18b>;
  10229. cam_vana-supply = <0x186>;
  10230. cam_vio-supply = <0x185>;
  10231. qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana";
  10232. qcom,cam-vreg-min-voltage = <0x124f80 0x1b7740 0x2ab980>;
  10233. qcom,cam-vreg-max-voltage = <0x124f80 0x1b7740 0x2ab980>;
  10234. qcom,cam-vreg-op-mode = <0x19a28 0x0 0x13880>;
  10235. qcom,gpio-no-mux = <0x0>;
  10236. pinctrl-names = "cam_default", "cam_suspend";
  10237. pinctrl-0 = <0x18c 0x18d>;
  10238. pinctrl-1 = <0x18e 0x18f>;
  10239. gpios = <0xbe 0x1b 0x0 0xbe 0x81 0x0 0xbe 0x82 0x0>;
  10240. qcom,gpio-reset = <0x1>;
  10241. qcom,gpio-standby = <0x2>;
  10242. qcom,gpio-req-tbl-num = <0x0 0x1 0x2>;
  10243. qcom,gpio-req-tbl-flags = <0x1 0x0 0x0>;
  10244. qcom,gpio-req-tbl-label = "CAMIF_MCLK2", "CAM_RESET2", "CAM_STANDBY2";
  10245. qcom,cam-power-seq-type = "sensor_vreg", "sensor_vreg", "sensor_vreg", "sensor_gpio", "sensor_gpio", "sensor_clk";
  10246. qcom,cam-power-seq-val = "cam_vana", "cam_vdig", "cam_vio", "sensor_gpio_standby", "sensor_gpio_reset", "sensor_cam_mclk";
  10247. qcom,cam-power-seq-cfg-val = <0x1 0x1 0x1 0x1 0x1 0x16e3600>;
  10248. qcom,cam-power-seq-delay = <0x1 0x1 0x1 0x5 0x5 0xa>;
  10249. status = "ok";
  10250. clocks = <0x37 0xa73cad0c 0x37 0x5002d85f>;
  10251. clock-names = "cam_src_clk", "cam_clk";
  10252. qcom,clock-rates = <0x124f800 0x0>;
  10253. linux,phandle = <0x194>;
  10254. phandle = <0x194>;
  10255. };
  10256.  
  10257. qcom,camera@0 {
  10258. cell-index = <0x0>;
  10259. compatible = "qcom,camera";
  10260. reg = <0x0>;
  10261. qcom,csiphy-sd-index = <0x0>;
  10262. qcom,csid-sd-index = <0x0>;
  10263. qcom,mount-angle = <0x5a>;
  10264. qcom,eeprom-src = <0x190>;
  10265. qcom,actuator-src = <0x191>;
  10266. qcom,led-flash-src = <0x192>;
  10267. cam_vdig-supply = <0x184>;
  10268. cam_vio-supply = <0x185>;
  10269. cam_vana-supply = <0x186>;
  10270. cam_vaf-supply = <0x183>;
  10271. qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana", "cam_vaf";
  10272. qcom,cam-vreg-min-voltage = <0x124f80 0x1b7740 0x2ab980 0x2b7cd0>;
  10273. qcom,cam-vreg-max-voltage = <0x124f80 0x1b7740 0x2ab980 0x2b7cd0>;
  10274. qcom,cam-vreg-op-mode = <0x30d40 0x13880 0x13880 0x186a0>;
  10275. pinctrl-names = "cam_default", "cam_suspend";
  10276. pinctrl-0 = <0x187 0x188>;
  10277. pinctrl-1 = <0x189 0x18a>;
  10278. gpios = <0xbe 0x1a 0x0 0xbe 0x28 0x0 0xbe 0x27 0x0>;
  10279. qcom,gpio-reset = <0x1>;
  10280. qcom,gpio-standby = <0x2>;
  10281. qcom,gpio-req-tbl-num = <0x0 0x1 0x2>;
  10282. qcom,gpio-req-tbl-flags = <0x1 0x0 0x0>;
  10283. qcom,gpio-req-tbl-label = "CAMIF_MCLK0", "CAM_RESET0", "CAM_STANDBY0";
  10284. qcom,sensor-position = <0x0>;
  10285. qcom,sensor-mode = <0x0>;
  10286. qcom,cci-master = <0x0>;
  10287. status = "ok";
  10288. clocks = <0x37 0x266b3853 0x37 0x80902deb>;
  10289. clock-names = "cam_src_clk", "cam_clk";
  10290. qcom,clock-rates = <0x16e3600 0x0>;
  10291. };
  10292.  
  10293. qcom,camera@2 {
  10294. cell-index = <0x2>;
  10295. compatible = "qcom,camera";
  10296. reg = <0x2>;
  10297. qcom,csiphy-sd-index = <0x2>;
  10298. qcom,csid-sd-index = <0x2>;
  10299. qcom,mount-angle = <0x10e>;
  10300. qcom,eeprom-src = <0x193 0x194>;
  10301. cam_vdig-supply = <0x18b>;
  10302. cam_vana-supply = <0x186>;
  10303. cam_vio-supply = <0x185>;
  10304. qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana";
  10305. qcom,cam-vreg-min-voltage = <0x124f80 0x1b7740 0x2ab980>;
  10306. qcom,cam-vreg-max-voltage = <0x124f80 0x1b7740 0x2ab980>;
  10307. qcom,cam-vreg-op-mode = <0x19a28 0x0 0x13880>;
  10308. qcom,gpio-no-mux = <0x0>;
  10309. pinctrl-names = "cam_default", "cam_suspend";
  10310. pinctrl-0 = <0x18c 0x18d>;
  10311. pinctrl-1 = <0x18e 0x18f>;
  10312. gpios = <0xbe 0x1b 0x0 0xbe 0x81 0x0 0xbe 0x82 0x0>;
  10313. qcom,gpio-reset = <0x1>;
  10314. qcom,gpio-standby = <0x2>;
  10315. qcom,gpio-req-tbl-num = <0x0 0x1 0x2>;
  10316. qcom,gpio-req-tbl-flags = <0x1 0x0 0x0>;
  10317. qcom,gpio-req-tbl-label = "CAMIF_MCLK2", "CAM_RESET2", "CAM_STANDBY2";
  10318. qcom,sensor-position = <0x1>;
  10319. qcom,sensor-mode = <0x0>;
  10320. qcom,cci-master = <0x1>;
  10321. status = "ok";
  10322. clocks = <0x37 0xa73cad0c 0x37 0x5002d85f>;
  10323. clock-names = "cam_src_clk", "cam_clk";
  10324. qcom,clock-rates = <0x16e3600 0x0>;
  10325. };
  10326. };
  10327.  
  10328. qcom,mdss_mdp@1a00000 {
  10329. compatible = "qcom,mdss_mdp";
  10330. reg = <0x1a00000 0x90000 0x1ab0000 0x1040>;
  10331. reg-names = "mdp_phys", "vbif_phys";
  10332. interrupts = <0x0 0x48 0x0>;
  10333. vdd-supply = <0x178>;
  10334. qcom,msm-bus,name = "mdss_mdp";
  10335. qcom,msm-bus,num-cases = <0x3>;
  10336. qcom,msm-bus,num-paths = <0x1>;
  10337. qcom,msm-bus,vectors-KBps = <0x16 0x200 0x0 0x0 0x16 0x200 0x0 0x61a800 0x16 0x200 0x0 0x61a800>;
  10338. qcom,mdss-ab-factor = <0x1 0x1>;
  10339. qcom,mdss-ib-factor = <0x1 0x1>;
  10340. qcom,mdss-clk-factor = <0x69 0x64>;
  10341. qcom,max-mixer-width = <0x800>;
  10342. qcom,max-pipe-width = <0x800>;
  10343. qcom,mdss-vbif-qos-rt-setting = <0x1 0x2 0x2 0x2>;
  10344. qcom,mdss-vbif-qos-nrt-setting = <0x1 0x1 0x1 0x1>;
  10345. qcom,mdss-has-panic-ctrl;
  10346. qcom,mdss-per-pipe-panic-luts = <0xf 0xffff 0xfffc 0xff00>;
  10347. qcom,mdss-mdp-reg-offset = <0x1000>;
  10348. qcom,max-bandwidth-low-kbps = <0x33e140>;
  10349. qcom,max-bandwidth-high-kbps = <0x33e140>;
  10350. qcom,max-bandwidth-per-pipe-kbps = <0x231860>;
  10351. qcom,max-clk-rate = <0x17d78400>;
  10352. qcom,mdss-default-ot-rd-limit = <0x20>;
  10353. qcom,mdss-default-ot-wr-limit = <0x10>;
  10354. qcom,max-bw-settings = <0x1 0x33e140 0x2 0x2f4d60>;
  10355. qcom,mdss-pipe-vig-off = <0x5000>;
  10356. qcom,mdss-pipe-rgb-off = <0x15000 0x17000>;
  10357. qcom,mdss-pipe-dma-off = <0x25000>;
  10358. qcom,mdss-pipe-cursor-off = <0x35000>;
  10359. qcom,mdss-pipe-vig-xin-id = <0x0>;
  10360. qcom,mdss-pipe-rgb-xin-id = <0x1 0x5>;
  10361. qcom,mdss-pipe-dma-xin-id = <0x2>;
  10362. qcom,mdss-pipe-cursor-xin-id = <0x7>;
  10363. qcom,mdss-pipe-vig-clk-ctrl-offsets = <0x2ac 0x0 0x0>;
  10364. qcom,mdss-pipe-rgb-clk-ctrl-offsets = <0x2ac 0x4 0x8 0x2b4 0x4 0x8>;
  10365. qcom,mdss-pipe-dma-clk-ctrl-offsets = <0x2ac 0x8 0xc>;
  10366. qcom,mdss-pipe-cursor-clk-ctrl-offsets = <0x3a8 0x10 0xf>;
  10367. qcom,mdss-ctl-off = <0x2000 0x2200 0x2400>;
  10368. qcom,mdss-mixer-intf-off = <0x45000 0x46000>;
  10369. qcom,mdss-dspp-off = <0x55000>;
  10370. qcom,mdss-wb-off = <0x65000 0x66000>;
  10371. qcom,mdss-intf-off = <0x6b000 0x6b800 0x6c000>;
  10372. qcom,mdss-pingpong-off = <0x71000 0x71800>;
  10373. qcom,mdss-slave-pingpong-off = <0x73000>;
  10374. qcom,mdss-cdm-off = <0x7a200>;
  10375. qcom,mdss-wfd-mode = "intf";
  10376. qcom,mdss-highest-bank-bit = <0x1>;
  10377. qcom,mdss-has-decimation;
  10378. qcom,mdss-has-non-scalar-rgb;
  10379. qcom,mdss-has-rotator-downscale;
  10380. qcom,mdss-idle-power-collapse-enabled;
  10381. qcom,mdss-rot-block-size = <0x40>;
  10382. qcom,mdss-ppb-off = <0x330>;
  10383. qcom,mdss-has-pingpong-split;
  10384. clocks = <0x37 0xbfb92ed3 0x37 0x668f51de 0x37 0x6dc1f8f1 0x195 0x588460a4 0x37 0x32a09f1f>;
  10385. clock-names = "iface_clk", "bus_clk", "core_clk_src", "core_clk", "vsync_clk";
  10386. qcom,mdp-settings = <0x1190 0x0 0x506c 0x0 0x1506c 0x0 0x1706c 0x0 0x2506c 0x0>;
  10387. qcom,vbif-settings = <0xd0 0x10>;
  10388. qcom,regs-dump-mdp = <0x1000 0x1454 0x2000 0x2064 0x2200 0x2264 0x2400 0x2464 0x5000 0x5150 0x5200 0x5230 0x15000 0x15150 0x17000 0x17150 0x25000 0x25150 0x35000 0x35150 0x45000 0x452bc 0x46000 0x462bc 0x55000 0x5522c 0x65000 0x652c0 0x66000 0x662c0 0x6b800 0x6ba68 0x6c000 0x6c268 0x71000 0x710d4 0x71800 0x718d4>;
  10389. qcom,regs-dump-names-mdp = "MDP", "CTL_0", "CTL_1", "CTL_2", "VIG0_SSPP", "VIG0", "RGB0_SSPP", "RGB1_SSPP", "DMA0_SSPP", "CURSOR0_SSPP", "LAYER_0", "LAYER_1", "DSPP_0", "WB_0", "WB_2", "INTF_1", "INTF_2", "PP_0", "PP_1";
  10390. qcom,mdss-prefill-outstanding-buffer-bytes = <0x0>;
  10391. qcom,mdss-prefill-y-buffer-bytes = <0x0>;
  10392. qcom,mdss-prefill-scaler-buffer-lines-bilinear = <0x2>;
  10393. qcom,mdss-prefill-scaler-buffer-lines-caf = <0x4>;
  10394. qcom,mdss-prefill-post-scaler-buffer-pixels = <0x800>;
  10395. qcom,mdss-prefill-pingpong-buffer-pixels = <0x1000>;
  10396. qcom,mdss-pref-prim-intf = "dsi";
  10397. linux,phandle = <0x19b>;
  10398. phandle = <0x19b>;
  10399.  
  10400. qcom,mdss-pp-offsets {
  10401. qcom,mdss-sspp-mdss-igc-lut-off = <0x2000>;
  10402. qcom,mdss-sspp-vig-pcc-off = <0x1780>;
  10403. qcom,mdss-sspp-rgb-pcc-off = <0x380>;
  10404. qcom,mdss-sspp-dma-pcc-off = <0x380>;
  10405. qcom,mdss-lm-pgc-off = <0x3c0>;
  10406. qcom,mdss-dspp-pcc-off = <0x1700>;
  10407. qcom,mdss-dspp-pgc-off = <0x17c0>;
  10408. };
  10409.  
  10410. qcom,mdss-reg-bus {
  10411. qcom,msm-bus,name = "mdss_reg";
  10412. qcom,msm-bus,num-cases = <0x4>;
  10413. qcom,msm-bus,num-paths = <0x1>;
  10414. qcom,msm-bus,active-only;
  10415. qcom,msm-bus,vectors-KBps = <0x1 0x24e 0x0 0x0 0x1 0x24e 0x0 0x12c00 0x1 0x24e 0x0 0x27100 0x1 0x24e 0x0 0x4e200>;
  10416. };
  10417.  
  10418. qcom,mdss-hw-rt-bus {
  10419. qcom,msm-bus,name = "mdss_hw_rt";
  10420. qcom,msm-bus,num-cases = <0x2>;
  10421. qcom,msm-bus,num-paths = <0x1>;
  10422. qcom,msm-bus,vectors-KBps = <0x16 0x200 0x0 0x0 0x16 0x200 0x0 0x3e8>;
  10423. };
  10424.  
  10425. qcom,smmu_mdp_unsec_cb {
  10426. compatible = "qcom,smmu_mdp_unsec";
  10427. };
  10428.  
  10429. qcom,smmu_mdp_sec_cb {
  10430. compatible = "qcom,smmu_mdp_sec";
  10431. };
  10432.  
  10433. qcom,mdss_fb_primary {
  10434. cell-index = <0x0>;
  10435. compatible = "qcom,mdss-fb";
  10436. linux,phandle = <0x199>;
  10437. phandle = <0x199>;
  10438.  
  10439. qcom,cont-splash-memory {
  10440. linux,contiguous-region = <0x196>;
  10441. };
  10442. };
  10443.  
  10444. qcom,mdss_fb_wfd {
  10445. cell-index = <0x1>;
  10446. compatible = "qcom,mdss-fb";
  10447. linux,phandle = <0x1a5>;
  10448. phandle = <0x1a5>;
  10449. };
  10450.  
  10451. qcom,mdss_fb_secondary {
  10452. cell-index = <0x2>;
  10453. compatible = "qcom,mdss-fb";
  10454. linux,phandle = <0x19a>;
  10455. phandle = <0x19a>;
  10456. };
  10457.  
  10458. qcom,mdss_dsi_nt35521s_ebbg_720p_video {
  10459. qcom,mdss-dsi-panel-name = "nt35521s_HD720p_video_EBBG";
  10460. qcom,mdss-dsi-panel-controller = <0x197>;
  10461. qcom,mdss-dsi-panel-type = "dsi_video_mode";
  10462. qcom,mdss-dsi-panel-destination = "display_1";
  10463. qcom,mdss-dsi-panel-framerate = <0x3c>;
  10464. qcom,mdss-dsi-virtual-channel-id = <0x0>;
  10465. qcom,mdss-dsi-stream = <0x0>;
  10466. qcom,mdss-dsi-panel-width = <0x2d0>;
  10467. qcom,mdss-dsi-panel-height = <0x500>;
  10468. qcom,mdss-pan-physical-width-dimension = <0x3e>;
  10469. qcom,mdss-pan-physical-height-dimension = <0x6e>;
  10470. qcom,mdss-dsi-h-front-porch = <0x64>;
  10471. qcom,mdss-dsi-h-back-porch = <0x64>;
  10472. qcom,mdss-dsi-h-pulse-width = <0x14>;
  10473. qcom,mdss-dsi-h-sync-skew = <0x0>;
  10474. qcom,mdss-dsi-v-back-porch = <0x1c>;
  10475. qcom,mdss-dsi-v-front-porch = <0x23>;
  10476. qcom,mdss-dsi-v-pulse-width = <0x2>;
  10477. qcom,mdss-dsi-h-left-border = <0x0>;
  10478. qcom,mdss-dsi-h-right-border = <0x0>;
  10479. qcom,mdss-dsi-v-top-border = <0x0>;
  10480. qcom,mdss-dsi-v-bottom-border = <0x14>;
  10481. qcom,mdss-dsi-bpp = <0x18>;
  10482. qcom,mdss-dsi-underflow-color = <0xff>;
  10483. qcom,mdss-dsi-border-color = <0x0>;
  10484. qcom,mdss-dsi-on-command = [29 01 00 00 00 00 05 ff aa 55 25 00 29 01 00 00 00 00 02 35 00 05 01 00 00 78 00 02 11 00 05 01 00 00 00 00 02 29 00];
  10485. qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00 05 01 00 00 78 00 02 10 00];
  10486. qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
  10487. qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
  10488. qcom,mdss-dsi-h-sync-pulse = <0x1>;
  10489. qcom,mdss-dsi-traffic-mode = "burst_mode";
  10490. qcom,mdss-dsi-bllp-eof-power-mode;
  10491. qcom,mdss-dsi-bllp-power-mode;
  10492. qcom,mdss-dsi-lane-0-state;
  10493. qcom,mdss-dsi-lane-1-state;
  10494. qcom,mdss-dsi-lane-2-state;
  10495. qcom,mdss-dsi-lane-3-state;
  10496. qcom,mdss-dsi-panel-timings = <0x871c1200 0x42421820 0x17030400>;
  10497. qcom,mdss-dsi-panel-timings-8996 = <0x1e1c0406 0x20304a0 0x1e1c0406 0x20304a0 0x1e1c0406 0x20304a0 0x1e1c0406 0x20304a0 0x1e0e0405 0x20304a0>;
  10498. qcom,mdss-dsi-t-clk-post = <0x4>;
  10499. qcom,mdss-dsi-t-clk-pre = <0x1b>;
  10500. qcom,mdss-dsi-bl-min-level = <0x1>;
  10501. qcom,mdss-dsi-bl-max-level = <0xfff>;
  10502. qcom,mdss-dsi-dma-trigger = "trigger_sw";
  10503. qcom,mdss-dsi-mdp-trigger = "none";
  10504. qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
  10505. qcom,mdss-dsi-reset-sequence = <0x1 0x32 0x0 0x14 0x1 0x32>;
  10506. qcom,mdss-dsi-lp11-init;
  10507. qcom,mdss-dsi-init-delay-us = <0xc350>;
  10508. qcom,panel-supply-entries = <0x198>;
  10509. linux,phandle = <0x19e>;
  10510. phandle = <0x19e>;
  10511. };
  10512.  
  10513. qcom,mdss_dsi_nt35596_ebbg_1080p_video {
  10514. qcom,mdss-dsi-panel-name = "nt35596_1080p_video_EBBG";
  10515. qcom,mdss-dsi-panel-controller = <0x197>;
  10516. qcom,mdss-dsi-panel-type = "dsi_video_mode";
  10517. qcom,mdss-dsi-panel-destination = "display_1";
  10518. qcom,mdss-dsi-panel-framerate = <0x3c>;
  10519. qcom,mdss-dsi-virtual-channel-id = <0x0>;
  10520. qcom,mdss-dsi-stream = <0x0>;
  10521. qcom,mdss-dsi-panel-width = <0x438>;
  10522. qcom,mdss-dsi-panel-height = <0x780>;
  10523. qcom,mdss-dsi-h-front-porch = <0x7c>;
  10524. qcom,mdss-dsi-h-back-porch = <0x78>;
  10525. qcom,mdss-dsi-h-pulse-width = <0x4>;
  10526. qcom,mdss-dsi-h-sync-skew = <0x0>;
  10527. qcom,mdss-dsi-v-back-porch = <0xf>;
  10528. qcom,mdss-dsi-v-front-porch = <0x8>;
  10529. qcom,mdss-dsi-v-pulse-width = <0x5>;
  10530. qcom,mdss-dsi-h-left-border = <0x0>;
  10531. qcom,mdss-dsi-h-right-border = <0x0>;
  10532. qcom,mdss-dsi-v-top-border = <0x0>;
  10533. qcom,mdss-dsi-v-bottom-border = <0x0>;
  10534. qcom,mdss-dsi-bpp = <0x18>;
  10535. qcom,mdss-dsi-underflow-color = <0xff>;
  10536. qcom,mdss-dsi-border-color = <0x0>;
  10537. qcom,mdss-dsi-on-command = [29 01 00 00 00 00 02 ff ee 29 01 00 00 0a 00 02 18 40 29 01 00 00 0a 00 02 18 00 29 01 00 00 00 00 02 ff 00 29 01 00 00 00 00 02 35 00 29 01 00 00 00 00 02 d3 14 29 01 00 00 00 00 02 d4 08 29 01 00 00 78 00 02 11 00 29 01 00 00 0a 00 02 29 00];
  10538. qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00];
  10539. qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
  10540. qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
  10541. qcom,mdss-dsi-h-sync-pulse = <0x1>;
  10542. qcom,mdss-dsi-traffic-mode = "burst_mode";
  10543. qcom,mdss-dsi-bllp-eof-power-mode;
  10544. qcom,mdss-dsi-bllp-power-mode;
  10545. qcom,mdss-dsi-lane-0-state;
  10546. qcom,mdss-dsi-lane-1-state;
  10547. qcom,mdss-dsi-lane-2-state;
  10548. qcom,mdss-dsi-lane-3-state;
  10549. qcom,mdss-dsi-panel-timings = <0xf23a2800 0x6c6e2c3e 0x2e030400>;
  10550. qcom,mdss-dsi-panel-timings-8996 = <0x241f0809 0x50304a0 0x241f0809 0x50304a0 0x241f0809 0x50304a0 0x241f0809 0x50304a0 0x241c0809 0x50304a0>;
  10551. qcom,mdss-dsi-t-clk-post = <0x2>;
  10552. qcom,mdss-dsi-t-clk-pre = <0x2d>;
  10553. qcom,mdss-dsi-bl-min-level = <0x1>;
  10554. qcom,mdss-dsi-bl-max-level = <0xfff>;
  10555. qcom,mdss-dsi-dma-trigger = "trigger_sw";
  10556. qcom,mdss-dsi-mdp-trigger = "none";
  10557. qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
  10558. qcom,mdss-dsi-reset-sequence = <0x1 0x14 0x0 0xa 0x1 0x14 0x0 0xa 0x1 0x14>;
  10559. qcom,mdss-dsi-panel-warm-command = <0x29010000 0x2ff 0x1290000 0x2 0x75002900 0x0 0x2763329 0x0 0x27700 0x29000000 0x278 0x40290000 0x2 0x79002900 0x0 0x27a5b29 0x0 0x27b00 0x29000000 0x27c 0x77290000 0x2 0x7d002900 0x0 0x27e9329 0x0 0x27f00 0x29000000 0x280 0xa4290000 0x2 0x81002900 0x0 0x282b429 0x0 0x28300 0x29000000 0x284 0xc1290000 0x2 0x85002900 0x0 0x286cb29 0x0 0x28700 0x29000000 0x288 0xfd290000 0x2 0x89012900 0x0 0x28a2029 0x0 0x28b01 0x29000000 0x28c 0x5d290000 0x2 0x8d012900 0x0 0x28e8a29 0x0 0x28f01 0x29000000 0x290 0xd4290000 0x2 0x91022900 0x0 0x2921229 0x0 0x29302 0x29000000 0x294 0x14290000 0x2 0x95022900 0x0 0x2964b29 0x0 0x29702 0x29000000 0x298 0x88290000 0x2 0x99022900 0x0 0x29aac29 0x0 0x29b02 0x29000000 0x29c 0xe2290000 0x2 0x9d032900 0x0 0x29e0a29 0x0 0x29f03 0x29000000 0x2a0 0x33290000 0x2 0xa2032900 0x0 0x2a34229 0x0 0x2a403 0x29000000 0x2a5 0x51290000 0x2 0xa6032900 0x0 0x2a75f29 0x0 0x2a903 0x29000000 0x2aa 0x72290000 0x2 0xab032900 0x0 0x2ac8829 0x0 0x2ad03 0x29000000 0x2ae 0xab290000 0x2 0xaf032900 0x0 0x2b0c929 0x0 0x2b103 0x29000000 0x2b2 0xcb290000 0x2 0xb3002900 0x0 0x2b43329 0x0 0x2b500 0x29000000 0x2b6 0x40290000 0x2 0xb7002900 0x0 0x2b85b29 0x0 0x2b900 0x29000000 0x2ba 0x77290000 0x2 0xbb002900 0x0 0x2bc9329 0x0 0x2bd00 0x29000000 0x2be 0xa4290000 0x2 0xbf002900 0x0 0x2c0b429 0x0 0x2c100 0x29000000 0x2c2 0xc1290000 0x2 0xc3002900 0x0 0x2c4cb29 0x0 0x2c500 0x29000000 0x2c6 0xfd290000 0x2 0xc7012900 0x0 0x2c82029 0x0 0x2c901 0x29000000 0x2ca 0x5d290000 0x2 0xcb012900 0x0 0x2cc8a29 0x0 0x2cd01 0x29000000 0x2ce 0xd4290000 0x2 0xcf022900 0x0 0x2d01229 0x0 0x2d102 0x29000000 0x2d2 0x14290000 0x2 0xd3022900 0x0 0x2d44b29 0x0 0x2d502 0x29000000 0x2d6 0x88290000 0x2 0xd7022900 0x0 0x2d8ac29 0x0 0x2d902 0x29000000 0x2da 0xe2290000 0x2 0xdb032900 0x0 0x2dc0a29 0x0 0x2dd03 0x29000000 0x2de 0x33290000 0x2 0xdf032900 0x0 0x2e04229 0x0 0x2e103 0x29000000 0x2e2 0x51290000 0x2 0xe3032900 0x0 0x2e45f29 0x0 0x2e503 0x29000000 0x2e6 0x72290000 0x2 0xe7032900 0x0 0x2e88829 0x0 0x2e903 0x29000000 0x2ea 0xab290000 0x2 0xeb032900 0x0 0x2ecc929 0x0 0x2ed03 0x29000000 0x2ee 0xcb290000 0x2 0xef002900 0x0 0x2f0cb29 0x0 0x2f100 0x29000000 0x2f2 0xd2290000 0x2 0xf3002900 0x0 0x2f4dd29 0x0 0x2f500 0x29000000 0x2f6 0xe7290000 0x2 0xf7002900 0x0 0x2f8f129 0x0 0x2f900 0x29010000 0x2fa 0xfa290100 0x2 0xfb012901 0x0 0x2ff0229 0x0 0x20001 0x29000000 0x201 0x4290000 0x2 0x2012900 0x0 0x2030d29 0x0 0x20401 0x29000000 0x205 0x16290000 0x2 0x6012900 0x0 0x2073629 0x0 0x20801 0x29000000 0x209 0x50290000 0x2 0xa012900 0x0 0x20b7e29 0x0 0x20c01 0x29000000 0x20d 0xa5290000 0x2 0xe012900 0x0 0x20fe729 0x0 0x21002 0x29000000 0x211 0x1e290000 0x2 0x12022900 0x0 0x2132029 0x0 0x21402 0x29000000 0x215 0x54290000 0x2 0x16022900 0x0 0x2179129 0x0 0x21802 0x29000000 0x219 0xb8290000 0x2 0x1a022900 0x0 0x21beb29 0x0 0x21c03 0x29000000 0x21d 0xd290000 0x2 0x1e032900 0x0 0x21f3629 0x0 0x22003 0x29000000 0x221 0x44290000 0x2 0x22032900 0x0 0x2235229 0x0 0x22403 0x29000000 0x225 0x61290000 0x2 0x26032900 0x0 0x2277429 0x0 0x22803 0x29000000 0x229 0x89290000 0x2 0x2a032900 0x0 0x22b9e29 0x0 0x22d03 0x29000000 0x22f 0xc5290000 0x2 0x30032900 0x0 0x231cb29 0x0 0x23200 0x29000000 0x233 0xcb290000 0x2 0x34002900 0x0 0x235d229 0x0 0x23600 0x29000000 0x237 0xdd290000 0x2 0x38002900 0x0 0x239e729 0x0 0x23a00 0x29000000 0x23b 0xf1290000 0x2 0x3d002900 0x0 0x23ffa29 0x0 0x24001 0x29000000 0x241 0x4290000 0x2 0x42012900 0x0 0x2430d29 0x0 0x24401 0x29000000 0x245 0x16290000 0x2 0x46012900 0x0 0x2473629 0x0 0x24801 0x29000000 0x249 0x50290000 0x2 0x4a012900 0x0 0x24b7e29 0x0 0x24c01 0x29000000 0x24d 0xa5290000 0x2 0x4e012900 0x0 0x24fe729 0x0 0x25002 0x29000000 0x251 0x1e290000 0x2 0x52022900 0x0 0x2532029 0x0 0x25402 0x29000000 0x255 0x54290000 0x2 0x56022900 0x0 0x2589129 0x0 0x25902 0x29000000 0x25a 0xb8290000 0x2 0x5b022900 0x0 0x25ceb29 0x0 0x25d03 0x29000000 0x25e 0xd290000 0x2 0x5f032900 0x0 0x2603629 0x0 0x26103 0x29000000 0x262 0x44290000 0x2 0x63032900 0x0 0x2645229 0x0 0x26503 0x29000000 0x266 0x61290000 0x2 0x67032900 0x0 0x2687429 0x0
  10560. 0x26903 0x29000000 0x26a 0x89290000 0x2 0x6b032900 0x0 0x26c9e29 0x0 0x26d03 0x29000000 0x26e 0xc5290000 0x2 0x6f032900 0x0 0x270cb29 0x0 0x27100 0x29000000 0x272 0xf2290000 0x2 0x73002900 0x0 0x274f629 0x0 0x27500 0x29000000 0x276 0xfe290000 0x2 0x77012900 0x0 0x2780729 0x0 0x27901 0x29000000 0x27a 0xf290000 0x2 0x7b012900 0x0 0x27c1729 0x0 0x27d01 0x29000000 0x27e 0x1e290000 0x2 0x7f012900 0x0 0x2802429 0x0 0x28101 0x29000000 0x282 0x2b290000 0x2 0x83012900 0x0 0x2844829 0x0 0x28501 0x29000000 0x286 0x5f290000 0x2 0x87012900 0x0 0x2888829 0x0 0x28901 0x29000000 0x28a 0xaf290000 0x2 0x8b012900 0x0 0x28cec29 0x0 0x28d02 0x29000000 0x28e 0x22290000 0x2 0x8f022900 0x0 0x2902329 0x0 0x29102 0x29000000 0x292 0x57290000 0x2 0x93022900 0x0 0x2949329 0x0 0x29502 0x29000000 0x296 0xba290000 0x2 0x97022900 0x0 0x298ef29 0x0 0x29903 0x29000000 0x29a 0x8290000 0x2 0x9b032900 0x0 0x29c2929 0x0 0x29d03 0x29000000 0x29e 0x33290000 0x2 0x9f032900 0x0 0x2a04229 0x0 0x2a203 0x29000000 0x2a3 0x52290000 0x2 0xa4032900 0x0 0x2a56329 0x0 0x2a603 0x29000000 0x2a7 0x7b290000 0x2 0xa9032900 0x0 0x2aa9b29 0x0 0x2ab03 0x29000000 0x2ac 0xc7290000 0x2 0xad032900 0x0 0x2aecb29 0x0 0x2af00 0x29000000 0x2b0 0xf2290000 0x2 0xb1002900 0x0 0x2b2f629 0x0 0x2b300 0x29000000 0x2b4 0xfe290000 0x2 0xb5012900 0x0 0x2b60729 0x0 0x2b701 0x29000000 0x2b8 0xf290000 0x2 0xb9012900 0x0 0x2ba1729 0x0 0x2bb01 0x29000000 0x2bc 0x1e290000 0x2 0xbd012900 0x0 0x2be2429 0x0 0x2bf01 0x29000000 0x2c0 0x2b290000 0x2 0xc1012900 0x0 0x2c24829 0x0 0x2c301 0x29000000 0x2c4 0x5f290000 0x2 0xc5012900 0x0 0x2c68829 0x0 0x2c701 0x29000000 0x2c8 0xaf290000 0x2 0xc9012900 0x0 0x2caec29 0x0 0x2cb02 0x29000000 0x2cc 0x22290000 0x2 0xcd022900 0x0 0x2ce2329 0x0 0x2cf02 0x29000000 0x2d0 0x57290000 0x2 0xd1022900 0x0 0x2d29329 0x0 0x2d302 0x29000000 0x2d4 0xba290000 0x2 0xd5022900 0x0 0x2d6ef29 0x0 0x2d703 0x29000000 0x2d8 0x8290000 0x2 0xd9032900 0x0 0x2da2929 0x0 0x2db03 0x29000000 0x2dc 0x33290000 0x2 0xdd032900 0x0 0x2de4229 0x0 0x2df03 0x29000000 0x2e0 0x52290000 0x2 0xe1032900 0x0 0x2e26329 0x0 0x2e303 0x29000000 0x2e4 0x7b290000 0x2 0xe5032900 0x0 0x2e69b29 0x0 0x2e703 0x29000000 0x2e8 0xc7290000 0x2 0xe9032901 0x0 0x2eacb29 0x1000000 0x2fb01>;
  10561. qcom,mdss-dsi-panel-cool-command = <0x29010000 0x2ff 0x1290000 0x2 0x75002900 0x0 0x276b029 0x0 0x27700 0x29000000 0x278 0xb9290000 0x2 0x79002900 0x0 0x27ac529 0x0 0x27b00 0x29000000 0x27c 0xd0290000 0x2 0x7d002900 0x0 0x27ede29 0x0 0x27f00 0x29000000 0x280 0xef290000 0x2 0x81002900 0x0 0x282fb29 0x0 0x28301 0x29000000 0x284 0x5290000 0x2 0x85012900 0x0 0x2860e29 0x0 0x28701 0x29000000 0x288 0x2f290000 0x2 0x89012900 0x0 0x28a5329 0x0 0x28b01 0x29000000 0x28c 0x81290000 0x2 0x8d012900 0x0 0x28eab29 0x0 0x28f01 0x29000000 0x290 0xf1290000 0x2 0x91022900 0x0 0x2922929 0x0 0x29302 0x29000000 0x294 0x2a290000 0x2 0x95022900 0x0 0x2966029 0x0 0x29702 0x29000000 0x298 0x9f290000 0x2 0x99022900 0x0 0x29ac729 0x0 0x29b02 0x29000000 0x29c 0xfd290000 0x2 0x9d032900 0x0 0x29e1f29 0x0 0x29f03 0x29000000 0x2a0 0x4a290000 0x2 0xa2032900 0x0 0x2a35829 0x0 0x2a403 0x29000000 0x2a5 0x63290000 0x2 0xa6032900 0x0 0x2a77529 0x0 0x2a903 0x29000000 0x2aa 0x86290000 0x2 0xab032900 0x0 0x2ac9e29 0x0 0x2ad03 0x29000000 0x2ae 0xc5290000 0x2 0xaf032900 0x0 0x2b0ca29 0x0 0x2b103 0x29000000 0x2b2 0xcb290000 0x2 0xb3002900 0x0 0x2b4b029 0x0 0x2b500 0x29000000 0x2b6 0xb9290000 0x2 0xb7002900 0x0 0x2b8c529 0x0 0x2b900 0x29000000 0x2ba 0xd0290000 0x2 0xbb002900 0x0 0x2bcde29 0x0 0x2bd00 0x29000000 0x2be 0xef290000 0x2 0xbf002900 0x0 0x2c0fb29 0x0 0x2c101 0x29000000 0x2c2 0x5290000 0x2 0xc3012900 0x0 0x2c40e29 0x0 0x2c501 0x29000000 0x2c6 0x2f290000 0x2 0xc7012900 0x0 0x2c85329 0x0 0x2c901 0x29000000 0x2ca 0x81290000 0x2 0xcb012900 0x0 0x2ccab29 0x0 0x2cd01 0x29000000 0x2ce 0xf1290000 0x2 0xcf022900 0x0 0x2d02929 0x0 0x2d102 0x29000000 0x2d2 0x2a290000 0x2 0xd3022900 0x0 0x2d46029 0x0 0x2d502 0x29000000 0x2d6 0x9f290000 0x2 0xd7022900 0x0 0x2d8c729 0x0 0x2d902 0x29000000 0x2da 0xfd290000 0x2 0xdb032900 0x0 0x2dc1f29 0x0 0x2dd03 0x29000000 0x2de 0x4a290000 0x2 0xdf032900 0x0 0x2e05829 0x0 0x2e103 0x29000000 0x2e2 0x63290000 0x2 0xe3032900 0x0 0x2e47529 0x0 0x2e503 0x29000000 0x2e6 0x86290000 0x2 0xe7032900 0x0 0x2e89e29 0x0 0x2e903 0x29000000 0x2ea 0xc5290000 0x2 0xeb032900 0x0 0x2ecca29 0x0 0x2ed03 0x29000000 0x2ee 0xcb290000 0x2 0xef002900 0x0 0x2f09e29 0x0 0x2f100 0x29000000 0x2f2 0xa6290000 0x2 0xf3002900 0x0 0x2f4b729 0x0 0x2f500 0x29000000 0x2f6 0xc6290000 0x2 0xf7002900 0x0 0x2f8d529 0x0 0x2f900 0x29010000 0x2fa 0xe1290100 0x2 0xfb012901 0x0 0x2ff0229 0x0 0x20000 0x29000000 0x201 0xec290000 0x2 0x2002900 0x0 0x203f629 0x0 0x20401 0x29000000 0x205 0x290000 0x2 0x6012900 0x0 0x2072529 0x0 0x20801 0x29000000 0x209 0x46290000 0x2 0xa012900 0x0 0x20b7a29 0x0 0x20c01 0x29000000 0x20d 0xa6290000 0x2 0xe012900 0x0 0x20fec29 0x0 0x21002 0x29000000 0x211 0x26290000 0x2 0x12022900 0x0 0x2132829 0x0 0x21402 0x29000000 0x215 0x5f290000 0x2 0x16022900 0x0 0x2179f29 0x0 0x21802 0x29000000 0x219 0xc7290000 0x2 0x1a022900 0x0 0x21bfd29 0x0 0x21c03 0x29000000 0x21d 0x1f290000 0x2 0x1e032900 0x0 0x21f4a29 0x0 0x22003 0x29000000 0x221 0x58290000 0x2 0x22032900 0x0 0x2236429 0x0 0x22403 0x29000000 0x225 0x76290000 0x2 0x26032900 0x0 0x2278629 0x0 0x22803 0x29000000 0x229 0x99290000 0x2 0x2a032900 0x0 0x22bae29 0x0 0x22d03 0x29000000 0x22f 0xc9290000 0x2 0x30032900 0x0 0x231cb29 0x0 0x23200 0x29000000 0x233 0x9e290000 0x2 0x34002900 0x0 0x235a629 0x0 0x23600 0x29000000 0x237 0xb7290000 0x2 0x38002900 0x0 0x239c629 0x0 0x23a00 0x29000000 0x23b 0xd5290000 0x2 0x3d002900 0x0 0x23fe129 0x0 0x24000 0x29000000 0x241 0xec290000 0x2 0x42002900 0x0 0x243f629 0x0 0x24401 0x29000000 0x245 0x290000 0x2 0x46012900 0x0 0x2472529 0x0 0x24801 0x29000000 0x249 0x46290000 0x2 0x4a012900 0x0 0x24b7a29 0x0 0x24c01 0x29000000 0x24d 0xa6290000 0x2 0x4e012900 0x0 0x24fec29 0x0 0x25002 0x29000000 0x251 0x26290000 0x2 0x52022900 0x0 0x2532829 0x0 0x25402 0x29000000 0x255 0x5f290000 0x2 0x56022900 0x0 0x2589f29 0x0 0x25902 0x29000000 0x25a 0xc7290000 0x2 0x5b022900 0x0 0x25cfd29 0x0 0x25d03 0x29000000 0x25e 0x1f290000 0x2 0x5f032900 0x0 0x2604a29 0x0 0x26103 0x29000000 0x262 0x58290000 0x2 0x63032900 0x0 0x2646429 0x0 0x26503 0x29000000 0x266 0x75290000 0x2 0x67032900 0x0 0x2688629 0x0
  10562. 0x26903 0x29000000 0x26a 0x99290000 0x2 0x6b032900 0x0 0x26cae29 0x0 0x26d03 0x29000000 0x26e 0xc9290000 0x2 0x6f032900 0x0 0x270cb29 0x0 0x27100 0x29000000 0x272 0x30290000 0x2 0x73002900 0x0 0x2743f29 0x0 0x27500 0x29000000 0x276 0x5c290000 0x2 0x77002900 0x0 0x2787229 0x0 0x27900 0x29000000 0x27a 0x85290000 0x2 0x7b002900 0x0 0x27c9729 0x0 0x27d00 0x29000000 0x27e 0xa9290000 0x2 0x7f002900 0x0 0x280ba29 0x0 0x28100 0x29000000 0x282 0xc7290000 0x2 0x83002900 0x0 0x284f729 0x0 0x28501 0x29000000 0x286 0x1e290000 0x2 0x87012900 0x0 0x2885c29 0x0 0x28901 0x29000000 0x28a 0x8c290000 0x2 0x8b012900 0x0 0x28cdc29 0x0 0x28d02 0x29000000 0x28e 0x1b290000 0x2 0x8f022900 0x0 0x2901d29 0x0 0x29102 0x29000000 0x292 0x56290000 0x2 0x93022900 0x0 0x2949829 0x0 0x29502 0x29000000 0x296 0xc1290000 0x2 0x97022900 0x0 0x298fb29 0x0 0x29903 0x29000000 0x29a 0x1d290000 0x2 0x9b032900 0x0 0x29c4729 0x0 0x29d03 0x29000000 0x29e 0x54290000 0x2 0x9f032900 0x0 0x2a06029 0x0 0x2a203 0x29000000 0x2a3 0x72290000 0x2 0xa4032900 0x0 0x2a58229 0x0 0x2a603 0x29000000 0x2a7 0x9c290000 0x2 0xa9032900 0x0 0x2aac329 0x0 0x2ab03 0x29000000 0x2ac 0xc9290000 0x2 0xad032900 0x0 0x2aecb29 0x0 0x2af00 0x29000000 0x2b0 0x30290000 0x2 0xb1002900 0x0 0x2b23f29 0x0 0x2b300 0x29000000 0x2b4 0x5c290000 0x2 0xb5002900 0x0 0x2b67229 0x0 0x2b700 0x29000000 0x2b8 0x85290000 0x2 0xb9002900 0x0 0x2ba9729 0x0 0x2bb00 0x29000000 0x2bc 0xa9290000 0x2 0xbd002900 0x0 0x2beba29 0x0 0x2bf00 0x29000000 0x2c0 0xc7290000 0x2 0xc1002900 0x0 0x2c2f729 0x0 0x2c301 0x29000000 0x2c4 0x1e290000 0x2 0xc5012900 0x0 0x2c65c29 0x0 0x2c701 0x29000000 0x2c8 0x8c290000 0x2 0xc9012900 0x0 0x2cadc29 0x0 0x2cb02 0x29000000 0x2cc 0x1b290000 0x2 0xcd022900 0x0 0x2ce1d29 0x0 0x2cf02 0x29000000 0x2d0 0x56290000 0x2 0xd1022900 0x0 0x2d29829 0x0 0x2d302 0x29000000 0x2d4 0xc1290000 0x2 0xd5022900 0x0 0x2d6fb29 0x0 0x2d703 0x29000000 0x2d8 0x1d290000 0x2 0xd9032900 0x0 0x2da4729 0x0 0x2db03 0x29000000 0x2dc 0x54290000 0x2 0xdd032900 0x0 0x2de6029 0x0 0x2df03 0x29000000 0x2e0 0x72290000 0x2 0xe1032900 0x0 0x2e28229 0x0 0x2e303 0x29000000 0x2e4 0x9c290000 0x2 0xe5032900 0x0 0x2e6c329 0x0 0x2e703 0x29000000 0x2e8 0xc9290000 0x2 0xe9032901 0x0 0x2eacb29 0x1000000 0x2fb01>;
  10563. qcom,mdss-dsi-panel-nature-command = [29 01 00 00 00 00 02 fb 00 29 01 00 00 00 00 02 ff 00 29 01 00 00 00 00 02 11 00];
  10564. qcom,mdss-dsi-panel-ce-std-command = [29 01 00 00 00 00 02 ff 00 29 01 00 00 00 00 02 55 00];
  10565. qcom,mdss-dsi-panel-ce-bright-command = [29 01 00 00 00 00 02 ff 00 29 01 00 00 00 00 02 55 80];
  10566. qcom,mdss-dsi-panel-ce-vivid-command = [29 01 00 00 00 00 02 ff 00 29 01 00 00 00 00 02 55 b0];
  10567. qcom,mdss-dsi-panel-gamma-command-state = "dsi_hs_mode";
  10568. qcom,mdss-dsi-panel-ce-command-state = "dsi_hs_mode";
  10569. qcom,mdss-dsi-lp11-init;
  10570. qcom,mdss-dsi-init-delay-us = <0xc350>;
  10571. qcom,mdss-pan-physical-width-dimension = <0x3e>;
  10572. qcom,mdss-pan-physical-height-dimension = <0x6e>;
  10573. qcom,mdss-night-brightness = <0x9 0x1b 0x2d 0x3f>;
  10574. qcom,panel-supply-entries = <0x198>;
  10575. linux,phandle = <0x19f>;
  10576. phandle = <0x19f>;
  10577. };
  10578.  
  10579. qcom,mdss_dsi_r63350_1080p_video {
  10580. qcom,mdss-dsi-panel-name = "r63350_1080p_video_Tianma";
  10581. qcom,mdss-dsi-panel-controller = <0x197>;
  10582. qcom,mdss-dsi-panel-type = "dsi_video_mode";
  10583. qcom,mdss-dsi-panel-destination = "display_1";
  10584. qcom,mdss-dsi-panel-framerate = <0x3c>;
  10585. qcom,mdss-dsi-virtual-channel-id = <0x0>;
  10586. qcom,mdss-dsi-stream = <0x0>;
  10587. qcom,mdss-dsi-panel-width = <0x438>;
  10588. qcom,mdss-dsi-panel-height = <0x780>;
  10589. qcom,mdss-dsi-h-front-porch = <0x5c>;
  10590. qcom,mdss-dsi-h-back-porch = <0x32>;
  10591. qcom,mdss-dsi-h-pulse-width = <0xc>;
  10592. qcom,mdss-dsi-h-sync-skew = <0x0>;
  10593. qcom,mdss-dsi-v-back-porch = <0x4>;
  10594. qcom,mdss-dsi-v-front-porch = <0x4>;
  10595. qcom,mdss-dsi-v-pulse-width = <0x2>;
  10596. qcom,mdss-dsi-h-left-border = <0x0>;
  10597. qcom,mdss-dsi-h-right-border = <0x0>;
  10598. qcom,mdss-dsi-v-top-border = <0x0>;
  10599. qcom,mdss-dsi-v-bottom-border = <0x0>;
  10600. qcom,mdss-dsi-bpp = <0x18>;
  10601. qcom,mdss-dsi-color-order = "rgb_swap_rgb";
  10602. qcom,mdss-dsi-underflow-color = <0xff>;
  10603. qcom,mdss-dsi-border-color = <0x0>;
  10604. qcom,mdss-dsi-on-command = [29 01 00 00 00 00 02 b0 00 29 01 00 00 00 00 02 d6 01 29 01 00 00 00 00 1b d3 1b 33 bb bb b3 33 33 33 33 00 01 00 00 d8 a0 05 2f 2f 33 33 72 12 8a 57 3d bc 05 01 00 00 10 00 02 29 00 05 01 00 00 78 00 02 11 00];
  10605. qcom,mdss-dsi-off-command = [29 01 00 00 00 00 02 b0 00 05 01 00 00 10 00 02 28 00 29 01 00 00 32 00 1b d3 13 33 bb b3 b3 33 33 33 33 00 01 00 00 d8 a0 05 2f 2f 33 33 72 12 8a 57 3d bc 05 01 00 00 78 00 02 10 00 29 01 00 00 00 00 02 b1 01];
  10606. qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
  10607. qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
  10608. qcom,mdss-dsi-panel-warm-command = [29 01 00 00 00 00 02 b0 00 29 01 00 00 00 00 02 d6 01 29 01 00 00 00 00 1f c7 00 0b 13 1c 2b 3a 44 56 3c 45 51 5f 68 6e 72 00 0b 13 1c 2b 3a 44 56 3c 45 51 5f 68 6e 72 29 01 00 00 00 00 14 c8 01 00 01 03 fc fc 00 00 ff 02 fd b9 00 00 fe 08 03 b7 00];
  10609. qcom,mdss-dsi-panel-cool-command = [29 01 00 00 00 00 02 b0 00 29 01 00 00 00 00 02 d6 01 29 01 00 00 00 00 1f c7 00 0d 13 1d 2d 3c 46 58 3f 48 55 63 6b 70 72 00 0d 13 1d 2d 3c 46 58 3f 48 55 63 6b 70 72 29 01 00 00 00 00 14 c8 01 00 03 01 fe de 00 00 01 01 fc cf 00 00 02 05 09 fc 00];
  10610. qcom,mdss-dsi-panel-nature-command = [29 01 00 00 00 00 02 b0 00 29 01 00 00 00 00 02 d6 01 29 01 00 00 00 00 1f c7 00 0d 13 1d 2d 3c 46 58 3f 48 55 63 6b 70 72 00 0d 13 1d 2d 3c 46 58 3f 48 55 63 6b 70 72 29 01 00 00 00 00 14 c8 01 00 03 01 fe fc 00 00 01 ff fe fc 00 00 01 06 0b fc 00];
  10611. qcom,mdss-dsi-panel-ce-std-command = [29 01 00 00 00 00 02 b0 00 29 01 00 00 00 00 02 d6 01 29 01 00 00 00 00 2c ca 1c fc fc fc 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00];
  10612. qcom,mdss-dsi-panel-ce-vivid-command = [29 00 00 00 00 00 02 b0 00 29 00 00 00 00 00 02 d6 01 29 01 00 00 00 00 2c ca 1d fc fc fc 00 d0 d0 90 00 90 90 90 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00];
  10613. qcom,mdss-dsi-panel-ce-bright-command = [29 00 00 00 00 00 02 b0 00 29 00 00 00 00 00 02 d6 01 29 01 00 00 00 00 2c ca 1d fc fc fc 40 c0 c0 7f 80 80 7f 80 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00];
  10614. qcom,mdss-dsi-panel-gamma-command-state = "dsi_lp_mode";
  10615. qcom,mdss-dsi-panel-ce-command-state = "dsi_lp_mode";
  10616. qcom,mdss-dsi-init-last;
  10617. qcom,mdss-dsi-h-sync-pulse = <0x1>;
  10618. qcom,mdss-dsi-traffic-mode = "burst_mode";
  10619. qcom,mdss-dsi-lane-map = "lane_map_0123";
  10620. qcom,mdss-dsi-bllp-eof-power-mode;
  10621. qcom,mdss-dsi-bllp-power-mode;
  10622. qcom,mdss-dsi-lane-0-state;
  10623. qcom,mdss-dsi-lane-1-state;
  10624. qcom,mdss-dsi-lane-2-state;
  10625. qcom,mdss-dsi-lane-3-state;
  10626. qcom,mdss-dsi-panel-timings = <0xe2362400 0x666a2838 0x2a030400>;
  10627. qcom,mdss-dsi-panel-timings-8996 = <0x231f0709 0x50304a0 0x231f0709 0x50304a0 0x231f0709 0x50304a0 0x231f0709 0x50304a0 0x23190808 0x50304a0>;
  10628. qcom,mdss-dsi-t-clk-post = <0x2>;
  10629. qcom,mdss-dsi-t-clk-pre = <0x2a>;
  10630. qcom,mdss-dsi-bl-min-level = <0x1>;
  10631. qcom,mdss-dsi-bl-max-level = <0xfff>;
  10632. qcom,mdss-dsi-dma-trigger = "trigger_sw";
  10633. qcom,mdss-dsi-mdp-trigger = "none";
  10634. qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
  10635. qcom,mdss-dsi-reset-sequence = <0x1 0xa 0x0 0xa 0x1 0x14>;
  10636. qcom,mdss-dsi-lp11-init;
  10637. qcom,mdss-dsi-init-delay-us = <0xc350>;
  10638. qcom,mdss-pan-physical-width-dimension = <0x3e>;
  10639. qcom,mdss-pan-physical-height-dimension = <0x6e>;
  10640. qcom,mdss-night-brightness = <0xb 0x1c 0x2d 0x3e>;
  10641. qcom,panel-supply-entries = <0x198>;
  10642. linux,phandle = <0x1a0>;
  10643. phandle = <0x1a0>;
  10644. };
  10645.  
  10646. qcom,mdss_dsi_sim_video {
  10647. qcom,mdss-dsi-panel-name = "Simulator video mode dsi panel";
  10648. qcom,mdss-dsi-panel-type = "dsi_video_mode";
  10649. qcom,mdss-dsi-panel-framerate = <0x3c>;
  10650. qcom,mdss-dsi-virtual-channel-id = <0x0>;
  10651. qcom,mdss-dsi-stream = <0x0>;
  10652. qcom,mdss-dsi-panel-width = <0x280>;
  10653. qcom,mdss-dsi-panel-height = <0x1e0>;
  10654. qcom,mdss-dsi-h-front-porch = <0x6>;
  10655. qcom,mdss-dsi-h-back-porch = <0x6>;
  10656. qcom,mdss-dsi-h-pulse-width = <0x2>;
  10657. qcom,mdss-dsi-h-sync-skew = <0x0>;
  10658. qcom,mdss-dsi-v-back-porch = <0x6>;
  10659. qcom,mdss-dsi-v-front-porch = <0x6>;
  10660. qcom,mdss-dsi-v-pulse-width = <0x2>;
  10661. qcom,mdss-dsi-h-left-border = <0x0>;
  10662. qcom,mdss-dsi-h-right-border = <0x0>;
  10663. qcom,mdss-dsi-v-top-border = <0x0>;
  10664. qcom,mdss-dsi-v-bottom-border = <0x0>;
  10665. qcom,mdss-dsi-bpp = <0x18>;
  10666. qcom,mdss-dsi-underflow-color = <0xff>;
  10667. qcom,mdss-dsi-border-color = <0x0>;
  10668. qcom,mdss-dsi-on-command = [32 01 00 00 00 00 02 00 00];
  10669. qcom,mdss-dsi-off-command = [22 01 00 00 00 00 02 00 00];
  10670. qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
  10671. qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
  10672. qcom,mdss-dsi-h-sync-pulse = <0x0>;
  10673. qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
  10674. qcom,mdss-dsi-bllp-eof-power-mode;
  10675. qcom,mdss-dsi-bllp-power-mode;
  10676. qcom,mdss-dsi-lane-0-state;
  10677. qcom,mdss-dsi-lane-1-state;
  10678. qcom,mdss-dsi-lane-2-state;
  10679. qcom,mdss-dsi-lane-3-state;
  10680. qcom,mdss-dsi-panel-timings = <0x0 0x0 0x0>;
  10681. qcom,mdss-dsi-t-clk-post = <0x4>;
  10682. qcom,mdss-dsi-t-clk-pre = <0x1b>;
  10683. qcom,mdss-dsi-dma-trigger = "trigger_sw";
  10684. qcom,mdss-dsi-mdp-trigger = "none";
  10685. qcom,mdss-dsi-reset-sequence = <0x1 0x0 0x0 0x0 0x1 0x0>;
  10686. qcom,panel-ack-disabled;
  10687. };
  10688.  
  10689. qcom,mdss_dsi_dual_sim_video {
  10690. qcom,mdss-dsi-panel-name = "Sim dual video mode dsi panel";
  10691. qcom,mdss-dsi-panel-type = "dsi_video_mode";
  10692. qcom,mdss-dsi-panel-framerate = <0x3c>;
  10693. qcom,mdss-dsi-virtual-channel-id = <0x0>;
  10694. qcom,mdss-dsi-stream = <0x0>;
  10695. qcom,mdss-dsi-panel-width = <0x500>;
  10696. qcom,mdss-dsi-panel-height = <0x5a0>;
  10697. qcom,mdss-dsi-h-front-porch = <0x78>;
  10698. qcom,mdss-dsi-h-back-porch = <0x2c>;
  10699. qcom,mdss-dsi-h-pulse-width = <0x10>;
  10700. qcom,mdss-dsi-h-sync-skew = <0x0>;
  10701. qcom,mdss-dsi-v-back-porch = <0x4>;
  10702. qcom,mdss-dsi-v-front-porch = <0x8>;
  10703. qcom,mdss-dsi-v-pulse-width = <0x4>;
  10704. qcom,mdss-dsi-h-left-border = <0x0>;
  10705. qcom,mdss-dsi-h-right-border = <0x0>;
  10706. qcom,mdss-dsi-v-top-border = <0x0>;
  10707. qcom,mdss-dsi-v-bottom-border = <0x0>;
  10708. qcom,mdss-dsi-bpp = <0x18>;
  10709. qcom,mdss-dsi-underflow-color = <0xff>;
  10710. qcom,mdss-dsi-border-color = <0x0>;
  10711. qcom,mdss-dsi-h-sync-pulse = <0x0>;
  10712. qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
  10713. qcom,mdss-dsi-bllp-eof-power-mode;
  10714. qcom,mdss-dsi-bllp-power-mode;
  10715. qcom,mdss-dsi-panel-broadcast-mode;
  10716. qcom,mdss-dsi-lane-0-state;
  10717. qcom,mdss-dsi-lane-1-state;
  10718. qcom,mdss-dsi-lane-2-state;
  10719. qcom,mdss-dsi-lane-3-state;
  10720. qcom,mdss-dsi-panel-timings = <0xcd322200 0x60642634 0x29030400>;
  10721. qcom,mdss-dsi-t-clk-post = <0x3>;
  10722. qcom,mdss-dsi-t-clk-pre = <0x27>;
  10723. qcom,mdss-dsi-bl-max-level = <0xfff>;
  10724. qcom,mdss-dsi-dma-trigger = "trigger_sw";
  10725. qcom,mdss-dsi-mdp-trigger = "none";
  10726. qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
  10727. qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00];
  10728. qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
  10729. qcom,mdss-dsi-reset-sequence = <0x1 0x14 0x0 0xc8 0x1 0x14>;
  10730. qcom,panel-ack-disabled;
  10731. };
  10732.  
  10733. qcom,mdss_dsi_sim_cmd {
  10734. qcom,mdss-dsi-panel-name = "Simulator cmd mode dsi panel";
  10735. qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
  10736. qcom,mdss-dsi-panel-framerate = <0x3c>;
  10737. qcom,mdss-dsi-virtual-channel-id = <0x0>;
  10738. qcom,mdss-dsi-stream = <0x0>;
  10739. qcom,mdss-dsi-panel-width = <0x438>;
  10740. qcom,mdss-dsi-panel-height = <0x780>;
  10741. qcom,mdss-dsi-h-front-porch = <0x60>;
  10742. qcom,mdss-dsi-h-back-porch = <0x40>;
  10743. qcom,mdss-dsi-h-pulse-width = <0x10>;
  10744. qcom,mdss-dsi-h-sync-skew = <0x0>;
  10745. qcom,mdss-dsi-v-back-porch = <0x10>;
  10746. qcom,mdss-dsi-v-front-porch = <0x4>;
  10747. qcom,mdss-dsi-v-pulse-width = <0x1>;
  10748. qcom,mdss-dsi-h-left-border = <0x0>;
  10749. qcom,mdss-dsi-h-right-border = <0x0>;
  10750. qcom,mdss-dsi-v-top-border = <0x0>;
  10751. qcom,mdss-dsi-v-bottom-border = <0x0>;
  10752. qcom,mdss-dsi-bpp = <0x18>;
  10753. qcom,mdss-dsi-color-order = "rgb_swap_rgb";
  10754. qcom,mdss-dsi-underflow-color = <0xff>;
  10755. qcom,mdss-dsi-border-color = <0x0>;
  10756. qcom,mdss-dsi-h-sync-pulse = <0x0>;
  10757. qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
  10758. qcom,mdss-dsi-bllp-eof-power-mode;
  10759. qcom,mdss-dsi-bllp-power-mode;
  10760. qcom,mdss-dsi-lane-0-state;
  10761. qcom,mdss-dsi-lane-1-state;
  10762. qcom,mdss-dsi-lane-2-state;
  10763. qcom,mdss-dsi-lane-3-state;
  10764. qcom,mdss-dsi-hor-line-idle = <0x0 0x28 0x100 0x28 0x78 0x80 0x78 0xf0 0x40>;
  10765. qcom,mdss-dsi-panel-timings = <0xcd322200 0x60642634 0x29030400>;
  10766. qcom,mdss-dsi-reset-sequence = <0x1 0xa 0x0 0xa 0x1 0xa>;
  10767. qcom,mdss-dsi-t-clk-post = <0x3>;
  10768. qcom,mdss-dsi-t-clk-pre = <0x27>;
  10769. qcom,mdss-dsi-bl-max-level = <0xfff>;
  10770. qcom,mdss-dsi-dma-trigger = "trigger_sw";
  10771. qcom,mdss-dsi-mdp-trigger = "none";
  10772. qcom,mdss-dsi-te-pin-select = <0x1>;
  10773. qcom,mdss-dsi-wr-mem-start = <0x2c>;
  10774. qcom,mdss-dsi-wr-mem-continue = <0x3c>;
  10775. qcom,mdss-dsi-te-dcs-command = <0x1>;
  10776. qcom,mdss-dsi-te-check-enable;
  10777. qcom,mdss-dsi-te-using-te-pin;
  10778. qcom,mdss-dsi-on-command = <0x29010000 0x2b0 0x3050100 0xa0001 0x150100 0xa0002 0x3a773901 0xa00 0x52a0000 0x4ff3901 0xa00 0x52b0000 0x59f1501 0xa00 0x2350039 0x100000a 0x34400 0x150100 0xa0002 0x51ff1501 0xa00 0x2532415 0x100000a 0x25500 0x5010000 0x78000111 0x5010000 0x10000129>;
  10779. qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
  10780. qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00];
  10781. qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
  10782. qcom,panel-ack-disabled;
  10783. };
  10784.  
  10785. qcom,mdss_dsi_dual_sim_cmd {
  10786. qcom,mdss-dsi-panel-name = "Sim dual cmd mode dsi panel";
  10787. qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
  10788. qcom,mdss-dsi-panel-framerate = <0x3c>;
  10789. qcom,mdss-dsi-virtual-channel-id = <0x0>;
  10790. qcom,mdss-dsi-stream = <0x0>;
  10791. qcom,mdss-dsi-panel-width = <0x500>;
  10792. qcom,mdss-dsi-panel-height = <0x5a0>;
  10793. qcom,mdss-dsi-h-front-porch = <0x78>;
  10794. qcom,mdss-dsi-h-back-porch = <0x2c>;
  10795. qcom,mdss-dsi-h-pulse-width = <0x10>;
  10796. qcom,mdss-dsi-h-sync-skew = <0x0>;
  10797. qcom,mdss-dsi-v-back-porch = <0x4>;
  10798. qcom,mdss-dsi-v-front-porch = <0x8>;
  10799. qcom,mdss-dsi-v-pulse-width = <0x4>;
  10800. qcom,mdss-dsi-h-left-border = <0x0>;
  10801. qcom,mdss-dsi-h-right-border = <0x0>;
  10802. qcom,mdss-dsi-v-top-border = <0x0>;
  10803. qcom,mdss-dsi-v-bottom-border = <0x0>;
  10804. qcom,mdss-dsi-bpp = <0x18>;
  10805. qcom,mdss-dsi-color-order = "rgb_swap_rgb";
  10806. qcom,mdss-dsi-underflow-color = <0xff>;
  10807. qcom,mdss-dsi-border-color = <0x0>;
  10808. qcom,mdss-dsi-h-sync-pulse = <0x0>;
  10809. qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
  10810. qcom,mdss-dsi-bllp-eof-power-mode;
  10811. qcom,mdss-dsi-bllp-power-mode;
  10812. qcom,cmd-sync-wait-broadcast;
  10813. qcom,mdss-dsi-lane-0-state;
  10814. qcom,mdss-dsi-lane-1-state;
  10815. qcom,mdss-dsi-lane-2-state;
  10816. qcom,mdss-dsi-lane-3-state;
  10817. qcom,mdss-dsi-hor-line-idle = <0x0 0x28 0x100 0x28 0x78 0x80 0x78 0xf0 0x40>;
  10818. qcom,mdss-dsi-panel-timings = <0xcd322200 0x60642634 0x29030400>;
  10819. qcom,mdss-dsi-reset-sequence = <0x1 0xa 0x0 0xa 0x1 0xa>;
  10820. qcom,mdss-dsi-t-clk-post = <0x3>;
  10821. qcom,mdss-dsi-t-clk-pre = <0x27>;
  10822. qcom,mdss-dsi-bl-max-level = <0xfff>;
  10823. qcom,mdss-dsi-dma-trigger = "trigger_sw";
  10824. qcom,mdss-dsi-mdp-trigger = "none";
  10825. qcom,mdss-dsi-te-pin-select = <0x1>;
  10826. qcom,mdss-dsi-wr-mem-start = <0x2c>;
  10827. qcom,mdss-dsi-wr-mem-continue = <0x3c>;
  10828. qcom,mdss-dsi-te-dcs-command = <0x1>;
  10829. qcom,mdss-dsi-te-check-enable;
  10830. qcom,mdss-dsi-te-using-te-pin;
  10831. qcom,mdss-dsi-on-command = <0x29010000 0x2b0 0x3050100 0xa0001 0x150100 0xa0002 0x3a773901 0xa00 0x52a0000 0x4ff3901 0xa00 0x52b0000 0x59f1501 0xa00 0x2350039 0x100000a 0x34400 0x150100 0xa0002 0x51ff1501 0xa00 0x2532415 0x100000a 0x25500 0x5010000 0x78000111 0x5010000 0x10000129>;
  10832. qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
  10833. qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00];
  10834. qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
  10835. qcom,panel-ack-disabled;
  10836. };
  10837.  
  10838. qcom,mdss_dsi_truly_1080p_video {
  10839. qcom,mdss-dsi-panel-name = "truly 1080p video mode dsi panel";
  10840. qcom,mdss-dsi-panel-type = "dsi_video_mode";
  10841. qcom,mdss-dsi-panel-framerate = <0x3c>;
  10842. qcom,mdss-dsi-virtual-channel-id = <0x0>;
  10843. qcom,mdss-dsi-stream = <0x0>;
  10844. qcom,mdss-dsi-panel-width = <0x438>;
  10845. qcom,mdss-dsi-panel-height = <0x780>;
  10846. qcom,mdss-dsi-h-front-porch = <0x60>;
  10847. qcom,mdss-dsi-h-back-porch = <0x40>;
  10848. qcom,mdss-dsi-h-pulse-width = <0x10>;
  10849. qcom,mdss-dsi-h-sync-skew = <0x0>;
  10850. qcom,mdss-dsi-v-back-porch = <0x10>;
  10851. qcom,mdss-dsi-v-front-porch = <0x4>;
  10852. qcom,mdss-dsi-v-pulse-width = <0x1>;
  10853. qcom,mdss-dsi-h-left-border = <0x0>;
  10854. qcom,mdss-dsi-h-right-border = <0x0>;
  10855. qcom,mdss-dsi-v-top-border = <0x0>;
  10856. qcom,mdss-dsi-v-bottom-border = <0x0>;
  10857. qcom,mdss-dsi-bpp = <0x18>;
  10858. qcom,mdss-dsi-underflow-color = <0xff>;
  10859. qcom,mdss-dsi-border-color = <0x0>;
  10860. qcom,mdss-dsi-h-sync-pulse = <0x0>;
  10861. qcom,mdss-dsi-traffic-mode = "burst_mode";
  10862. qcom,mdss-dsi-bllp-eof-power-mode;
  10863. qcom,mdss-dsi-bllp-power-mode;
  10864. qcom,mdss-dsi-lane-0-state;
  10865. qcom,mdss-dsi-lane-1-state;
  10866. qcom,mdss-dsi-lane-2-state;
  10867. qcom,mdss-dsi-lane-3-state;
  10868. qcom,mdss-dsi-panel-timings = <0xe6382600 0x686e2a3c 0x44030400>;
  10869. qcom,mdss-dsi-t-clk-post = <0x2>;
  10870. qcom,mdss-dsi-t-clk-pre = <0x2d>;
  10871. qcom,mdss-dsi-bl-min-level = <0x1>;
  10872. qcom,mdss-dsi-bl-max-level = <0xfff>;
  10873. qcom,mdss-dsi-dma-trigger = "trigger_sw";
  10874. qcom,mdss-dsi-mdp-trigger = "none";
  10875. qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 35 00 15 01 00 00 00 00 02 51 ff 15 01 00 00 00 00 02 53 2c 15 01 00 00 00 00 02 55 00 05 01 00 00 78 00 02 11 00 23 01 00 00 00 00 02 b0 00 29 01 00 00 00 00 07 b3 14 00 00 00 00 00 29 01 00 00 00 00 03 b6 3a d3 29 01 00 00 00 00 03 c0 00 00 29 01 00 00 00 00 23 c1 84 60 10 eb ff 6f ce ff ff 17 02 58 73 ae b1 20 c6 ff ff 1f f3 ff 5f 10 10 10 10 00 02 01 22 22 00 01 29 01 00 00 00 00 08 c2 31 f7 80 06 08 00 00 29 01 00 00 00 00 17 c4 70 00 00 00 00 04 00 00 00 0c 06 00 00 00 00 00 04 00 00 00 0c 06 29 01 00 00 00 00 29 c6 00 69 00 69 00 69 00 00 00 00 00 69 00 69 00 69 10 19 07 00 01 00 69 00 69 00 69 00 00 00 00 00 69 00 69 00 69 10 19 07 29 01 00 00 00 00 0a cb 31 fc 3f 8c 00 00 00 00 c0 23 01 00 00 00 00 02 cc 0b 29 01 00 00 00 00 0b d0 11 81 bb 1e 1e 4c 19 19 0c 00 29 01 00 00 00 00 1a d3 1b 33 bb bb b3 33 33 33 00 01 00 a0 d8 a0 0d 4e 4e 33 3b 22 72 07 3d bf 33 29 01 00 00 00 00 08 d5 06 00 00 01 51 01 32 29 01 00 00 00 00 1f c7 01 0a 11 18 26 33 3e 50 38 42 52 60 67 6e 77 01 0a 11 18 26 33 3e 50 38 42 52 60 67 6e 77 29 01 00 00 14 00 14 c8 01 00 00 00 00 fc 00 00 00 00 00 fc 00 00 00 00 00 fc 00 05 01 00 00 14 00 02 29 00];
  10876. qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00];
  10877. qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
  10878. qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
  10879. qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
  10880. qcom,mdss-dsi-reset-sequence = <0x1 0xa 0x0 0xa 0x1 0xa>;
  10881. qcom,mdss-dsi-tx-eot-append;
  10882. qcom,mdss-dsi-post-init-delay = <0x1>;
  10883. qcom,mdss-dsi-panel-timings-8996 = <0x231e0809 0x50304a0 0x231e0809 0x50304a0 0x231e0809 0x50304a0 0x231e0809 0x50304a0 0x231a0809 0x50304a0>;
  10884. };
  10885.  
  10886. qcom,mdss_dsi_truly_1080p_cmd {
  10887. qcom,mdss-dsi-panel-name = "truly 1080p cmd mode dsi panel";
  10888. qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
  10889. qcom,mdss-dsi-panel-framerate = <0x3c>;
  10890. qcom,mdss-dsi-virtual-channel-id = <0x0>;
  10891. qcom,mdss-dsi-stream = <0x0>;
  10892. qcom,mdss-dsi-panel-width = <0x438>;
  10893. qcom,mdss-dsi-panel-height = <0x780>;
  10894. qcom,mdss-dsi-h-front-porch = <0x60>;
  10895. qcom,mdss-dsi-h-back-porch = <0x40>;
  10896. qcom,mdss-dsi-h-pulse-width = <0x10>;
  10897. qcom,mdss-dsi-h-sync-skew = <0x0>;
  10898. qcom,mdss-dsi-v-back-porch = <0x10>;
  10899. qcom,mdss-dsi-v-front-porch = <0x4>;
  10900. qcom,mdss-dsi-v-pulse-width = <0x1>;
  10901. qcom,mdss-dsi-h-left-border = <0x0>;
  10902. qcom,mdss-dsi-h-right-border = <0x0>;
  10903. qcom,mdss-dsi-v-top-border = <0x0>;
  10904. qcom,mdss-dsi-v-bottom-border = <0x0>;
  10905. qcom,mdss-dsi-bpp = <0x18>;
  10906. qcom,mdss-dsi-underflow-color = <0xff>;
  10907. qcom,mdss-dsi-border-color = <0x0>;
  10908. qcom,mdss-dsi-te-pin-select = <0x1>;
  10909. qcom,mdss-dsi-te-dcs-command = <0x1>;
  10910. qcom,mdss-dsi-te-check-enable;
  10911. qcom,mdss-dsi-te-using-te-pin;
  10912. qcom,mdss-dsi-h-sync-pulse = <0x0>;
  10913. qcom,mdss-dsi-traffic-mode = "burst_mode";
  10914. qcom,mdss-dsi-bllp-eof-power-mode;
  10915. qcom,mdss-dsi-bllp-power-mode;
  10916. qcom,mdss-dsi-lane-0-state;
  10917. qcom,mdss-dsi-lane-1-state;
  10918. qcom,mdss-dsi-lane-2-state;
  10919. qcom,mdss-dsi-lane-3-state;
  10920. qcom,mdss-dsi-panel-timings = <0xe6382600 0x686e2a3c 0x44030400>;
  10921. qcom,mdss-dsi-t-clk-post = <0x2>;
  10922. qcom,mdss-dsi-t-clk-pre = <0x2d>;
  10923. qcom,mdss-dsi-tx-eot-append;
  10924. qcom,mdss-dsi-dma-trigger = "trigger_sw";
  10925. qcom,mdss-dsi-mdp-trigger = "none";
  10926. qcom,mdss-dsi-on-command = [23 01 00 00 00 00 02 d6 01 15 01 00 00 00 00 02 35 00 15 01 00 00 00 00 02 51 ff 15 01 00 00 00 00 02 53 2c 15 01 00 00 00 00 02 55 00 05 01 00 00 78 00 02 11 00 23 01 00 00 00 00 02 b0 04 29 01 00 00 00 00 07 b3 04 00 00 00 00 00 29 01 00 00 00 00 03 b6 3a d3 29 01 00 00 00 00 03 c0 00 00 29 01 00 00 00 00 23 c1 84 60 10 eb ff 6f ce ff ff 17 02 58 73 ae b1 20 c6 ff ff 1f f3 ff 5f 10 10 10 10 00 02 01 22 22 00 01 29 01 00 00 00 00 08 c2 31 f7 80 06 08 00 00 29 01 00 00 00 00 17 c4 70 00 00 00 00 04 00 00 00 0c 06 00 00 00 00 00 04 00 00 00 0c 06 29 01 00 00 00 00 29 c6 78 69 00 69 00 69 00 00 00 00 00 69 00 69 00 69 10 19 07 00 78 00 69 00 69 00 69 00 00 00 00 00 69 00 69 00 69 10 19 07 29 01 00 00 00 00 0a cb 31 fc 3f 8c 00 00 00 00 c0 23 01 00 00 00 00 02 cc 0b 29 01 00 00 00 00 0b d0 11 81 bb 1e 1e 4c 19 19 0c 00 29 01 00 00 00 00 1a d3 1b 33 bb bb b3 33 33 33 00 01 00 a0 d8 a0 0d 4e 4e 33 3b 22 72 07 3d bf 33 29 01 00 00 00 00 08 d5 06 00 00 01 51 01 32 29 01 00 00 00 00 1f c7 01 0a 11 18 26 33 3e 50 38 42 52 60 67 6e 77 01 0a 11 18 26 33 3e 50 38 42 52 60 67 6e 77 29 01 00 00 14 00 14 c8 01 00 00 00 00 fc 00 00 00 00 00 fc 00 00 00 00 00 fc 00 05 01 00 00 14 00 02 29 00];
  10927. qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00];
  10928. qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
  10929. qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
  10930. qcom,mdss-dsi-bl-min-level = <0x1>;
  10931. qcom,mdss-dsi-bl-max-level = <0xfff>;
  10932. qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
  10933. qcom,mdss-dsi-reset-sequence = <0x1 0xa 0x0 0xa 0x1 0xa>;
  10934. qcom,mdss-dsi-post-init-delay = <0x1>;
  10935. qcom,mdss-dsi-panel-timings-8996 = <0x231e0809 0x50304a0 0x231e0809 0x50304a0 0x231e0809 0x50304a0 0x231e0809 0x50304a0 0x231a0809 0x50304a0>;
  10936. };
  10937.  
  10938. qcom,mdss_dsi_adv7533_1080p {
  10939. label = "adv7533 1080p video mode dsi panel";
  10940. qcom,mdss-dsi-panel-name = "dsi_adv7533_1080p";
  10941. qcom,mdss-dsi-panel-controller = <0x197>;
  10942. qcom,mdss-dsi-panel-type = "dsi_video_mode";
  10943. qcom,mdss-dsi-panel-destination = "display_1";
  10944. qcom,mdss-dsi-panel-framerate = <0x3c>;
  10945. qcom,mdss-dsi-virtual-channel-id = <0x0>;
  10946. qcom,mdss-dsi-stream = <0x0>;
  10947. qcom,mdss-dsi-panel-width = <0x780>;
  10948. qcom,mdss-dsi-panel-height = <0x438>;
  10949. qcom,mdss-dsi-h-front-porch = <0x58>;
  10950. qcom,mdss-dsi-h-back-porch = <0x94>;
  10951. qcom,mdss-dsi-h-pulse-width = <0x2c>;
  10952. qcom,mdss-dsi-h-sync-skew = <0x0>;
  10953. qcom,mdss-dsi-v-back-porch = <0x24>;
  10954. qcom,mdss-dsi-v-front-porch = <0x4>;
  10955. qcom,mdss-dsi-v-pulse-width = <0x5>;
  10956. qcom,mdss-dsi-h-left-border = <0x0>;
  10957. qcom,mdss-dsi-h-right-border = <0x0>;
  10958. qcom,mdss-dsi-v-top-border = <0x0>;
  10959. qcom,mdss-dsi-v-bottom-border = <0x0>;
  10960. qcom,mdss-dsi-bpp = <0x18>;
  10961. qcom,mdss-dsi-underflow-color = <0xff>;
  10962. qcom,mdss-dsi-border-color = <0x0>;
  10963. qcom,mdss-dsi-on-command = [05 01 00 00 c8 00 02 11 00 05 01 00 00 0a 00 02 29 00];
  10964. qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00 05 01 00 00 00 00 02 10 00];
  10965. qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
  10966. qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
  10967. qcom,mdss-dsi-h-sync-pulse = <0x1>;
  10968. qcom,mdss-dsi-traffic-mode = "non_burst_sync_pulse";
  10969. qcom,mdss-dsi-bllp-eof-power-mode;
  10970. qcom,mdss-dsi-bllp-power-mode;
  10971. qcom,mdss-dsi-lane-0-state;
  10972. qcom,mdss-dsi-lane-1-state;
  10973. qcom,mdss-dsi-lane-2-state;
  10974. qcom,mdss-dsi-lane-3-state;
  10975. qcom,mdss-dsi-panel-timings = <0xe6382600 0x686c2a3a 0x2c030400>;
  10976. qcom,mdss-dsi-t-clk-post = <0x2>;
  10977. qcom,mdss-dsi-t-clk-pre = <0x2b>;
  10978. qcom,mdss-dsi-bl-min-level = <0x1>;
  10979. qcom,mdss-dsi-bl-max-level = <0xfff>;
  10980. qcom,mdss-dsi-dma-trigger = "trigger_sw";
  10981. qcom,mdss-dsi-mdp-trigger = "none";
  10982. qcom,mdss-dsi-reset-sequence = <0x1 0x14 0x0 0x1 0x1 0x14>;
  10983. qcom,mdss-pan-physical-width-dimension = <0xa0>;
  10984. qcom,mdss-pan-physical-height-dimension = <0x5a>;
  10985. qcom,mdss-dsi-force-clock-lane-hs;
  10986. qcom,mdss-dsi-always-on;
  10987. qcom,mdss-dsi-panel-timings-8996 = <0x241f0809 0x50304a0 0x241f0809 0x50304a0 0x241f0809 0x50304a0 0x241f0809 0x50304a0 0x241b0809 0x50304a0>;
  10988. qcom,dba-panel;
  10989. qcom,bridge-name = "adv7533";
  10990. };
  10991.  
  10992. qcom,mdss_dsi_adv7533_720p {
  10993. label = "adv7533 720p video mode dsi panel";
  10994. qcom,mdss-dsi-panel-name = "dsi_adv7533_720p";
  10995. qcom,mdss-dsi-panel-controller = <0x197>;
  10996. qcom,mdss-dsi-panel-type = "dsi_video_mode";
  10997. qcom,mdss-dsi-panel-destination = "display_1";
  10998. qcom,mdss-dsi-panel-framerate = <0x3c>;
  10999. qcom,mdss-dsi-virtual-channel-id = <0x0>;
  11000. qcom,mdss-dsi-stream = <0x0>;
  11001. qcom,mdss-dsi-panel-width = <0x500>;
  11002. qcom,mdss-dsi-panel-height = <0x2d0>;
  11003. qcom,mdss-dsi-h-front-porch = <0x6e>;
  11004. qcom,mdss-dsi-h-back-porch = <0xdc>;
  11005. qcom,mdss-dsi-h-pulse-width = <0x28>;
  11006. qcom,mdss-dsi-h-sync-skew = <0x0>;
  11007. qcom,mdss-dsi-v-back-porch = <0x14>;
  11008. qcom,mdss-dsi-v-front-porch = <0x5>;
  11009. qcom,mdss-dsi-v-pulse-width = <0x5>;
  11010. qcom,mdss-dsi-h-left-border = <0x0>;
  11011. qcom,mdss-dsi-h-right-border = <0x0>;
  11012. qcom,mdss-dsi-v-top-border = <0x0>;
  11013. qcom,mdss-dsi-v-bottom-border = <0x0>;
  11014. qcom,mdss-dsi-bpp = <0x18>;
  11015. qcom,mdss-dsi-underflow-color = <0xff>;
  11016. qcom,mdss-dsi-border-color = <0x0>;
  11017. qcom,mdss-dsi-on-command = [05 01 00 00 c8 00 02 11 00 05 01 00 00 0a 00 02 29 00];
  11018. qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00 05 01 00 00 00 00 02 10 00];
  11019. qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
  11020. qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
  11021. qcom,mdss-dsi-h-sync-pulse = <0x1>;
  11022. qcom,mdss-dsi-traffic-mode = "non_burst_sync_pulse";
  11023. qcom,mdss-dsi-bllp-eof-power-mode;
  11024. qcom,mdss-dsi-bllp-power-mode;
  11025. qcom,mdss-dsi-lane-0-state;
  11026. qcom,mdss-dsi-lane-1-state;
  11027. qcom,mdss-dsi-lane-2-state;
  11028. qcom,mdss-dsi-panel-timings = <0xa4241800 0x4e521c28 0x1c030400>;
  11029. qcom,mdss-dsi-t-clk-post = <0x3>;
  11030. qcom,mdss-dsi-t-clk-pre = <0x20>;
  11031. qcom,mdss-dsi-bl-min-level = <0x1>;
  11032. qcom,mdss-dsi-bl-max-level = <0xfff>;
  11033. qcom,mdss-dsi-dma-trigger = "trigger_sw";
  11034. qcom,mdss-dsi-mdp-trigger = "none";
  11035. qcom,mdss-dsi-reset-sequence = <0x1 0x14 0x0 0x1 0x1 0x14>;
  11036. qcom,mdss-pan-physical-width-dimension = <0xa0>;
  11037. qcom,mdss-pan-physical-height-dimension = <0x5a>;
  11038. qcom,mdss-dsi-force-clock-lane-hs;
  11039. qcom,mdss-dsi-always-on;
  11040. qcom,mdss-dsi-panel-timings-8996 = <0x1e1b0406 0x20304a0 0x1e1b0406 0x20304a0 0x1e1b0406 0x20304a0 0x1e1b0406 0x20304a0 0x1e0e0405 0x20304a0>;
  11041. qcom,dba-panel;
  11042. qcom,bridge-name = "adv7533";
  11043. };
  11044.  
  11045. qcom,mdss_dsi_r69006_1080p_video {
  11046. qcom,mdss-dsi-panel-name = "r69006 1080p video mode dsi panel";
  11047. qcom,mdss-dsi-panel-type = "dsi_video_mode";
  11048. qcom,mdss-dsi-panel-framerate = <0x3c>;
  11049. qcom,mdss-dsi-virtual-channel-id = <0x0>;
  11050. qcom,mdss-dsi-stream = <0x0>;
  11051. qcom,mdss-dsi-panel-width = <0x438>;
  11052. qcom,mdss-dsi-panel-height = <0x780>;
  11053. qcom,mdss-dsi-h-front-porch = <0x64>;
  11054. qcom,mdss-dsi-h-back-porch = <0x52>;
  11055. qcom,mdss-dsi-h-pulse-width = <0x14>;
  11056. qcom,mdss-dsi-h-sync-skew = <0x0>;
  11057. qcom,mdss-dsi-v-back-porch = <0x9>;
  11058. qcom,mdss-dsi-v-front-porch = <0x3>;
  11059. qcom,mdss-dsi-v-pulse-width = <0xf>;
  11060. qcom,mdss-dsi-h-left-border = <0x0>;
  11061. qcom,mdss-dsi-h-right-border = <0x0>;
  11062. qcom,mdss-dsi-v-top-border = <0x0>;
  11063. qcom,mdss-dsi-v-bottom-border = <0x0>;
  11064. qcom,mdss-dsi-bpp = <0x18>;
  11065. qcom,mdss-dsi-underflow-color = <0xff>;
  11066. qcom,mdss-dsi-border-color = <0x0>;
  11067. qcom,mdss-dsi-on-command = [23 01 00 00 00 00 02 b0 00 29 01 00 00 00 00 06 b3 05 10 00 00 00 29 01 00 00 00 00 03 b4 0c 00 29 01 00 00 00 00 04 b6 3b c3 00 23 01 00 00 00 00 02 c0 00 15 01 00 00 00 00 02 36 98 23 01 00 00 00 00 02 cc 04 29 01 00 00 00 00 20 c1 84 00 10 ef 8b f1 ff ff df 9c c5 9a 73 8d ad 63 fe ff ff cb f8 01 00 aa 40 00 c2 01 08 00 01 29 01 00 00 00 00 0a cb 0d fe 1f 2c 00 00 00 00 00 29 01 00 00 00 00 0b c2 01 f7 80 04 63 00 60 00 01 30 29 01 00 00 00 00 07 c3 55 01 00 01 00 00 29 01 00 00 00 00 12 c4 70 00 00 00 00 00 00 00 00 02 01 00 05 01 00 00 00 29 01 00 00 00 00 0f c6 59 07 4a 07 4a 01 0e 01 02 01 02 09 15 07 29 01 00 00 00 00 1f c7 00 30 32 34 42 4e 56 62 44 4a 54 62 6b 73 7f 08 30 32 34 42 4e 56 62 44 4a 54 62 6b 73 7f 29 01 00 00 00 00 14 c8 00 00 00 00 00 fc 00 00 00 00 00 fc 00 00 00 00 00 fc 00 29 01 00 00 00 00 09 c9 1f 68 1f 68 4c 4c c4 11 29 01 00 00 00 00 11 d0 33 01 91 0b d9 19 19 00 00 00 19 99 00 00 00 00 29 01 00 00 00 00 1d d3 1b 3b bb ad a5 33 33 33 00 80 ad a8 6f 6f 33 33 33 f7 f2 1f 7d 7c ff 0f 99 00 ff ff 29 01 00 00 00 00 04 d4 57 33 03 29 01 00 00 00 00 0c d5 66 00 00 01 27 01 27 00 6d 00 6d 23 01 00 00 00 00 02 d6 81 05 01 00 00 78 00 02 11 00 05 01 00 00 78 00 02 29 00];
  11068. qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 96 00 02 10 00];
  11069. qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
  11070. qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
  11071. qcom,mdss-dsi-h-sync-pulse = <0x1>;
  11072. qcom,mdss-dsi-traffic-mode = "burst_mode";
  11073. qcom,mdss-dsi-bllp-eof-power-mode;
  11074. qcom,mdss-dsi-bllp-power-mode;
  11075. qcom,mdss-dsi-lane-0-state;
  11076. qcom,mdss-dsi-lane-1-state;
  11077. qcom,mdss-dsi-lane-2-state;
  11078. qcom,mdss-dsi-lane-3-state;
  11079. qcom,mdss-dsi-panel-timings = <0x7d251d00 0x37332227 0x1e030400>;
  11080. qcom,mdss-dsi-t-clk-post = <0x20>;
  11081. qcom,mdss-dsi-t-clk-pre = <0x2c>;
  11082. qcom,mdss-dsi-bl-min-level = <0x1>;
  11083. qcom,mdss-dsi-bl-max-level = <0xfff>;
  11084. qcom,mdss-dsi-dma-trigger = "trigger_sw";
  11085. qcom,mdss-dsi-mdp-trigger = "none";
  11086. qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
  11087. qcom,mdss-dsi-reset-sequence = <0x1 0x14 0x0 0x2 0x1 0x14>;
  11088. qcom,mdss-dsi-panel-status-command = <0x6010001 0x500010a>;
  11089. qcom,mdss-dsi-panel-status-command-mode = "dsi_lp_mode";
  11090. qcom,mdss-dsi-panel-status-check-mode = "reg_read";
  11091. qcom,mdss-dsi-panel-status-read-length = <0x1>;
  11092. qcom,mdss-dsi-panel-status-value = <0x1c>;
  11093. qcom,mdss-dsi-panel-max-error-count = <0x3>;
  11094. qcom,mdss-dsi-panel-timings-8996 = <0x241f0809 0x50304a0 0x241f0809 0x50304a0 0x241f0809 0x50304a0 0x241f0809 0x50304a0 0x241b0809 0x50304a0>;
  11095. qcom,panel-supply-entries = <0x198>;
  11096. };
  11097.  
  11098. qcom,mdss_dsi_r69006_1080p_cmd {
  11099. qcom,mdss-dsi-panel-name = "r69006 1080p cmd mode dsi panel";
  11100. qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
  11101. qcom,mdss-dsi-panel-framerate = <0x3c>;
  11102. qcom,mdss-dsi-virtual-channel-id = <0x0>;
  11103. qcom,mdss-dsi-stream = <0x0>;
  11104. qcom,mdss-dsi-panel-width = <0x438>;
  11105. qcom,mdss-dsi-panel-height = <0x780>;
  11106. qcom,mdss-dsi-h-front-porch = <0x64>;
  11107. qcom,mdss-dsi-h-back-porch = <0x52>;
  11108. qcom,mdss-dsi-h-pulse-width = <0x14>;
  11109. qcom,mdss-dsi-h-sync-skew = <0x0>;
  11110. qcom,mdss-dsi-v-back-porch = <0x9>;
  11111. qcom,mdss-dsi-v-front-porch = <0x3>;
  11112. qcom,mdss-dsi-v-pulse-width = <0xf>;
  11113. qcom,mdss-dsi-h-left-border = <0x0>;
  11114. qcom,mdss-dsi-h-right-border = <0x0>;
  11115. qcom,mdss-dsi-v-top-border = <0x0>;
  11116. qcom,mdss-dsi-v-bottom-border = <0x0>;
  11117. qcom,mdss-dsi-bpp = <0x18>;
  11118. qcom,mdss-dsi-underflow-color = <0xff>;
  11119. qcom,mdss-dsi-border-color = <0x0>;
  11120. qcom,mdss-dsi-on-command = [23 01 00 00 00 00 02 b0 00 29 01 00 00 00 00 06 b3 04 10 00 00 00 29 01 00 00 00 00 03 b4 0c 00 29 01 00 00 00 00 04 b6 3b d3 00 23 01 00 00 00 00 02 c0 00 15 01 00 00 00 00 02 36 98 23 01 00 00 00 00 02 cc 04 29 01 00 00 00 00 20 c1 84 00 10 ef 8b f1 ff ff df 9c c5 9a 73 8d ad 63 fe ff ff cb f8 01 00 aa 40 02 c2 01 08 00 01 29 01 00 00 00 00 0a cb 0d fe 1f 2c 00 00 00 00 00 29 01 00 00 00 00 0b c2 01 f7 80 04 63 00 60 00 01 30 29 01 00 00 00 00 07 c3 55 01 00 01 00 00 29 01 00 00 00 00 12 c4 70 00 00 00 00 00 00 00 00 02 01 00 05 01 00 00 00 29 01 00 00 00 00 0f c6 57 07 4a 07 4a 01 0e 01 02 01 02 09 15 07 29 01 00 00 00 00 1f c7 00 06 0c 16 27 35 3f 4d 33 3c 49 5b 64 66 67 00 06 0c 16 27 35 3f 4d 33 3c 49 5b 64 66 67 29 01 00 00 00 00 14 c8 00 00 fe 01 08 e7 00 00 fd 02 03 a8 00 00 fc e7 e9 c9 00 29 01 00 00 00 00 09 c9 1f 68 1f 68 4c 4c c4 11 29 01 00 00 00 00 11 d0 11 01 91 0b d9 19 19 00 00 00 19 99 00 00 00 00 29 01 00 00 00 00 1d d3 1b 3b bb ad a5 33 33 33 00 80 ad a8 37 33 33 33 33 f7 f2 1f 7d 7c ff 0f 99 00 ff ff 29 01 00 00 00 00 04 d4 57 33 03 29 01 00 00 00 00 0c d5 66 00 00 01 32 01 32 00 0b 00 0b 29 01 00 00 00 00 02 be 04 29 01 00 00 00 00 11 cf 40 10 00 00 00 00 32 00 00 00 00 00 00 00 00 00 29 01 00 00 00 00 06 de 00 00 3f ff 10 29 01 00 00 00 00 02 e9 00 29 01 00 00 00 00 02 f2 00 23 01 00 00 00 00 02 d6 01 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 51 ff 39 01 00 00 00 00 02 53 2c 39 01 00 00 00 00 02 55 00 05 01 00 00 78 00 02 11 00 05 01 00 00 14 00 02 29 00];
  11121. qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00];
  11122. qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
  11123. qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
  11124. qcom,mdss-dsi-traffic-mode = "burst_mode";
  11125. qcom,mdss-dsi-bllp-eof-power-mode;
  11126. qcom,mdss-dsi-bllp-power-mode;
  11127. qcom,mdss-dsi-lane-0-state;
  11128. qcom,mdss-dsi-lane-1-state;
  11129. qcom,mdss-dsi-lane-2-state;
  11130. qcom,mdss-dsi-lane-3-state;
  11131. qcom,mdss-dsi-te-pin-select = <0x1>;
  11132. qcom,mdss-dsi-wr-mem-start = <0x2c>;
  11133. qcom,mdss-dsi-wr-mem-continue = <0x3c>;
  11134. qcom,mdss-dsi-te-dcs-command = <0x1>;
  11135. qcom,mdss-dsi-te-check-enable;
  11136. qcom,mdss-dsi-te-using-te-pin;
  11137. qcom,mdss-dsi-panel-timings = <0x6e3f3600 0x5a4f3841 0x54030400>;
  11138. qcom,mdss-dsi-t-clk-post = <0x1e>;
  11139. qcom,mdss-dsi-t-clk-pre = <0x30>;
  11140. qcom,mdss-dsi-bl-min-level = <0x1>;
  11141. qcom,mdss-dsi-bl-max-level = <0xfff>;
  11142. qcom,mdss-dsi-dma-trigger = "trigger_sw";
  11143. qcom,mdss-dsi-mdp-trigger = "none";
  11144. qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
  11145. qcom,mdss-dsi-reset-sequence = <0x1 0xa 0x0 0xa 0x1 0xa>;
  11146. qcom,mdss-dsi-panel-status-command = <0x6010001 0x500010a>;
  11147. qcom,mdss-dsi-panel-status-command-mode = "dsi_lp_mode";
  11148. qcom,mdss-dsi-panel-status-check-mode = "reg_read";
  11149. qcom,mdss-dsi-panel-status-read-length = <0x1>;
  11150. qcom,mdss-dsi-panel-status-value = <0x1c>;
  11151. qcom,mdss-dsi-panel-max-error-count = <0x3>;
  11152. qcom,mdss-dsi-rx-eot-ignore;
  11153. qcom,mdss-dsi-tx-eot-append;
  11154. qcom,mdss-dsi-panel-timings-8996 = <0x241f0809 0x50304a0 0x241f0809 0x50304a0 0x241f0809 0x50304a0 0x241f0809 0x50304a0 0x241b0809 0x50304a0>;
  11155. qcom,panel-supply-entries = <0x198>;
  11156. };
  11157.  
  11158. qcom,mdss_dsi_truly_wuxga_video {
  11159. qcom,mdss-dsi-panel-name = "truly wuxga video mode dsi panel";
  11160. qcom,mdss-dsi-panel-type = "dsi_video_mode";
  11161. qcom,mdss-dsi-panel-framerate = <0x3c>;
  11162. qcom,mdss-dsi-virtual-channel-id = <0x0>;
  11163. qcom,mdss-dsi-stream = <0x0>;
  11164. qcom,mdss-dsi-panel-width = <0x780>;
  11165. qcom,mdss-dsi-panel-height = <0x4b0>;
  11166. qcom,mdss-dsi-h-front-porch = <0x60>;
  11167. qcom,mdss-dsi-h-back-porch = <0x40>;
  11168. qcom,mdss-dsi-h-pulse-width = <0x10>;
  11169. qcom,mdss-dsi-h-sync-skew = <0x0>;
  11170. qcom,mdss-dsi-v-back-porch = <0x10>;
  11171. qcom,mdss-dsi-v-front-porch = <0x4>;
  11172. qcom,mdss-dsi-v-pulse-width = <0x1>;
  11173. qcom,mdss-dsi-h-left-border = <0x0>;
  11174. qcom,mdss-dsi-h-right-border = <0x0>;
  11175. qcom,mdss-dsi-v-top-border = <0x0>;
  11176. qcom,mdss-dsi-v-bottom-border = <0x0>;
  11177. qcom,mdss-dsi-bpp = <0x18>;
  11178. qcom,mdss-dsi-underflow-color = <0xff>;
  11179. qcom,mdss-dsi-border-color = <0x0>;
  11180. qcom,mdss-dsi-h-sync-pulse = <0x0>;
  11181. qcom,mdss-dsi-traffic-mode = "burst_mode";
  11182. qcom,mdss-dsi-bllp-eof-power-mode;
  11183. qcom,mdss-dsi-bllp-power-mode;
  11184. qcom,mdss-dsi-lane-0-state;
  11185. qcom,mdss-dsi-lane-1-state;
  11186. qcom,mdss-dsi-lane-2-state;
  11187. qcom,mdss-dsi-lane-3-state;
  11188. qcom,mdss-dsi-panel-timings = <0xf33a2600 0x6c6e2c3e 0x2f030400>;
  11189. qcom,mdss-dsi-t-clk-post = <0x2>;
  11190. qcom,mdss-dsi-t-clk-pre = <0x2d>;
  11191. qcom,mdss-dsi-bl-min-level = <0x1>;
  11192. qcom,mdss-dsi-bl-max-level = <0xfff>;
  11193. qcom,mdss-dsi-dma-trigger = "trigger_sw";
  11194. qcom,mdss-dsi-mdp-trigger = "none";
  11195. qcom,mdss-dsi-on-command = [32 01 00 00 00 00 02 00 00];
  11196. qcom,mdss-dsi-off-command = [22 01 00 00 00 00 02 00 00];
  11197. qcom,mdss-dsi-on-command-state = "dsi_hs_mode";
  11198. qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
  11199. qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
  11200. qcom,mdss-dsi-reset-sequence = <0x1 0xc8 0x0 0xc8 0x1 0xc8>;
  11201. qcom,mdss-dsi-panel-timings-8996 = <0x241f0809 0x50304a0 0x241f0809 0x50304a0 0x241f0809 0x50304a0 0x241f0809 0x50304a0 0x241c0809 0x50304a0>;
  11202. };
  11203. };
  11204.  
  11205. qcom,mdss_dsi@0 {
  11206. compatible = "qcom,mdss-dsi";
  11207. hw-config = "single_dsi";
  11208. #address-cells = <0x1>;
  11209. #size-cells = <0x1>;
  11210. gdsc-supply = <0x178>;
  11211. vdda-supply = <0x179>;
  11212. vcca-supply = <0x12d>;
  11213. qcom,msm-bus,name = "mdss_dsi";
  11214. qcom,msm-bus,num-cases = <0x2>;
  11215. qcom,msm-bus,num-paths = <0x1>;
  11216. qcom,msm-bus,vectors-KBps = <0x16 0x200 0x0 0x0 0x16 0x200 0x0 0x3e8>;
  11217. ranges = <0x1a94000 0x1a94000 0x400 0x1a94400 0x1a94400 0x588 0x193e000 0x193e000 0x30 0x1a96000 0x1a96000 0x400 0x1a96400 0x1a96400 0x588 0x193e000 0x193e000 0x30>;
  11218. clocks = <0x195 0x588460a4 0x37 0xbfb92ed3 0x37 0x668f51de 0x195 0xfb32f31e 0x195 0x585ef6d4 0x195 0x87c1612 0x195 0x8067c5a3>;
  11219. clock-names = "mdp_core_clk", "iface_clk", "bus_clk", "ext_byte0_clk", "ext_byte1_clk", "ext_pixel0_clk", "ext_pixel1_clk";
  11220. qcom,mmss-ulp-clamp-ctrl-offset = <0x20>;
  11221. qcom,mmss-phyreset-ctrl-offset = <0x24>;
  11222. qcom,mdss-fb-map-prim = <0x199>;
  11223. qcom,mdss-fb-map-sec = <0x19a>;
  11224.  
  11225. qcom,core-supply-entries {
  11226. #address-cells = <0x1>;
  11227. #size-cells = <0x0>;
  11228.  
  11229. qcom,core-supply-entry@0 {
  11230. reg = <0x0>;
  11231. qcom,supply-name = "gdsc";
  11232. qcom,supply-min-voltage = <0x0>;
  11233. qcom,supply-max-voltage = <0x0>;
  11234. qcom,supply-enable-load = <0x0>;
  11235. qcom,supply-disable-load = <0x0>;
  11236. };
  11237. };
  11238.  
  11239. qcom,ctrl-supply-entries {
  11240. #address-cells = <0x1>;
  11241. #size-cells = <0x0>;
  11242.  
  11243. qcom,ctrl-supply-entry@0 {
  11244. reg = <0x0>;
  11245. qcom,supply-name = "vdda";
  11246. qcom,supply-min-voltage = <0x12b128>;
  11247. qcom,supply-max-voltage = <0x12b128>;
  11248. qcom,supply-enable-load = <0x46f0>;
  11249. qcom,supply-disable-load = <0x1>;
  11250. };
  11251. };
  11252.  
  11253. qcom,phy-supply-entries {
  11254. #address-cells = <0x1>;
  11255. #size-cells = <0x0>;
  11256.  
  11257. qcom,phy-supply-entry@0 {
  11258. reg = <0x0>;
  11259. qcom,supply-name = "vcca";
  11260. qcom,supply-min-voltage = <0xe1d48>;
  11261. qcom,supply-max-voltage = <0xe1d48>;
  11262. qcom,supply-enable-load = <0x4268>;
  11263. qcom,supply-disable-load = <0x20>;
  11264. };
  11265. };
  11266.  
  11267. qcom,mdss_dsi_ctrl0@1a94000 {
  11268. compatible = "qcom,mdss-dsi-ctrl";
  11269. label = "MDSS DSI CTRL->0";
  11270. cell-index = <0x0>;
  11271. reg = <0x1a94000 0x400 0x1a94400 0x580 0x193e000 0x30>;
  11272. reg-names = "dsi_ctrl", "dsi_phy", "mmss_misc_phys";
  11273. qcom,timing-db-mode;
  11274. qcom,mdss-mdp = <0x19b>;
  11275. vdd-supply = <0x183>;
  11276. vddio-supply = <0x185>;
  11277. lab-supply = <0x19c>;
  11278. ibb-supply = <0x19d>;
  11279. clocks = <0x195 0x35da7862 0x195 0xcc5c5c77 0x37 0xaec5cb25 0x195 0x75cc885b 0x195 0xccac1f35 0xf5 0x60e83f06 0xf5 0x792379e1 0xf5 0xbbaa30be 0xf5 0x45b3260f 0xf5 0x177c029c 0xf5 0x98ae3c92>;
  11280. clock-names = "byte_clk", "pixel_clk", "core_clk", "byte_clk_rcg", "pixel_clk_rcg", "pll_byte_clk_mux", "pll_pixel_clk_mux", "pll_byte_clk_src", "pll_pixel_clk_src", "pll_shadow_byte_clk_src", "pll_shadow_pixel_clk_src";
  11281. qcom,platform-strength-ctrl = [ff 06 ff 06 ff 06 ff 06 ff 00];
  11282. qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
  11283. qcom,platform-lane-config = <0x100f 0x100f 0x100f 0x100f 0x108f>;
  11284. qcom,dsi-pref-prim-pan = <0x19e>;
  11285. qcom,dsi-pref-sub-pan = <0x19f>;
  11286. qcom,dsi-pref-sub1-pan = <0x1a0>;
  11287. pinctrl-names = "mdss_default", "mdss_sleep";
  11288. pinctrl-0 = <0x1a1 0x1a2>;
  11289. pinctrl-1 = <0x1a3 0x1a4>;
  11290. qcom,platform-te-gpio = <0xbe 0x18 0x0>;
  11291. qcom,platform-reset-gpio = <0xbe 0x3d 0x0>;
  11292. linux,phandle = <0x197>;
  11293. phandle = <0x197>;
  11294. };
  11295.  
  11296. qcom,mdss_dsi_ctrl1@1a96000 {
  11297. compatible = "qcom,mdss-dsi-ctrl";
  11298. label = "MDSS DSI CTRL->1";
  11299. cell-index = <0x1>;
  11300. reg = <0x1a96000 0x400 0x1a96400 0x588 0x193e000 0x30>;
  11301. reg-names = "dsi_ctrl", "dsi_phy", "mmss_misc_phys";
  11302. qcom,mdss-mdp = <0x19b>;
  11303. vdd-supply = <0x183>;
  11304. vddio-supply = <0x185>;
  11305. lab-supply = <0x19c>;
  11306. ibb-supply = <0x19d>;
  11307. clocks = <0x195 0x41f97fd8 0x195 0x9a9c430d 0x37 0x34653cc7 0x195 0x63c2c955 0x195 0x90f68ac 0xf6 0xb5a42b7b 0xf6 0x36458019 0xf6 0x63930a8f 0xf6 0xe4c9b56 0xf6 0xfc021ce5 0xf6 0xdcca3ffc>;
  11308. clock-names = "byte_clk", "pixel_clk", "core_clk", "byte_clk_rcg", "pixel_clk_rcg", "pll_byte_clk_mux", "pll_pixel_clk_mux", "pll_byte_clk_src", "pll_pixel_clk_src", "pll_shadow_byte_clk_src", "pll_shadow_pixel_clk_src";
  11309. qcom,timing-db-mode;
  11310. qcom,platform-strength-ctrl = [ff 06 ff 06 ff 06 ff 06 ff 00];
  11311. qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
  11312. qcom,platform-lane-config = <0x100f 0x100f 0x100f 0x100f 0x108f>;
  11313. status = "disabled";
  11314. };
  11315. };
  11316.  
  11317. qcom,mdss_wb_panel {
  11318. compatible = "qcom,mdss_wb";
  11319. qcom,mdss_pan_res = <0x280 0x280>;
  11320. qcom,mdss_pan_bpp = <0x18>;
  11321. qcom,mdss-fb-map = <0x1a5>;
  11322. };
  11323.  
  11324. qcom,mdss_rotator {
  11325. compatible = "qcom,mdss_rotator";
  11326. qcom,mdss-wb-count = <0x1>;
  11327. qcom,mdss-has-downscale;
  11328. qcom,mdss-has-ubwc;
  11329. qcom,msm-bus,name = "mdss_rotator";
  11330. qcom,msm-bus,num-cases = <0x3>;
  11331. qcom,msm-bus,num-paths = <0x1>;
  11332. qcom,msm-bus,vectors-KBps = <0x16 0x200 0x0 0x0 0x16 0x200 0x0 0x61a800 0x16 0x200 0x0 0x61a800>;
  11333. rot-vdd-supply = <0x178>;
  11334. qcom,supply-names = "rot-vdd";
  11335. qcom,mdss-has-reg-bus;
  11336. clocks = <0x37 0xbfb92ed3 0x195 0x5b1f675e>;
  11337. clock-names = "iface_clk", "rot_core_clk";
  11338.  
  11339. qcom,mdss-rot-reg-bus {
  11340. qcom,msm-bus,name = "mdss_rot_reg";
  11341. qcom,msm-bus,num-cases = <0x2>;
  11342. qcom,msm-bus,num-paths = <0x1>;
  11343. qcom,msm-bus,active-only;
  11344. qcom,msm-bus,vectors-KBps = <0x1 0x24e 0x0 0x0 0x1 0x24e 0x0 0x12c00>;
  11345. };
  11346. };
  11347.  
  11348. qcom,mdss_dsi_pll@994400 {
  11349. compatible = "qcom,mdss_dsi_pll_8953";
  11350. label = "MDSS DSI 0 PLL";
  11351. cell-index = <0x0>;
  11352. #clock-cells = <0x1>;
  11353. reg = <0x1a94400 0x588 0x184d074 0x8 0x1a94200 0x98>;
  11354. reg-names = "pll_base", "gdsc_base", "dynamic_pll_base";
  11355. gdsc-supply = <0x178>;
  11356. clocks = <0x37 0xbfb92ed3>;
  11357. clock-names = "iface_clk";
  11358. clock-rate = <0x0>;
  11359. qcom,dsi-pll-ssc-en;
  11360. qcom,dsi-pll-ssc-mode = "down-spread";
  11361. memory-region = <0x1a6>;
  11362. linux,phandle = <0xf5>;
  11363. phandle = <0xf5>;
  11364.  
  11365. qcom,platform-supply-entries {
  11366. #address-cells = <0x1>;
  11367. #size-cells = <0x0>;
  11368.  
  11369. qcom,platform-supply-entry@0 {
  11370. reg = <0x0>;
  11371. qcom,supply-name = "gdsc";
  11372. qcom,supply-min-voltage = <0x0>;
  11373. qcom,supply-max-voltage = <0x0>;
  11374. qcom,supply-enable-load = <0x0>;
  11375. qcom,supply-disable-load = <0x0>;
  11376. };
  11377. };
  11378. };
  11379.  
  11380. qcom,mdss_dsi_pll@996400 {
  11381. compatible = "qcom,mdss_dsi_pll_8953";
  11382. label = "MDSS DSI 1 PLL";
  11383. cell-index = <0x1>;
  11384. #clock-cells = <0x1>;
  11385. reg = <0x1a96400 0x588 0x184d074 0x8 0x1a96200 0x98>;
  11386. reg-names = "pll_base", "gdsc_base", "dynamic_pll_base";
  11387. gdsc-supply = <0x178>;
  11388. qcom,dsi-pll-ssc-en;
  11389. qcom,dsi-pll-ssc-mode = "down-spread";
  11390. clocks = <0x37 0xbfb92ed3>;
  11391. clock-names = "iface_clk";
  11392. clock-rate = <0x0>;
  11393. linux,phandle = <0xf6>;
  11394. phandle = <0xf6>;
  11395.  
  11396. qcom,platform-supply-entries {
  11397. #address-cells = <0x1>;
  11398. #size-cells = <0x0>;
  11399.  
  11400. qcom,platform-supply-entry@0 {
  11401. reg = <0x0>;
  11402. qcom,supply-name = "gdsc";
  11403. qcom,supply-min-voltage = <0x0>;
  11404. qcom,supply-max-voltage = <0x0>;
  11405. qcom,supply-enable-load = <0x0>;
  11406. qcom,supply-disable-load = <0x0>;
  11407. };
  11408. };
  11409. };
  11410.  
  11411. qcom,camera-flash {
  11412. cell-index = <0x0>;
  11413. compatible = "qcom,camera-flash";
  11414. qcom,flash-type = <0x1>;
  11415. qcom,flash-source = <0x1a7 0x1a8>;
  11416. qcom,torch-source = <0x1a9 0x1aa 0x1ab>;
  11417. qcom,switch-source = <0x1ac>;
  11418. linux,phandle = <0x192>;
  11419. phandle = <0x192>;
  11420. };
  11421.  
  11422. gpio_keys {
  11423. compatible = "gpio-keys";
  11424. input-name = "gpio-keys";
  11425. pinctrl-names = "tlmm_gpio_key_active", "tlmm_gpio_key_suspend";
  11426. pinctrl-0 = <0x1ad>;
  11427. pinctrl-1 = <0x1ae>;
  11428.  
  11429. vol_up {
  11430. label = "volume_up";
  11431. gpios = <0xbe 0x55 0x1>;
  11432. linux,input-type = <0x1>;
  11433. linux,code = <0x73>;
  11434. debounce-interval = <0xf>;
  11435. };
  11436. };
  11437.  
  11438. gen-vkey {
  11439. compatible = "qcom,gen-vkeys";
  11440. label = "ft5346";
  11441. qcom,disp-maxx = <0x438>;
  11442. qcom,disp-maxy = <0x780>;
  11443. qcom,panel-maxx = <0x438>;
  11444. qcom,panel-maxy = <0x820>;
  11445. qcom,key-codes = <0x8b 0xac 0x9e>;
  11446. qcom,y-offset = <0x0>;
  11447. };
  11448.  
  11449. gen-vkey-atmel {
  11450. compatible = "qcom,gen-vkeys-atm";
  11451. label = "atmel-maxtouch";
  11452. qcom,disp-maxx = <0x438>;
  11453. qcom,disp-maxy = <0x780>;
  11454. qcom,panel-maxx = <0x438>;
  11455. qcom,panel-maxy = <0x820>;
  11456. qcom,key-codes = <0x8b 0xac 0x9e>;
  11457. qcom,y-offset = <0x0>;
  11458. };
  11459.  
  11460. goodix_fp {
  11461. compatible = "goodix,fingerprint";
  11462. spi-max-frequency = <0xf4240>;
  11463. input-device-name = "gf3208";
  11464. interrupt-parent = <0xbe>;
  11465. interrupts = <0x9 0x0>;
  11466. goodix,gpio_reset = <0xbe 0x8c 0x0>;
  11467. goodix,gpio_irq = <0xbe 0x30 0x0>;
  11468. clock-names = "iface_clk", "core_clk";
  11469. clocks = <0x37 0x8caa5b4f 0x37 0x759a76b0>;
  11470. pinctrl-names = "goodixfp_spi_active", "goodixfp_reset_reset", "goodixfp_reset_active", "goodixfp_irq_active";
  11471. pinctrl-0 = <0x1af>;
  11472. pinctrl-1 = <0x1b0>;
  11473. pinctrl-2 = <0x1b1>;
  11474. pinctrl-3 = <0x1b2>;
  11475. };
  11476.  
  11477. vdd_vreg {
  11478. compatible = "regulator-fixed";
  11479. status = "ok";
  11480. regulator-name = "vdd_vreg";
  11481. };
  11482.  
  11483. boardinfo {
  11484. compatible = "wt:boardinfo";
  11485. };
  11486.  
  11487. gpio-leds {
  11488. compatible = "gpio-leds";
  11489. status = "okay";
  11490. pinctrl-names = "default";
  11491. pinctrl-0 = <0x1b3>;
  11492.  
  11493. infred {
  11494. gpios = <0xbe 0x2d 0x0>;
  11495. label = "infrared";
  11496. linux,default-trigger = "infra-red";
  11497. default-state = "off";
  11498. retain-state-suspended;
  11499. };
  11500. };
  11501.  
  11502. fpc1020 {
  11503. compatible = "soc:fpc1020";
  11504. interrupt-parent = <0xbe>;
  11505. interrupts = <0x30 0x0>;
  11506. fpc,gpio_rst = <0xbe 0x8c 0x0>;
  11507. fpc,gpio_irq = <0xbe 0x30 0x0>;
  11508. vcc_spi-supply = <0xe1>;
  11509. vdd_ana-supply = <0xe1>;
  11510. vdd_io-supply = <0xe1>;
  11511. fpc,enable-on-boot;
  11512. fpc,spi-max-frequency = <0x493e00>;
  11513. clock-names = "iface_clk", "core_clk";
  11514. clocks = <0x37 0x8caa5b4f 0x37 0x759a76b0>;
  11515. pinctrl-names = "fpc1020_spi_active", "fpc1020_reset_reset", "fpc1020_reset_active", "fpc1020_irq_active";
  11516. pinctrl-0 = <0x1b4>;
  11517. pinctrl-1 = <0x1b5>;
  11518. pinctrl-2 = <0x1b6>;
  11519. pinctrl-3 = <0x1b7>;
  11520. };
  11521.  
  11522. dsi_panel_pwr_supply {
  11523. #address-cells = <0x1>;
  11524. #size-cells = <0x0>;
  11525. linux,phandle = <0x198>;
  11526. phandle = <0x198>;
  11527.  
  11528. qcom,panel-supply-entry@0 {
  11529. reg = <0x0>;
  11530. qcom,supply-name = "vdd";
  11531. qcom,supply-min-voltage = <0x2b7cd0>;
  11532. qcom,supply-max-voltage = <0x2b7cd0>;
  11533. qcom,supply-enable-load = <0x186a0>;
  11534. qcom,supply-disable-load = <0x64>;
  11535. };
  11536.  
  11537. qcom,panel-supply-entry@1 {
  11538. reg = <0x1>;
  11539. qcom,supply-name = "vddio";
  11540. qcom,supply-min-voltage = <0x1b7740>;
  11541. qcom,supply-max-voltage = <0x1b7740>;
  11542. qcom,supply-enable-load = <0x186a0>;
  11543. qcom,supply-disable-load = <0x64>;
  11544. };
  11545.  
  11546. qcom,panel-supply-entry@2 {
  11547. reg = <0x2>;
  11548. qcom,supply-name = "lab";
  11549. qcom,supply-min-voltage = <0x4630c0>;
  11550. qcom,supply-max-voltage = <0x5b8d80>;
  11551. qcom,supply-enable-load = <0x186a0>;
  11552. qcom,supply-disable-load = <0x64>;
  11553. };
  11554.  
  11555. qcom,panel-supply-entry@3 {
  11556. reg = <0x3>;
  11557. qcom,supply-name = "ibb";
  11558. qcom,supply-min-voltage = <0x4630c0>;
  11559. qcom,supply-max-voltage = <0x5b8d80>;
  11560. qcom,supply-enable-load = <0x186a0>;
  11561. qcom,supply-disable-load = <0x64>;
  11562. qcom,supply-post-on-sleep = <0xa>;
  11563. };
  11564. };
  11565. };
  11566.  
  11567. chosen {
  11568. bootargs = "sched_enable_hmp=1 sched_enable_power_aware=1";
  11569. };
  11570.  
  11571. aliases {
  11572. smd1 = "/soc/qcom,smdtty/qcom,smdtty-apps-fm";
  11573. smd2 = "/soc/qcom,smdtty/smdtty-apps-riva-bt-acl";
  11574. smd3 = "/soc/qcom,smdtty/qcom,smdtty-apps-riva-bt-cmd";
  11575. smd4 = "/soc/qcom,smdtty/qcom,smdtty-mbalbridge";
  11576. smd5 = "/soc/qcom,smdtty/smdtty-apps-riva-ant-cmd";
  11577. smd6 = "/soc/qcom,smdtty/smdtty-apps-riva-ant-data";
  11578. smd7 = "/soc/qcom,smdtty/qcom,smdtty-data1";
  11579. smd8 = "/soc/qcom,smdtty/qcom,smdtty-data4";
  11580. smd11 = "/soc/qcom,smdtty/qcom,smdtty-data11";
  11581. smd21 = "/soc/qcom,smdtty/qcom,smdtty-data21";
  11582. smd36 = "/soc/qcom,smdtty/smdtty-loopback";
  11583. sdhc1 = "/soc/sdhci@7824900";
  11584. sdhc2 = "/soc/sdhci@7864900";
  11585. i2c2 = "/soc/i2c@78b6000";
  11586. i2c3 = "/soc/i2c@78b7000";
  11587. i2c5 = "/soc/i2c@7af5000";
  11588. spi3 = "/soc/spi@78b7000";
  11589. };
  11590.  
  11591. memory {
  11592. device_type = "memory";
  11593. reg = <0x0 0x0 0x0 0x0>;
  11594. };
  11595.  
  11596. reserved-memory {
  11597. #address-cells = <0x2>;
  11598. #size-cells = <0x2>;
  11599. ranges;
  11600.  
  11601. other_ext_region@0 {
  11602. compatible = "removed-dma-pool";
  11603. no-map;
  11604. reg = <0x0 0x84a00000 0x0 0x1e00000>;
  11605. };
  11606.  
  11607. modem_region@0 {
  11608. compatible = "removed-dma-pool";
  11609. no-map-fixup;
  11610. reg = <0x0 0x86c00000 0x0 0x5600000>;
  11611. linux,phandle = <0x121>;
  11612. phandle = <0x121>;
  11613. };
  11614.  
  11615. reloc_region@0 {
  11616. compatible = "removed-dma-pool";
  11617. no-map;
  11618. reg = <0x0 0x8c200000 0x0 0x1800000>;
  11619. linux,phandle = <0x124>;
  11620. phandle = <0x124>;
  11621. };
  11622.  
  11623. venus_region@0 {
  11624. compatible = "shared-dma-pool";
  11625. reusable;
  11626. alloc-ranges = <0x0 0x80000000 0x0 0x10000000>;
  11627. alignment = <0x0 0x400000>;
  11628. size = <0x0 0x800000>;
  11629. linux,phandle = <0x125>;
  11630. phandle = <0x125>;
  11631. };
  11632.  
  11633. secure_region@0 {
  11634. compatible = "shared-dma-pool";
  11635. reusable;
  11636. alignment = <0x0 0x400000>;
  11637. size = <0x0 0x9800000>;
  11638. linux,phandle = <0x3e>;
  11639. phandle = <0x3e>;
  11640. };
  11641.  
  11642. qseecom_region@0 {
  11643. compatible = "shared-dma-pool";
  11644. reusable;
  11645. alignment = <0x0 0x400000>;
  11646. size = <0x0 0x1000000>;
  11647. linux,phandle = <0x3f>;
  11648. phandle = <0x3f>;
  11649. };
  11650.  
  11651. adsp_region@0 {
  11652. compatible = "shared-dma-pool";
  11653. reusable;
  11654. size = <0x0 0x400000>;
  11655. linux,phandle = <0x103>;
  11656. phandle = <0x103>;
  11657. };
  11658.  
  11659. dfps_data_mem@90000000 {
  11660. reg = <0x0 0x90000000 0x0 0x1000>;
  11661. label = "dfps_data_mem";
  11662. linux,phandle = <0x1a6>;
  11663. phandle = <0x1a6>;
  11664. };
  11665.  
  11666. splash_region@0x90001000 {
  11667. reg = <0x0 0x90001000 0x0 0x13ff000>;
  11668. label = "cont_splash_mem";
  11669. linux,phandle = <0x196>;
  11670. phandle = <0x196>;
  11671. };
  11672.  
  11673. gpu_region@0 {
  11674. compatible = "shared-dma-pool";
  11675. reusable;
  11676. alloc-ranges = <0x0 0x80000000 0x0 0x10000000>;
  11677. alignment = <0x0 0x400000>;
  11678. size = <0x0 0x800000>;
  11679. linux,phandle = <0x36>;
  11680. phandle = <0x36>;
  11681. };
  11682. };
  11683.  
  11684. psci {
  11685. compatible = "arm,psci-1.0";
  11686. method = "smc";
  11687. };
  11688.  
  11689. qcom,battery-data {
  11690. qcom,batt-id-range-pct = <0xf>;
  11691. linux,phandle = <0x11d>;
  11692. phandle = <0x11d>;
  11693.  
  11694. qcom,2369665_wingtech_b5w_4000mah_averaged_masterslave_apr1st2016 {
  11695. qcom,max-voltage-uv = <0x432380>;
  11696. qcom,nom-batt-capacity-mah = <0xfa0>;
  11697. qcom,batt-id-kohm = <0x64>;
  11698. qcom,battery-beta = <0xd6b>;
  11699. qcom,thermal-coefficients = [c2 86 bb 50 cf 37];
  11700. qcom,battery-type = "Coslight_4000mah";
  11701. qcom,chg-rslow-comp-c1 = <0x39f5bb>;
  11702. qcom,chg-rslow-comp-c2 = <0x578ee5>;
  11703. qcom,chg-rs-to-rslow = <0xfb421>;
  11704. qcom,chg-rslow-comp-thr = <0xab>;
  11705. qcom,checksum = <0x3522>;
  11706. qcom,gui-version = "PMI8950GUI - 2.0.0.15";
  11707. qcom,fg-profile-data = <0xcb837577 0xd37b5574 0x5e834e6d 0x65887c8f 0x45829598 0x69b608c2 0x52149b83 0xda6fc379 0xe96d3883 0x2279e585 0x6a81a182 0x2d98c0b7 0xcec87013 0x4010d059 0x1470f8ff 0x1335a645 0xcf400000 0x8647f131 0x27400000 0x0 0x0 0x6270f469 0x235bfd88 0x6a7c1572 0x1e639e80 0x90751d6b 0x656fcca8 0x230d6056 0x5da0710c 0x2800ff36 0xf0113003 0xc>;
  11708. };
  11709.  
  11710. qcom,2389679_wingtech_b5w_scud_4000mah_averaged_masterslave_apr11th2016 {
  11711. qcom,max-voltage-uv = <0x432380>;
  11712. qcom,nom-batt-capacity-mah = <0xfa0>;
  11713. qcom,batt-id-kohm = <0x32>;
  11714. qcom,battery-beta = <0xd6b>;
  11715. qcom,thermal-coefficients = [c2 86 bb 50 cf 37];
  11716. qcom,battery-type = "Feimaotui_4000mah";
  11717. qcom,chg-rslow-comp-c1 = <0x273e66>;
  11718. qcom,chg-rslow-comp-c2 = <0x2a067a>;
  11719. qcom,chg-rs-to-rslow = <0x1ca6d6>;
  11720. qcom,chg-rslow-comp-thr = <0x99>;
  11721. qcom,checksum = <0x8aa7>;
  11722. qcom,gui-version = "PMI8950GUI - 2.0.0.15";
  11723. qcom,fg-profile-data = <0xb783d775 0x607a676d 0x6c833c77 0xe38bf596 0xf581959a 0x23bd5ec9 0x4c126883 0xfd54c071 0x6c323e83 0x9978d884 0xde7b5182 0x25990ebc 0x41c8710c 0x6b10d252 0x1470eefc 0xf0352447 0xca410000 0xae47e539 0x0 0x0 0x0 0xea737072 0x6cfa80 0x3b75d862 0x150ac72 0xc56e654b 0x7c77f0ab 0x21b96a95 0x6ca0710c 0x2800ff36 0xf0113003 0xc>;
  11724. };
  11725.  
  11726. qcom,2369665_wingtech_b5w_4000mah_default {
  11727. qcom,max-voltage-uv = <0x432380>;
  11728. qcom,nom-batt-capacity-mah = <0xfa0>;
  11729. qcom,batt-id-kohm = <0x1>;
  11730. qcom,battery-beta = <0xd6b>;
  11731. qcom,thermal-coefficients = [c2 86 bb 50 cf 37];
  11732. qcom,battery-type = "Default_Coslight_4000mah";
  11733. qcom,chg-rslow-comp-c1 = <0x39f5bb>;
  11734. qcom,chg-rslow-comp-c2 = <0x578ee5>;
  11735. qcom,chg-rs-to-rslow = <0xfb421>;
  11736. qcom,chg-rslow-comp-thr = <0xab>;
  11737. qcom,checksum = <0x3522>;
  11738. qcom,gui-version = "PMI8950GUI - 2.0.0.15";
  11739. qcom,fg-profile-data = <0xcb837577 0xd37b5574 0x5e834e6d 0x65887c8f 0x45829598 0x69b608c2 0x52149b83 0xda6fc379 0xe96d3883 0x2279e585 0x6a81a182 0x2d98c0b7 0xcec87013 0x4010d059 0x1470f8ff 0x1335a645 0xcf400000 0x8647f131 0x27400000 0x0 0x0 0x6270f469 0x235bfd88 0x6a7c1572 0x1e639e80 0x90751d6b 0x656fcca8 0x230d6056 0x5da0710c 0x2800ff36 0xf0113003 0xc>;
  11740. };
  11741. };
  11742. };
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