raul@raul-vbox:~/or1k/mysoc$ fusesoc sim --sim=icarus wb_sdram_ctrl
INFO:  Preparing wb_bfm
INFO:  Preparing vlog_tb_utils
INFO:  Preparing wb_sdram_ctrl
INFO:  Checking out https://github.com/skristiansson/wb_sdram_ctrl/archive/master.tar.gz revision master to /home/raul/.cache/fusesoc/wb_sdram_ctrl
INFO:  Preparing mt48lc16m16a2
INFO:  Checking out http://www.micron.com/~/media/Documents/Products/Sim%20Model/DRAM/DRAM/4012mt48lc16m16a2.zip to /home/raul/.cache/fusesoc/mt48lc16m16a2

/home/raul/or1k/mysoc/build/wb_sdram_ctrl/src/mt48lc16m16a2/mt48lc16m16a2_wrapper.v:2: Include file timescale.v not found
error: Unable to find the root module "wb_sdram_ctrl_tb" in the Verilog source.
     : Perhaps ``-s wb_sdram_ctrl_tb'' is incorrect?
1 error(s) during elaboration.
ERROR: Failed to build simulation model
ERROR: Failed to compile Icarus Simulation model
raul@raul-vbox:~/or1k/mysoc$