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beaglebone_gpio.h

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  1. #ifndef _BEAGLEBONE_GPIO_H_
  2. #define _BEAGLEBONE_GPIO_H_
  3.  
  4. #define CONTROL_MODULE_START_ADDR   0x44E10000
  5. #define CONTROL_MODULE_END_ADDR 0x44E11FFF
  6. #define CONTROL_MODULE_SIZE (CONTROL_MODULE_END_ADDR - CONTROL_MODULE_START_ADDR)
  7.  
  8. #define PIN_RX_DISABLED 0
  9. #define PIN_RX_ENABLED  (1<<5)
  10.  
  11. #define PIN_PULLUD_DISABLED 0
  12. #define PIN_PULLUD_ENABLED (1<<3)
  13.  
  14. #define PIN_PULLUP (1<<4)
  15. #define PIN_PULLDOWN 0
  16.  
  17. #define PIN_SLEW_FAST 0
  18. #define PIN_SLEW_SLOW (1<<6)
  19.  
  20.  
  21. #define PIN_MODE0   0
  22. #define PIN_MODE1 1
  23. #define PIN_MODE2 2
  24. #define PIN_MODE3 3
  25. #define PIN_MODE4 4
  26. #define PIN_MODE5 5
  27. #define PIN_MODE6 6
  28. #define PIN_MODE7 7
  29.  
  30.  
  31. #define CONF_GPIO1_28 0x878
  32.  
  33.  
  34.  
  35. #define GPIO_SIZE               0x2000
  36. #define GPIO0_START_ADDR    0x44E07000
  37. #define GPIO1_START_ADDR    0x4804C000
  38. #define GPIO2_START_ADDR    0x481AC000
  39. #define GPIO3_START_ADDR    0x481AE000
  40.  
  41. #define GPIO_OE                 0x134
  42. #define GPIO_SETDATAOUT     0x194
  43. #define GPIO_CLEARDATAOUT   0x190
  44. #define GPIO_DATAIN         0x138
  45.  
  46. typedef struct {
  47.     volatile void *gpio_addr;
  48.     volatile unsigned int *oe_reg;
  49.     volatile unsigned int *setdataout_reg;
  50.     volatile unsigned int *clrdataout_reg;
  51.    volatile unsigned int *datain_reg;
  52. } bb_gpio_port;
  53.  
  54. typedef struct {
  55.     bb_gpio_port *port;
  56.     char port_num;
  57.     char pin_num;
  58.     unsigned short control_offset;
  59.     char claimed;
  60. } bb_gpio_pin;
  61.  
  62. volatile void *control_module;
  63.  
  64. bb_gpio_port *gpio_ports[4];
  65.  
  66. bb_gpio_pin user_led_gpio_pins[4] = {
  67.     { NULL, 1, 21, 0x854, 0 }, // led0, gpmc_a5
  68.     { NULL, 1, 22, 0x858, 0 }, // led1, gpmc_a6
  69.     { NULL, 1, 23, 0x85C, 0 }, // led2, gpmc_a7
  70.     { NULL, 1, 24, 0x860, 0 }   // led3, gpmc_a8
  71. };
  72.  
  73. bb_gpio_pin p8_pins[47] = {
  74.     { NULL, -1, -1, -1, 1 }, // 0 unused
  75.     { NULL, -1, -1, -1, 1 }, // 1 GND
  76.     { NULL, -1, -1, -1, 1 }, // 2 GND
  77.     { NULL, 1,  6, 0x818, 0 }, // pin 3, gpmc_ad6
  78.     { NULL, 1,  7, 0x81C, 0 }, // pin 4, gpmc_ad7
  79.     { NULL, 1,  2, 0x808, 0 }, // pin 5, gpmc_ad2
  80.     { NULL, 1,  3, 0x803, 0 }, // pin 6, gpmc_ad3
  81.     { NULL, 2,  2, 0x890, 0 }, // pin 7, gpmc_advn_ale
  82.     { NULL, 2,  3, 0x894, 0 }, // pin 8, gpmc_oen_ren
  83.     { NULL, 2,  5, 0x89C, 0 }, // pin 9, gpmc_ben0_cle
  84.     { NULL, 2,  4, 0x898, 0 }, // pin 10, gpmc_wen
  85.     { NULL, 1, 13, 0x834, 0 }, // pin 11, gpmc_ad13
  86.     { NULL, 1, 12, 0x830, 0 }, // pin 12, GPMC_AD12
  87.     { NULL, 0, 23, 0x824, 0 }, // pin 13, gpmc_ad9
  88.     { NULL, 0, 26, 0x828, 0 }, // pin 14, gpmc_ad10
  89.     { NULL, 1, 15, 0x83C, 0 }, // pin 15, gpmc_ad15
  90.     { NULL, 1, 14, 0x838, 0 }, // pin 16, gpmc_ad14
  91.     { NULL, 0, 27, 0x82C, 0 }, // pin 17, gpmc_ad11
  92.     { NULL, 2,  1, 0x88C, 0 }, // pin 18, gpmc_clk_mux0
  93.     { NULL, 0, 22, 0x820, 0 }, // pin 19, gpmc_ad8
  94.     { NULL, 1, 31, 0x884, 0 }, // pin 20, gpmc_csn2
  95.     { NULL, 1, 30, 0x880, 0 }, // pin 21, gpmc_csn1
  96.     { NULL, 1,  5, 0x814, 0 }, // pin 22, gpmc_ad5
  97.     { NULL, 1,  4, 0x810, 0 }, // pin 23, gpmc_ad4
  98.     { NULL, 1,  1, 0x804, 0 }, // pin 24, gpmc_ad1
  99.     { NULL, 1,  0, 0x800, 0 }, // pin 25, gpmc_ad0
  100.     { NULL, 1, 29, 0x87C, 0 }, // pin 26, gpmc_csn0
  101.     { NULL, 2, 22, 0x8E0, 0 }, // pin 27, lcd_vsync
  102.     { NULL, 2, 24, 0x8E8, 0 }, // pin 28, lcd_pclk
  103.     { NULL, 2, 23, 0x8E4, 0 }, // pin 29, lcd_hsync
  104.     { NULL, 2, 25, 0x8EC, 0 }, // pin 30, lcd_ac_bias_en
  105.     { NULL, 0, 10, 0x8D8, 0 }, // pin 31, lcd_data14
  106.     { NULL, 0, 11, 0x8DC, 0 }, // pin 32, lcd_data15
  107.     { NULL, 0,  9, 0x8D4, 0 }, // pin 33, lcd_data13
  108.     { NULL, 2, 17, 0x8CC, 0 }, // pin 34, lcd_data11
  109.     { NULL, 0,  8, 0x8D0, 0 }, // pin 35, lcd_data12
  110.     { NULL, 2, 16, 0x8C8, 0 }, // pin 36, lcd_data10
  111.     { NULL, 2, 14, 0x8C0, 0 }, // pin 37, lcd_data8
  112.     { NULL, 2, 15, 0x8C4, 0 }, // pin 38, lcd_data9
  113.     { NULL, 2, 12, 0x8B8, 0 }, // pin 39, lcd_data6
  114.     { NULL, 2, 13, 0x8BC, 0 }, // pin 40, lcd_data7
  115.     { NULL, 2, 10, 0x8B0, 0 }, // pin 41, lcd_data4
  116.     { NULL, 2, 11, 0x8B4, 0 }, // pin 42, lcd_data5
  117.     { NULL, 2,  8, 0x8A8, 0 }, // pin 43, lcd_data2
  118.     { NULL, 2,  9, 0x8AC, 0 }, // pin 44, lcd_data3
  119.     { NULL, 2,  6, 0x8A0, 0 }, // pin 45, lcd_data0
  120.     { NULL, 2,  7, 0x8A4, 0 }  // pin 46, lcd_data1
  121. };
  122.  
  123. bb_gpio_pin p9_pins[47] = {
  124.     { NULL, -1, -1, -1, 1 }, // 0 unused
  125.     { NULL, -1, -1, -1, 1 }, // 1 GND
  126.     { NULL, -1, -1, -1, 1 }, // 2 GND
  127.     { NULL, -1, -1, -1, 1 }, // 3 3.3v
  128.     { NULL, -1, -1, -1, 1 }, // 4 3.v
  129.     { NULL, -1, -1, -1, 1 }, // 5 Vdd 5v
  130.     { NULL, -1, -1, -1, 1 }, // 6 Vdd 5v
  131.     { NULL, -1, -1, -1, 1 }, // 7 Sys 5v
  132.     { NULL, -1, -1, -1, 1 }, // 8 Sys 5v
  133.     { NULL, -1, -1, -1, 1 }, // 9 power button
  134.     { NULL, -1, -1, -1, 1 }, // 10 sys_reset
  135.     { NULL, 0, 30, 0x870, 0 }, // pin 11, gpmc_wait0
  136.     { NULL, 1, 28, 0x878, 0 }, // pin 12, gpmc_ben1
  137.     { NULL, 0, 31, 0x874, 0 }, // pin 13, gpmc_wpn
  138.     { NULL, 1, 18, 0x848, 0 }, // pin 14, gpmc_a2
  139.     { NULL, 1, 16, 0x840, 0 }, // pin 15, gpmc_a0
  140.     { NULL, 1, 19, 0x84C, 0 }, // pin 16, gpmc_a3
  141.     { NULL, 0,  5, 0x95C, 0 }, // pin 17, spi0_cs0
  142.     { NULL, 0,  4, 0x958, 0 }, // pin 18, spi0_d1
  143.     { NULL, 0, 13, 0x97C, 0 }, // pin 19, uart1_rtsn
  144.     { NULL, 0, 12, 0x978, 0 }, // pin 20, uart1_ctsn
  145.     { NULL, 0,  3, 0x954, 0 }, // pin 21, spi0_d0
  146.     { NULL, 0,  2, 0x950, 0 }, // pin 22, spi0_sclk
  147.     { NULL, 1, 17, 0x844, 0 }, // pin 23, gpmc_a1
  148.     { NULL, 0, 15, 0x984, 0 }, // pin 24, uart1_txd
  149.     { NULL, 3, 21, 0x9AC, 0 }, // pin 25, mcasp0_ahclkx
  150.     { NULL, 0, 14, 0x980, 0 }, // pin 26, uart1_rxd
  151.     { NULL, 3, 19, 0x9A4, 0 }, // pin 27, mcasp0_fsr
  152.     { NULL, 3, 17, 0x99C, 0 }, // pin 28, mcasp0_ahclkr
  153.     { NULL, 3, 15, 0x994, 0 }, // pin 29, mcasp0_fsx
  154.     { NULL, 3, 16, 0x998, 0 }, // pin 30, mcasp0_axr0
  155.     { NULL, 3, 14, 0x990, 0 }, // pin 31, mcasp0_aclkx
  156.     { NULL, -1, -1, -1, 1 }, // 32 VADC
  157.     { NULL, -1, -1, -1, 1 }, // 33 AIN4
  158.     { NULL, -1, -1, -1, 1 }, // 34 AGND
  159.     { NULL, -1, -1, -1, 1 }, // 35 AIN6
  160.     { NULL, -1, -1, -1, 1 }, // 36 AIN5
  161.     { NULL, -1, -1, -1, 1 }, // 37 AIN2
  162.     { NULL, -1, -1, -1, 1 }, // 38 AIN3
  163.     { NULL, -1, -1, -1, 1 }, // 39 AIN0
  164.     { NULL, -1, -1, -1, 1 }, // 40 AIN1
  165. //  { NULL, 3, 20, 0x9A8, 0 }, // pin 41, mcasp0_axr1        NOTE 41 and 42 each have two signals connected
  166.     { NULL, 0, 20, 0x9B4, 0 }, // pin 41, xdma_event_intr1
  167.     { NULL, 0,  7, 0x964, 0 }, // pin 42, ecap0_in_pwm0_out
  168. //  { NULL, 3, 18, 0x9A0, 0 }, // pin 42, mcasp0_aclkr
  169.     { NULL, -1, -1, -1, 1 }, // 43 GND
  170.     { NULL, -1, -1, -1, 1 }, // 44 GND
  171.     { NULL, -1, -1, -1, 1 }, // 45 GND
  172.     { NULL, -1, -1, -1, 1 }, // 46 GND
  173. };
  174.  
  175.  
  176.  
  177. #endif
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