module DEBUG_UART
  #(
    parameter clk_frequency = 50_000_000,
    parameter baud_rate = 921600,
    parameter stop_bits = 2,
    parameter data_width = 16,
    parameter sample_size = 32768
  )
  (
    input wire clk,
    input wire reset,
    input wire [data_width - 1:0] data,
    output wire txd
  );

  localparam data_width_bytes = ((data_width - 1) / 8) + 1;
  localparam sample_size_bytes = sample_size * data_width_bytes;
  localparam header_size_bytes = 12;

  localparam STATE_RECORD               = 2'h0;
  localparam STATE_TRANSFER_HEADER      = 2'h1;
  localparam STATE_TRANSFER_HEADER_STOP = 2'h2;
  localparam STATE_TRANSFER_DATA        = 2'h3;

  wire [7:0] uart_data;
  wire UART_start;
  wire UART_busy;

  reg [data_width - 1:0] data_buf [sample_size - 1:0];
  reg [data_width - 1:0] buf_out;
  reg [7:0] header [header_size_bytes - 1:0];
  reg [7:0] header_out;
  reg [1:0] state = STATE_RECORD;
  reg buf_we = 1'b1;
  reg [3:0] header_cnt = 0;
  reg [$clog2(sample_size) - 1:0] buf_cnt = 0;
  reg [$clog2(data_width_bytes) - 1:0] byte_cnt = 0;
  reg [7:0] buf_out_byte = 0;

  assign uart_data = ((state == STATE_TRANSFER_HEADER) ||
            (state == STATE_TRANSFER_HEADER_STOP)) ? header_out : buf_out_byte;
  assign UART_start = (state == STATE_TRANSFER_HEADER) ||
              (state == STATE_TRANSFER_HEADER_STOP) ||
              (state == STATE_TRANSFER_DATA);

  initial begin
    header[0] = 8'h01; header[1] = 8'h23;
    header[2] = 8'h45; header[3] = 8'h67;
    header[4] = 8'h89; header[5] = 8'hAB;
    header[6] = 8'hCD; header[7] = 8'hEF;
    header[8] = data_width;
    header[9] = sample_size >> 16;
    header[10] = sample_size >> 8;
    header[11] = sample_size;
  end

  always @(posedge clk) begin
    if (buf_we)
      data_buf[buf_cnt] <= data;
    buf_out <= data_buf[buf_cnt];
    buf_out_byte <= buf_out >> ((data_width_bytes - 1 - byte_cnt) * 8);
  end

  always @(posedge clk) begin
    if (reset) begin
      state <= STATE_RECORD;
      header_cnt <= 0;
      buf_cnt <= 0;
      buf_we <= 1'b1;
    end else begin
      case (state)
        STATE_RECORD: begin
          buf_we <= 1'b1;
          buf_cnt <= buf_cnt + 1;
          if (buf_cnt == sample_size - 1) begin
            header_cnt <= 0;
            buf_cnt <= 0;
            buf_we <= 1'b0;
            header_cnt <= 1;
            header_out <= header[0];
            state <= STATE_TRANSFER_HEADER;
          end
        end
        STATE_TRANSFER_HEADER: begin
          if (!UART_busy) begin
            header_cnt <= header_cnt + 1'b1;
            header_out <= header[header_cnt];
            if (header_cnt == header_size_bytes - 1) begin
              byte_cnt <= 0;
              buf_cnt <= 0;
              state <= STATE_TRANSFER_HEADER_STOP;
            end
          end
        end
        STATE_TRANSFER_HEADER_STOP: begin
          if (!UART_busy) begin
            state <= STATE_TRANSFER_DATA;
          end
        end
        STATE_TRANSFER_DATA: begin
          if (!UART_busy) begin
            if (byte_cnt < data_width_bytes - 1) begin
              byte_cnt <= byte_cnt + 1'b1;
            end else begin
              byte_cnt <= 0;
              buf_cnt <= buf_cnt + 1'b1;
              if (buf_cnt == sample_size - 1) begin
                buf_cnt <= 0;
                byte_cnt <= 0;
                state <= STATE_RECORD;
              end
            end
          end
        end
        default: begin
          state <= STATE_RECORD;
        end
      endcase
    end
  end

  UART_TX #(
    .clk_frequency(clk_frequency),
    .baud_rate(baud_rate),
    .stop_bits(stop_bits)
  ) UART_TX_inst (
    .clk(clk),
    .data(uart_data),
    .start(UART_start),
    .busy(UART_busy),
    .txd(txd)
  );
endmodule