`timescale 1ns / 1ps

/*
Copyright (c) 2016, Stephen J. Leary
All rights reserved.

Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright
   notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
   notice, this list of conditions and the following disclaimer in the
   documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this software
   must display the following acknowledgement:
   This product includes software developed by the <organization>.
4. Neither the name of the <organization> nor the
   names of its contributors may be used to endorse or promote products
   derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY <COPYRIGHT HOLDER> ''AS IS'' AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

*/

module sjl520(

           input     CLKCPU,
           input     CLK7M,

           input     BG20,
           input     AS20,
           input     DS20,
           input     RW20,
           output    RW00,


           input [2:0]   FC,
           input [1:0]   SIZ,

       input         A0,
           input [19:16] A,

           input     BGACK,
           input     VPA,
           input     DTACK,

           output    BG,
           output    LDS,
           output    UDS,
           output    VMA,
           output reg E,
           output    AS,
           output    BERR,

           output    DSACK1,
           output    AVEC
       );

reg DS20DLY = 1'b1;
reg AS20DLY = 1'b1;
reg RW20DLY = 1'b1;
reg CLK7MB2 = 1'b1;
reg BGACKD1 = 1'b1;
reg BGACKD2 = 1'b1;

reg [3:0] Q = 'hF;

reg DSACK1_SYNC = 1'b1;
reg VMA_SYNC = 1'b1;

initial begin

E = 'b0;

end


wire CPUSPACE = &FC;

wire CPCS = CPUSPACE & ({A[19:16]} === {4'b0010});
wire BKPT = CPUSPACE & ({A[19:16]} === {4'b0000});
wire IACK = CPUSPACE & ({A[19:16]} === {4'b1111});

always @(posedge CLK7M) begin

    // Delayed Address Strobes
    AS20DLY <= AS20;
    RW20DLY <= RW20;
    DS20DLY <= DS20;

    BGACKD1 <= BGACK;
    BGACKD2 <= BGACKD1;

    // 7Mhz Clock divided by 2
    CLK7MB2 <= ~CLK7MB2;

   if (Q == 'd9) begin

      VMA_SYNC <= 1'b1;
      DSACK1_SYNC <= 1'b1;
      Q <= 'd0;

   end else begin

      Q <= Q + 'd1;

      if (Q == 'd4) begin
     E <= 'b1;
      end

      if (Q == 'd8) begin
        E <= 'b0;
      end

      if (Q == 'd2) begin

         VMA_SYNC <= VPA | CPUSPACE;

      end

      if (Q == 'd7) begin
         DSACK1_SYNC <= VMA_SYNC;
      end

   end

end


//wire HIGHZ = BG20 | //(BG20 & (AS20DLY | AS20)) | CPUSPACE;
wire HIGHZ = (BG20 & (AS20DLY | AS20)) | CPUSPACE;
wire AS_INT = AS20DLY | AS20;
wire UDS_INT = DS20 | DS20DLY | A0;
wire LDS_INT = DS20 | DS20DLY | ({A0, SIZ[1:0]} == 3'b001);
wire VMA_INT = VMA_SYNC;

assign RW00 = RW20DLY | RW20;
assign AS = AS_INT;
assign UDS =  UDS_INT;
assign LDS =   LDS_INT;
assign VMA =  VMA_INT;

assign DSACK1 = CPCS | (AS20DLY | AS20 | (DTACK & DSACK1_SYNC));

assign BG = BG20 | AS20DLY | AS20;
assign AVEC = IACK & ~VPA;
//assign BERR = CPCS ? 1'b0 : 1'bz;

OBUFT #(
.DRIVE(12), // Specify the output drive strength
.IOSTANDARD("DEFAULT"), // Specify the output I/O standard
.SLEW("SLOW") // Specify the output slew rate
) OBUFT_inst (
.O(BERR), // Buffer output (connect directly to top-level port)
.I(~CPCS), // Buffer input
.T(~CPCS)
);

endmodule