Advertisement
Guest User

Untitled

a guest
Nov 24th, 2014
147
0
Never
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
VHDL 0.20 KB | None | 0 0
  1. entity Nand2 is
  2.  Port ( a : in STD_LOGIC;
  3.  b : in STD_LOGIC;
  4.  z : out STD_LOGIC);
  5. end Nand2;
  6.  
  7.  
  8. architecture Behavioral of Nand2 is
  9. begin
  10. z <= not(a and b);
  11. -- z <= a and b;
  12. end Behavioral;
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement