library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;


entity Dwukierunkowy3 is
    Port (	CLK, DIR: in  std_logic;
				Q : buffer std_logic_vector(7 downto 0));
end Dwukierunkowy3;

architecture Behavioral of Dwukierunkowy3 is

begin
process (CLK)
	begin
		if rising_edge (CLK) then
			if (DIR = '0') then
				Q <= Q + 1;
			else
				Q <= Q - 1;
			end if;
		end if;
	end process;
end Behavioral;