module UART_TX
  #(
    parameter clk_frequency = 50_000_000,
    parameter baud_rate = 921600,
    parameter stop_bits = 2
  )
  (
    input wire clk,
    input wire reset,
    input wire [7:0] data,
    input wire start,
    output wire busy,
    output wire txd
  );

  localparam frame_length = 9 + stop_bits;
  localparam stop_bit = 1'b1;
  localparam start_bit = 1'b0;

  localparam STATE_IDLE  = 1'b0;
  localparam STATE_TX    = 1'b1;

  localparam prescale = clk_frequency / baud_rate;

  reg state = STATE_IDLE;
  reg [frame_length - 1:0] data_reg = {frame_length{1'b1}};
  reg [3:0] bit_cnt = 0;
  reg [$clog2(prescale) - 1:0] prescale_reg;

  assign busy = (state != STATE_IDLE);
  assign txd = data_reg[0];

  always @(posedge clk) begin
    if (reset) begin
      state <= STATE_IDLE;
      prescale_reg <= 0;
      data_reg <= {frame_length{1'b1}};
      bit_cnt <= 0;
    end else begin
      if (state == STATE_IDLE) begin
        if (start) begin
          prescale_reg <= 0;
          bit_cnt <= 0;
          data_reg <= {{stop_bits{stop_bit}}, data, start_bit};
          state <= STATE_TX;
        end
      end else begin
        // state == STATE_TX
        prescale_reg <= prescale_reg + 1'b1;
        if (prescale_reg == prescale - 1) begin
          prescale_reg <= 0;
          data_reg <= {stop_bit, data_reg[frame_length - 2:1]};
          bit_cnt <= bit_cnt + 1'b1;
        end
        if (prescale_reg == prescale - 2 && bit_cnt == frame_length - 1) begin
          state <= STATE_IDLE;
        end
      end
    end
  end
endmodule