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  1. /* sim.cfg -- Simulator configuration script file
  2.  
  3. Copyright (C) 2001-2002, Marko Mlinar, markom@opencores.org
  4. Copyright (C) 2010, Embecosm Limited
  5.  
  6. Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
  7.  
  8. This file is part of OpenRISC 1000 Architectural Simulator.
  9.  
  10. This program is free software; you can redistribute it and/or modify it
  11. under the terms of the GNU General Public License as published by the Free
  12. Software Foundation; either version 3 of the License, or (at your option)
  13. any later version.
  14.  
  15. This program is distributed in the hope that it will be useful, but WITHOUT
  16. ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  17. FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  18. more details.
  19.  
  20. You should have received a copy of the GNU General Public License along
  21. with this program. If not, see <http://www.gnu.org/licenses/>. */
  22.  
  23.  
  24. /* -------------------------------------------------------------------------- */
  25. /* The Ork1sim has various parameters, that can be set in configuration files
  26. like this one. The user can specify a configuration file at startu[ with
  27. the -f <filename.cfg> option.
  28.  
  29. The user guide (see the 'doc' directory) gives full details on
  30. configuration files. This is a reference configuration, which may be used
  31. as a starting point for customization.
  32.  
  33. A number of peripherals are mapped at standard addresses (above 0x80000000)
  34. in the Verilog RTL of ORPSoC standard sitribution. The same values should
  35. be used in Or1ksim section definitions to match the behavior of the Verilog
  36.  
  37. 0x90000000 UART
  38. 0x91000000 GPIO
  39. 0x92000000 Ethernet
  40. 0x93000000 Memory controller
  41. 0x94000000 PS2 keyboard
  42. 0x97000000 Frame buffer
  43. 0x97100000 VGA
  44. 0x9a000000 DMA controller
  45. 0x9e000000 ATA disc
  46.  
  47. Section ordering matches that in the user guide. All optional peripherals
  48. and functionality is disabled. Comments only list the possible entries and
  49. values. Consult the user guide for their meaning.
  50.  
  51. Unless otherwise indicated, the first named option is the default. */
  52. /* -------------------------------------------------------------------------- */
  53.  
  54.  
  55. /* Simulator section
  56.  
  57. verbose = 0|1
  58. debug = 0-9
  59. profile = 0|1
  60. prof_file = "<filename>" (default: "sim.profile")
  61. mprofile = 0|1
  62. mprof_file = "<filename>" (default: "sim.mprofile")
  63. history = 0|1
  64. exe_log = 0|1
  65. exe_log_type = hardware|simple|software|default
  66. exe_log_start = <value> (default: 0)
  67. exe_log_end = <value> (default: never end)
  68. exe_log_marker = <value> (default: no markers)
  69. exe_log_file = "<filename>" (default: "executed.log")
  70. exe_bin_insn_log = 0|1
  71. exe_bin_insn_log_file = "<filename>" (default: "exe-insn.bin")
  72. clkcycle = <value>[ps|ns|us|ms]
  73. */
  74. section sim
  75. clkcycle = 100ns
  76. end
  77.  
  78.  
  79. /* VAPI section
  80.  
  81. enabled = 0|1
  82. server_port = <value> (default: 50000)
  83. log_enabled = 0|1
  84. hide_device_id = 0|1
  85. vapi_log_file = "<filename>" (default "vapi.log")
  86. */
  87. section VAPI
  88. server_port = 50000
  89. log_enabled = 0
  90. vapi_log_file = "vapi.log"
  91. end
  92.  
  93.  
  94. /* CUC section
  95.  
  96. memory_order = none|weak|strong|exact (default: strong)
  97. calling_convention = 0|1
  98. enable_bursts = 0|1
  99. no_multicycle = 0|1
  100. timings_file = "<filename>" (default: virtex.tim)
  101. */
  102. section cuc
  103. memory_order = weak
  104. calling_convention = 1
  105. enable_bursts = 1
  106. no_multicycle = 1
  107. end
  108.  
  109.  
  110. /* CPU section
  111.  
  112. ver = <value> (default: 0)
  113. cfg = <value> (default: 0)
  114. rev = <value> (default: 0)
  115. upr = <value> (see user manual for default settings)
  116. cfgr = <value> (default: 0x00000020)
  117. sr = <value> (default: 0x00008001)
  118. superscalar = 0|1
  119. hazards = 0|1
  120. dependstats = 0|1
  121. sbuf_len = <value> (default: 0)
  122. hardfloat = 0|1
  123. */
  124. section cpu
  125. ver = 0x12
  126. cfg = 0x00
  127. rev = 0x0001
  128. end
  129.  
  130.  
  131. /* Memory section
  132.  
  133. type = unknown|random|unknown|pattern
  134. random_seed = <value> (default: -1)
  135. pattern = <value> (default: 0)
  136. baseaddr = <hex_value> (default: 0)
  137. size = <hex_value> (default: 1024)
  138. name = "<string>" (default: "anonymous memory block")
  139. ce = <value> (default: -1)
  140. mc = <value> (default: 0)
  141. delayr = <value> (default: 1)
  142. delayw = <value> (default: 1)
  143. log = "<filename>" (default: NULL)
  144. */
  145. section memory
  146. name = "RAM"
  147. type = unknown
  148. baseaddr = 0x00000000
  149. size = 0x00800000
  150. delayr = 1
  151. delayw = 2
  152. end
  153.  
  154.  
  155. /* Data MMU section
  156.  
  157. enabled = 0|1
  158. nsets = <value> (default: 1)
  159. nways = <value> (default: 1)
  160. pagesize = <value> (default: 8192)
  161. entrysize = <value> (default: 1)
  162. ustates = <value> (default: 1)
  163. hitdelay = <value> (default: 1)
  164. missdelay = <value> (default: 1)
  165. */
  166. section dmmu
  167. enabled = 0
  168. nsets = 64
  169. nways = 1
  170. pagesize = 8192
  171. hitdelay = 0
  172. missdelay = 0
  173. end
  174.  
  175.  
  176. /* Instruction MMU section
  177.  
  178. enabled = 0|1
  179. nsets = <value> (default: 1)
  180. nways = <value> (default: 1)
  181. pagesize = <value> (default: 8192)
  182. entrysize = <value> (default: 1)
  183. ustates = <value> (default: 1)
  184. hitdelay = <value> (default: 1)
  185. missdelay = <value> (default: 1)
  186. */
  187. section immu
  188. enabled = 0
  189. nsets = 64
  190. nways = 1
  191. pagesize = 8192
  192. hitdelay = 0
  193. missdelay = 0
  194. end
  195.  
  196.  
  197. /* Data cache section
  198.  
  199. enabled = 0|1
  200. nsets = <value> (default: 1)
  201. nways = <value> (default: 1)
  202. blocksize = <value> (default: 16)
  203. ustates = <value> (default: 2)
  204. load_hitdelay = <value> (default: 2)
  205. load_missdelay = <value> (default: 2)
  206. store_hitdelay = <value> (default: 0)
  207. store_missdelay = <value> (default: 0)
  208. */
  209.  
  210. section dc
  211. enabled = 0
  212. nsets = 256
  213. nways = 1
  214. blocksize = 16
  215. load_hitdelay = 0
  216. load_missdelay = 0
  217. store_hitdelay = 0
  218. store_missdelay = 0
  219. end
  220.  
  221.  
  222. /* Instruction cache section
  223.  
  224. enabled = 0|1
  225. nsets = <value> (default: 1)
  226. nways = <value> (default: 1)
  227. blocksize = <value> (default: 16)
  228. ustates = <value> (default: 2)
  229. hitdelay = <value> (default: 1)
  230. missdelay = <value> (default: 1)
  231. */
  232. section ic
  233. enabled = 0
  234. nsets = 256
  235. nways = 1
  236. blocksize = 16
  237. hitdelay = 0
  238. missdelay = 0
  239. end
  240.  
  241.  
  242. /* Programmable interrupt controller section
  243.  
  244. enabled = 0|1
  245. edge_trigger = 0|1 (default: 1)
  246. */
  247.  
  248. section pic
  249. enabled = 0
  250. end
  251.  
  252.  
  253. /* Power management section
  254.  
  255. enabled = 0|1
  256. */
  257.  
  258. section pm
  259. enabled = 0
  260. end
  261.  
  262.  
  263. /* Branch prediction section
  264.  
  265. enabled = 0|1
  266. btic = 0|1
  267. sbp_bf_fwd = 0|1
  268. sbp_bnf_fwd = 0|1
  269. hitdelay = <value> (default: 0)
  270. missdelay = <value> (default: 0)
  271. */
  272.  
  273. section bpb
  274. enabled = 0
  275. end
  276.  
  277.  
  278. /* Debug unit section
  279.  
  280. enabled = 0|1
  281. rsp_enabled = 0|1
  282. rsp_port = <value> (default: 51000)
  283. vapi_id = <value> (default: 0)
  284. */
  285. section debug
  286. enabled = 0
  287. end
  288.  
  289.  
  290. /* Memory controller section
  291.  
  292. enabled = 0|1
  293. baseaddr = <value> (default: 0)
  294. POC = <value> (default: 0)
  295. index = <value> (default: 0)
  296. */
  297.  
  298. section mc
  299. enabled = 0
  300. baseaddr = 0x93000000
  301. POC = 0x0000000a /* 32 bit SSRAM */
  302. index = 0
  303. end
  304.  
  305.  
  306. /* UART section
  307.  
  308. enabled = 0|1
  309. baseaddr = <value> (default: 0)
  310. channel = "value>" (default: "xterm:")
  311. irq = <value> (default: 0)
  312. 16550 = 0|1
  313. jitter = <value> (default: 0)
  314. vapi_id = <value> (default: 0)
  315. */
  316.  
  317. section uart
  318. enabled = 0
  319. baseaddr = 0x90000000
  320. irq = 2
  321. 16550 = 1
  322. end
  323.  
  324.  
  325. /* DMA section
  326.  
  327. enabled = 0|1
  328. baseaddr = <value> (default: 0)
  329. irq = <value> (default: 0)
  330. vapi_id = <value> (default: 0)
  331. */
  332. section dma
  333. enabled = 0
  334. baseaddr = 0x9a000000
  335. irq = 11
  336. end
  337.  
  338.  
  339. /* Ethernet section
  340.  
  341. enabled = 0|1
  342. baseaddr = <value> (default: 0)
  343. dma = <value> (default: 0)
  344. irq = <value> (default: 0)
  345. rtx_type = 0|1
  346. rx_channel = <value> (default: 0)
  347. tx_channel = <value> (default: 0)
  348. rxfile = "<filename>" (default: "eth_rx")
  349. txfile = "<filename>" (default: "eth_rx")
  350. sockif = "<service>" (default: "or1ksim_eth")
  351. vapi_id = <value> (default: 0)
  352. */
  353. section ethernet
  354. enabled = 0
  355. baseaddr = 0x92000000
  356. irq = 4
  357. rtx_type = 0
  358. end
  359.  
  360.  
  361. /* GPIO section
  362.  
  363. enabled = 0|1
  364. baseaddr = <value> (default: 0)
  365. irq = <value> (default: 0)
  366. base_vapi_id = <value> (default: 0)
  367. */
  368. section gpio
  369. enabled = 0
  370. baseaddr = 0x91000000
  371. irq = 3
  372. base_vapi_id = 0x0200
  373. end
  374.  
  375. /* VGA section
  376.  
  377. enabled = 0|1
  378. baseaddr = <value> (default: 0)
  379. irq = <value> (default: 0)
  380. refresh_rate = <value> (default: cycles equivalent to 50Hz)
  381. filename = "<filename>" (default: "vga_out))
  382. */
  383. section vga
  384. enabled = 0
  385. baseaddr = 0x97100000
  386. irq = 8
  387. end
  388.  
  389.  
  390. /* Frame buffer section
  391.  
  392. enabled = 0|1
  393. baseaddr = <value> (default: 0)
  394. refresh_rate = <value> (default: cycles equivalent to 50Hz)
  395. filename = "<filename>" (default: "fb_out))
  396. */
  397. section fb
  398. enabled = 0
  399. baseaddr = 0x97000000
  400. end
  401.  
  402.  
  403. /* PS2 keyboard section
  404.  
  405. This section configures the PS/2 compatible keyboard
  406.  
  407. enabled = 0|1
  408. baseaddr = <value> (default: 0)
  409. irq = <value> (default: 0)
  410. rxfile = "<filename>" (default: "kbd_in")
  411. */
  412. section kbd
  413. enabled = 1
  414. baseaddr = 0x94000000
  415. irq = 5
  416. end
  417.  
  418.  
  419. /* ATA disc section
  420.  
  421. enabled = 0|1
  422. baseaddr = <value> (default: 0)
  423. irq = <value> (default: 0)
  424. dev_id = 1|2|3
  425. rev = 0-15 (default: 1)
  426. pio_mode0_t1 = 0-255 (default: 6)
  427. pio_mode0_t2 = 0-255 (default: 28)
  428. pio_mode0_t4 = 0-255 (default: 2)
  429. pio_mode0_teoc = 0-255 (default: 23)
  430. dma_mode0_tm = 0-255 (default: 4)
  431. dma_mode0_td = 0-255 (default: 21)
  432. dma_mode0_teoc = 0-255 (default: 21)
  433. device = 0|1
  434.  
  435. Device specific:
  436.  
  437. type = 0|1|2
  438. file = "<filename>" (default: "ata_file<type>")
  439. size = <value> (default: 0)
  440. packet = 0|1
  441. firmware = "<string>" (default: "02207031")
  442. heads = <value> (default: 7)
  443. sectors = <value> (default: 32)
  444. mwdma = 2|1|0|-1
  445. pio = 4|3|2|1|0
  446. */
  447. section ata
  448. enabled = 0
  449. baseaddr = 0x9e000000
  450. irq = 15
  451.  
  452. device 0
  453. type = 1
  454. size = 1
  455. enddevice
  456. end
  457.  
  458.  
  459. /* Generic peripheral section
  460.  
  461. enabled = 0|1
  462. baseaddr = <value> (default: 0)
  463. size = <value> (default: 0)
  464. name = "<string>" (default: "anonymous external peripheral")
  465. byte_enabled = 1|0
  466. hw_enabled = 1|0
  467. word_enabled = 1|0
  468. */
  469. section generic
  470. enabled = 0
  471. end
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