`timescale 1ns/1ps

module counter_test;

int start;
logic clk,rst;
logic [3:0] result;

initial begin
    clk=0;
    forever #10 clk = ~clk;
end



initial
begin
    start = 6;
    rst=0;
    #10 rst=1;
    repeat(16) #20 $strobe("Counter value: %d", result);
    #100 rst=0;
    #10 rst=1;
    #100 $stop;
end

bin_cnt test_dev(clk, rst,start,  result);

endmodule




module bin_cnt
(
    input logic clk, resetn,
    int start,
    output logic [3:0] count
);

int it;
logic cond;

    always @ (posedge clk or negedge resetn)
    begin

        if (!resetn)
            begin
                count <= 0;
                it = 0;
                cond = 1;
            end
        else
            if(cond)
            if (count==(start-it))
                begin
                    if((start-it)<=(it+1))
                        begin
                            cond = 0;
                            count <= count - 1;
                        end
                    else
                    count <= it++;
                    //it++;
                end
            else
                begin
                    count <= count + 1;
                end
    end

endmodule