zombah

picasso 4.3-downstream paz00 patch

Nov 7th, 2015
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  1. diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
  2. index ed7e100..36b1465 100644
  3. --- a/arch/arm/boot/dts/tegra20-paz00.dts
  4. +++ b/arch/arm/boot/dts/tegra20-paz00.dts
  5. @@ -1,5 +1,7 @@
  6. /dts-v1/;
  7.  
  8. +/memreserve/ 0x16800000 0x9800000;
  9. +
  10. #include <dt-bindings/input/input.h>
  11. #include "tegra20.dtsi"
  12.  
  13. @@ -18,14 +20,36 @@
  14. reg = <0x00000000 0x20000000>;
  15. };
  16.  
  17. - host1x@50000000 {
  18. - dc@54200000 {
  19. - rgb {
  20. - status = "okay";
  21. + nvmap {
  22. + compatible = "nvidia,tegra-nvmap";
  23. + #address-cells = <1>;
  24. + #size-cells = <1>;
  25. + ranges;
  26. +
  27. + carveouts {
  28. + #address-cells = <1>;
  29. + #size-cells = <1>;
  30. + ranges;
  31.  
  32. - nvidia,panel = <&panel>;
  33. + iram {
  34. + reg = <0x40000400 0x3FC00>;
  35. + reg-names = "iram";
  36. + buddy-size = <0>;
  37. + usage-mask = <0x20000000>;
  38. + };
  39. +
  40. + generic {
  41. + reg = <0x18000000 0x8000000>;
  42. + reg-names = "generic-0";
  43. + buddy-size = <0x8000>;
  44. + usage-mask = <0x1>;
  45. };
  46. };
  47. + };
  48. +
  49. + host1x@50000000 {
  50. + compatible = "nvidia,tegra20-host1x", "nvhost-bus";
  51. + ranges;
  52.  
  53. hdmi@54280000 {
  54. status = "okay";
  55. @@ -37,6 +61,109 @@
  56. nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
  57. GPIO_ACTIVE_HIGH>;
  58. };
  59. +
  60. + mpe@54040000 {
  61. + clock-names = "mpe";
  62. + };
  63. +
  64. + gr3d@54180000 {
  65. + clock-names = "gr3d";
  66. + };
  67. +
  68. + gr2d@54140000 {
  69. + clocks = <&tegra_car TEGRA20_CLK_GR2D>,
  70. + <&tegra_car TEGRA20_CLK_EPP>;
  71. + clock-names = "gr2d", "epp";
  72. + };
  73. +
  74. + epp@540c0000 {
  75. + clock-names = "epp";
  76. + };
  77. +
  78. + dc@54200000 {
  79. + reg = <0x54200000 0x00040000>,
  80. + <0x16800000 0x800000>;
  81. + reg-names = "regs", "fbmem";
  82. + interrupt-names = "irq";
  83. +
  84. + pnl-vdd-supply = <&vdd_pnl_reg>;
  85. +
  86. + rgb {
  87. + status = "okay";
  88. +
  89. + display {
  90. + fb-win = <0>;
  91. + fb-xres = <1024>;
  92. + fb-yres = <600>;
  93. + fb-bpp = <32>;
  94. +
  95. + dc-index = <0>;
  96. +
  97. + flags = <1>; /* TEGRA_DC_FLAG_ENABLED */
  98. +
  99. + type = <0>; /* TEGRA_DC_OUT_RGB */
  100. + order = <0>; /* TEGRA_DC_ORDER_RED_BLUE */
  101. + align = <0>; /* TEGRA_DC_ALIGN_MSB */
  102. + depth = <18>;
  103. + dither = <3>; /* TEGRA_DC_ERRDIFF_DITHER */
  104. +
  105. + default-emc-rate = <600000000>;
  106. + min-emc-rate = <300000000>;
  107. +
  108. + display-timings {
  109. + native-mode = <&timing0>;
  110. + timing0: 1024x600 {
  111. + clock-frequency = <54030000>;
  112. + hactive = <1024>;
  113. + vactive = <600>;
  114. + hfront-porch = <24>;
  115. + hback-porch = <160>;
  116. + hsync-len = <136>;
  117. + vsync-len = <6>;
  118. + vfront-porch = <3>;
  119. + vback-porch = <61>;
  120. + };
  121. + };
  122. + };
  123. + };
  124. + };
  125. +
  126. + dc@54240000 {
  127. + reg = <0x54240000 0x00040000>,
  128. + <0x54280000 0x00040000>,
  129. + <0x17000000 0x01000000>;
  130. + reg-names = "regs", "hdmi_regs", "fbmem";
  131. + clocks = <&tegra_car TEGRA20_CLK_DISP2>,
  132. + <&tegra_car TEGRA20_CLK_HDMI>,
  133. + <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
  134. + clock-names = "dc", "hdmi", "parent";
  135. + resets = <&tegra_car TEGRA20_CLK_DISP2>,
  136. + <&tegra_car TEGRA20_CLK_HDMI>;
  137. + reset-names = "dc", "hdmi";
  138. + interrupt-names = "irq";
  139. +
  140. + hdmi-vdd-supply = <&hdmi_vdd_reg>;
  141. + hdmi-pll-supply = <&hdmi_pll_reg>;
  142. +
  143. + rgb {
  144. + status = "okay";
  145. +
  146. + display {
  147. + fb-win = <0>;
  148. + fb-xres = <1280>;
  149. + fb-yres = <800>;
  150. + fb-bpp = <32>;
  151. +
  152. + dc-index = <1>;
  153. +
  154. + type = <1>; /* TEGRA_DC_OUT_HDMI */
  155. + order = <0>; /* TEGRA_DC_ORDER_RED_BLUE */
  156. + align = <0>; /* TEGRA_DC_ALIGN_MSB */
  157. + dc-flags = <0>; /* TEGRA_DC_OUT_HOTPLUG_HIGH */
  158. + max-clock = <148500>;
  159. + };
  160. + };
  161. + };
  162. };
  163.  
  164. pinmux@70000014 {
  165. @@ -448,6 +575,7 @@
  166. };
  167.  
  168. usb@c5000000 {
  169. + compatible = "nvidia,tegra20-udc";
  170. status = "okay";
  171. };
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