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  1. From caed7b8e9372681e918e7f1e791cbb1e390b5ba6 Mon Sep 17 00:00:00 2001
  2. From: Laine Walker-Avina <lwalkera@ieee.org>
  3. Date: Mon, 13 Sep 2010 12:43:33 -0700
  4. Subject: [PATCH 2/3] OMAP: Add support for the EHCI module
  5.  
  6. ---
  7. drivers/usb/host/Makefile | 1 +
  8. drivers/usb/host/ehci-omap3.c | 217 +++++++++++++++++++++++++++++++++++++++++
  9. drivers/usb/host/ehci.h | 4 +-
  10. 3 files changed, 220 insertions(+), 2 deletions(-)
  11. create mode 100644 drivers/usb/host/ehci-omap3.c
  12.  
  13. diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
  14. index 255679a..33f818d 100644
  15. --- a/drivers/usb/host/Makefile
  16. +++ b/drivers/usb/host/Makefile
  17. @@ -41,6 +41,7 @@ COBJS-$(CONFIG_USB_EHCI_IXP4XX) += ehci-ixp.o
  18. COBJS-$(CONFIG_USB_EHCI_KIRKWOOD) += ehci-kirkwood.o
  19. COBJS-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
  20. COBJS-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
  21. +COBJS-$(CONFIG_USB_EHCI_OMAP3) += ehci-omap3.o
  22.  
  23. COBJS := $(COBJS-y)
  24. SRCS := $(COBJS:.o=.c)
  25. diff --git a/drivers/usb/host/ehci-omap3.c b/drivers/usb/host/ehci-omap3.c
  26. new file mode 100644
  27. index 0000000..9bfd9da
  28. --- /dev/null
  29. +++ b/drivers/usb/host/ehci-omap3.c
  30. @@ -0,0 +1,217 @@
  31. +/*
  32. + * (C) Copyright 2009
  33. + * PASCO scientific <http://pasco.com>
  34. + * Written-by: Laine Walker-Avina <lwalkera@pasco.com>
  35. + *
  36. + * See file CREDITS for list of people who contributed to this
  37. + * project.
  38. + *
  39. + * This program is free software; you can redistribute it and/or
  40. + * modify it under the terms of the GNU General Public License as
  41. + * published by the Free Software Foundation; either version 2 of
  42. + * the License, or (at your option) any later version.
  43. + *
  44. + * This program is distributed in the hope that it will be useful,
  45. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  46. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  47. + * GNU General Public License for more details.
  48. + *
  49. + * You should have received a copy of the GNU General Public License
  50. + * along with this program; if not, write to the Free Software
  51. + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  52. + * MA 02110-1301 USA
  53. + */
  54. +#define DEBUG 1
  55. +#include <common.h>
  56. +#include <asm/io.h>
  57. +#include <usb.h>
  58. +#include "ehci.h"
  59. +#include "ehci-core.h"
  60. +#include <asm/arch/omap3.h>
  61. +
  62. +/* USB/EHCI registers */
  63. +#define OMAP3_USBTLL_BASE 0x48062000
  64. +#define OMAP3_UHH_BASE 0x48064000
  65. +#define OMAP3_EHCI_BASE 0x48064800
  66. +
  67. +#define REVISION 0x0
  68. +#define SYSCONFIG 0x10
  69. +#define SYSSTATUS 0x14
  70. +
  71. +#define ENAWAKEUP (1<<2)
  72. +#define SIDLEMODE_NOIDLE (1<<3)
  73. +#define CACTIVITY (1<<8)
  74. +#define MIDLEMODE_NOIDLE (1<<12)
  75. +#define AUTOIDLE (1<<0)
  76. +
  77. +#define UHH_HOSTCONFIG 0x40
  78. +#define UHH_DEBUG_CSR 0x44
  79. +
  80. +#define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN (1 << 2)
  81. +#define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN (1 << 3)
  82. +#define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN (1 << 4)
  83. +#define OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN (1 << 5)
  84. +#define OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS (1 << 8)
  85. +#define OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS (1 << 9)
  86. +#define OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS (1 << 10)
  87. +#define OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS (1 << 0)
  88. +#define OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS (1 << 11)
  89. +#define OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS (1 << 12)
  90. +
  91. +#define EHCI_INSNREG04 (0xA0)
  92. +#define EHCI_INSNREG04_DISABLE_UNSUSPEND (1 << 5)
  93. +#define EHCI_INSNREG05_ULPI (0xA4)
  94. +#define EHCI_INSNREG05_ULPI_CONTROL_SHIFT 31
  95. +#define EHCI_INSNREG05_ULPI_PORTSEL_SHIFT 24
  96. +#define EHCI_INSNREG05_ULPI_OPSEL_SHIFT 22
  97. +#define EHCI_INSNREG05_ULPI_REGADD_SHIFT 16
  98. +#define EHCI_INSNREG05_ULPI_EXTREGADD_SHIFT 8
  99. +#define EHCI_INSNREG05_ULPI_WRDATA_SHIFT 0
  100. +
  101. +/* ULPI */
  102. +
  103. +#define ULPI_SET(a) (a + 1)
  104. +#define ULPI_CLR(a) (a + 2)
  105. +
  106. +/*
  107. + * Register Map
  108. + */
  109. +#define ULPI_VENDOR_ID_LOW 0x00
  110. +#define ULPI_VENDOR_ID_HIGH 0x01
  111. +#define ULPI_PRODUCT_ID_LOW 0x02
  112. +#define ULPI_PRODUCT_ID_HIGH 0x03
  113. +#define ULPI_FUNC_CTRL 0x04
  114. +#define ULPI_IFC_CTRL 0x07
  115. +#define ULPI_OTG_CTRL 0x0a
  116. +#define ULPI_USB_INT_EN_RISE 0x0d
  117. +#define ULPI_USB_INT_EN_FALL 0x10
  118. +#define ULPI_USB_INT_STS 0x13
  119. +#define ULPI_USB_INT_LATCH 0x14
  120. +#define ULPI_DEBUG 0x15
  121. +#define ULPI_SCRATCH 0x16
  122. +/* Optional Carkit Registers */
  123. +#define ULPI_CARCIT_CTRL 0x19
  124. +#define ULPI_CARCIT_INT_DELAY 0x1c
  125. +#define ULPI_CARCIT_INT_EN 0x1d
  126. +#define ULPI_CARCIT_INT_STS 0x20
  127. +#define ULPI_CARCIT_INT_LATCH 0x21
  128. +#define ULPI_CARCIT_PLS_CTRL 0x22
  129. +/* Other Optional Registers */
  130. +#define ULPI_TX_POS_WIDTH 0x25
  131. +#define ULPI_TX_NEG_WIDTH 0x26
  132. +#define ULPI_POLARITY_RECOVERY 0x27
  133. +/* Access Extended Register Set */
  134. +#define ULPI_ACCESS_EXTENDED 0x2f
  135. +/* Vendor Specific */
  136. +#define ULPI_VENDOR_SPECIFIC 0x30
  137. +/* Extended Registers */
  138. +#define ULPI_EXT_VENDOR_SPECIFIC 0x80
  139. +
  140. +#define ULPI_FUNC_CTRL_RESET (1 << 5)
  141. +
  142. +
  143. +#define HW(x) *((volatile unsigned int *)(x))
  144. +
  145. +static void omap_ehci_soft_phy_reset(u8 port)
  146. +{
  147. + unsigned reg = 0;
  148. +
  149. + debug("PHY reset\n");
  150. +
  151. + reg = ULPI_FUNC_CTRL_RESET
  152. + /* FUNCTION_CTRL_SET register */
  153. + | (ULPI_SET(ULPI_FUNC_CTRL) << EHCI_INSNREG05_ULPI_REGADD_SHIFT)
  154. + /* Write */
  155. + | (2 << EHCI_INSNREG05_ULPI_OPSEL_SHIFT)
  156. + /* PORTn */
  157. + | ((port + 1) << EHCI_INSNREG05_ULPI_PORTSEL_SHIFT)
  158. + /* start ULPI access*/
  159. + | (1 << EHCI_INSNREG05_ULPI_CONTROL_SHIFT);
  160. +
  161. + HW(OMAP3_EHCI_BASE+EHCI_INSNREG05_ULPI) = reg;
  162. +
  163. + /* Wait for ULPI access completion */
  164. + while (HW(OMAP3_EHCI_BASE+EHCI_INSNREG05_ULPI)
  165. + & (1 << EHCI_INSNREG05_ULPI_CONTROL_SHIFT));
  166. +}
  167. +
  168. +/*
  169. + * Create the appropriate control structures to manage
  170. + * a new EHCI host controller.
  171. + */
  172. +int ehci_hcd_init(void)
  173. +{
  174. + unsigned int reg;
  175. +
  176. + debug("Initializing OMAP3 ECHI\n");
  177. +
  178. + // USBTLL soft reset
  179. + HW(OMAP3_USBTLL_BASE+SYSCONFIG) |= SOFTRESET;
  180. + while(!(HW(OMAP3_USBTLL_BASE+SYSSTATUS) & RESETDONE));
  181. + debug("TLL reset done\n");
  182. +
  183. + //Force UHH and TLL no-idle
  184. + HW(OMAP3_USBTLL_BASE+SYSCONFIG) =
  185. + ENAWAKEUP | SIDLEMODE_NOIDLE | CACTIVITY;
  186. +
  187. + reg = HW(OMAP3_UHH_BASE + SYSCONFIG);
  188. + reg |= ENAWAKEUP | SIDLEMODE_NOIDLE | CACTIVITY | MIDLEMODE_NOIDLE;
  189. + reg &= ~AUTOIDLE;
  190. + HW(OMAP3_UHH_BASE + SYSCONFIG) = reg;
  191. +
  192. + //setup PHY interface
  193. + reg = HW(OMAP3_UHH_BASE + UHH_HOSTCONFIG);
  194. + reg |= ( OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN
  195. + | OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN
  196. + | OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN);
  197. + reg &= ~OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN;
  198. + reg &= ~(OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS |
  199. + OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS |
  200. + OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS);
  201. + reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
  202. + HW(OMAP3_UHH_BASE + UHH_HOSTCONFIG) = reg;
  203. +
  204. +
  205. + /*
  206. + * An undocumented "feature" in the OMAP3 EHCI controller,
  207. + * causes suspended ports to be taken out of suspend when
  208. + * the USBCMD.Run/Stop bit is cleared (for example when
  209. + * we do ehci_bus_suspend).
  210. + * This breaks suspend-resume if the root-hub is allowed
  211. + * to suspend. Writing 1 to this undocumented register bit
  212. + * disables this feature and restores normal behavior.
  213. + */
  214. + HW(OMAP3_EHCI_BASE+EHCI_INSNREG04) = EHCI_INSNREG04_DISABLE_UNSUSPEND;
  215. +
  216. + //omap_ehci_soft_phy_reset(1);
  217. +
  218. + hccr = (struct ehci_hccr *)(OMAP3_EHCI_BASE);
  219. + hcor = (struct ehci_hcor *)(OMAP3_EHCI_BASE + 0x10);
  220. +
  221. + debug("OMAP3-ehci: init \n");
  222. +
  223. + return 0;
  224. +}
  225. +
  226. +/*
  227. + * Destroy the appropriate control structures corresponding
  228. + * the the EHCI host controller.
  229. + */
  230. +int ehci_hcd_stop(void)
  231. +{
  232. + /* Reset OMAP modules */
  233. + debug("Resetting OMAP USBH\n");
  234. + HW(OMAP3_UHH_BASE+SYSCONFIG) = SOFTRESET;
  235. + while (!(HW(OMAP3_UHH_BASE+SYSSTATUS) & (1 << 0)));
  236. + debug("USB Host reset\n");
  237. + while (!(HW(OMAP3_UHH_BASE+SYSSTATUS) & (1 << 1)));
  238. + debug("OHCI reset\n");
  239. + while (!(HW(OMAP3_UHH_BASE+SYSSTATUS) & (1 << 2)));
  240. + debug("EHCI reset\n");
  241. +
  242. + debug("Resetting OMAP USBTLL\n");
  243. + HW(OMAP3_USBTLL_BASE+SYSCONFIG) = 1<<1;
  244. + while (!(HW(OMAP3_USBTLL_BASE+SYSSTATUS) & (1 << 0)));
  245. +
  246. + return 0;
  247. +}
  248. diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h
  249. index b3c1d5d..cd59eac 100644
  250. --- a/drivers/usb/host/ehci.h
  251. +++ b/drivers/usb/host/ehci.h
  252. @@ -55,7 +55,7 @@ struct ehci_hccr {
  253. #define HCS_N_PORTS(p) (((p) >> 0) & 0xf)
  254. uint32_t cr_hccparams;
  255. uint8_t cr_hcsp_portrt[8];
  256. -} __attribute__ ((packed));
  257. +} __attribute__ ((packed,aligned(4)));
  258.  
  259. struct ehci_hcor {
  260. uint32_t or_usbcmd;
  261. @@ -80,7 +80,7 @@ struct ehci_hcor {
  262. #define FLAG_CF (1 << 0) /* true: we'll support "high speed" */
  263. uint32_t or_portsc[CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS];
  264. uint32_t or_systune;
  265. -} __attribute__ ((packed));
  266. +} __attribute__ ((packed, aligned(4)));
  267.  
  268. #define USBMODE 0x68 /* USB Device mode */
  269. #define USBMODE_SDIS (1 << 3) /* Stream disable */
  270. --
  271. 1.6.3.3
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