DEF MUX21
  PORT IN I0
  PORT IN I1
  PORT IN S
  PORT IN NS
  PORT OUT Z
  NET T1
  NET T2
  INST AN1 NAND NS I0 T1
  INST AN2 NAND S  I1 T2
  INST OUT NAND T1 T2 Z
ENDDEF

DEF MUX21x8
  PORT IN I0<7:0>
  PORT IN I1<7:0>
  PORT IN S
  PORT IN NS
  PORT OUT Z<7:0>
  INST MUX21 I0<7> I1<7> S NS Z<7>
  INST MUX21 I0<6> I1<6> S NS Z<6>
  INST MUX21 I0<5> I1<5> S NS Z<5>
  INST MUX21 I0<4> I1<4> S NS Z<4>
  INST MUX21 I0<3> I1<3> S NS Z<3>
  INST MUX21 I0<2> I1<2> S NS Z<2>
  INST MUX21 I0<1> I1<1> S NS Z<1>
  INST MUX21 I0<0> I1<0> S NS Z<0>
ENDDEF